A solar cell and its preparation method

Abstract

This invention relates to a solar cell and its fabrication method. The fabrication method includes the following steps: S1 cleaning and polishing a silicon substrate; S2 forming a dielectric region and a polycrystalline silicon layer; S3 forming a dopant source layer for impurities of a first conductivity type; S4 co-doping with impurities of different conductivity types in one step; S5 forming a dielectric layer; S6 metallization; the thickness of the dopant source layer for the first conductivity type impurities is 10nm-100nm. This invention, by first forming the dopant source layer for the first conductivity type impurities, reduces the number of high-temperature doping and cleaning cycles, lowers the doping temperature, shortens the process time, simplifies the process flow, reduces equipment investment costs, and reduces internal recombination in the solar cell, thereby improving photoelectric conversion efficiency.

Description

Technical Field

[0001] This invention relates to the field of solar cells, and in particular to a solar cell and a method for its fabrication. Background Technology

[0002] TOPCon (Tunnel Oxide Passivated Contact) is a solar cell technology based on the selective carrier principle of tunneling oxide passivated contact. Its cell structure is an N-type or P-type silicon substrate cell, with an ultra-thin oxide layer prepared on the back side, and then a doped silicon thin layer is formed. The two together form a passivated contact structure, which effectively reduces surface recombination and metal contact recombination.

[0003] There are currently two main production technologies for TOPCon cells: LPCVD (Low Pressure Chemical Vapor Deposition) and PECVD (Plasma Enhanced Chemical Vapor Deposition). The typical process for TOPCon cell fabrication includes the following steps: texturing – boron doping – BSG (borosilicate glass) removal and alkaline polishing – formation of tunneling oxide and poly oxide layers using LPCVD or PECVD – phosphorus doping – BSG, PSG (phosphosilicate glass) removal and RCA (industry-standard wet cleaning process) cleaning – ALD (atomic layer formation) – front and back antireflective coatings – metallization. Conventional fabrication routes for TOPCon cells are limited by the different doping sources, temperatures, and times in the P and N regions. Typically, boron doping is performed before phosphorus doping. However, this route has the following drawbacks: 1. A thick layer of BSG (bipolar silicon gas precipitate) needs to be grown before phosphorus doping, usually greater than 100 nm, to block alkaline polishing and the alkaline washing tank within the RCA (radioactive aluminum alloy). The thicker BSG also results in a higher oxygen content in the silicon wafer, leading to severe boron-oxygen recombination, which reduces photoelectric conversion efficiency and causes light-induced degradation. 2. The cell fabrication process requires two high-temperature processes (phosphorus doping and boron doping) and two removal processes, making the process cumbersome, time-consuming, and costly in terms of equipment investment. 3. Most TOPCon cells are produced using a single-insertion configuration, reducing production capacity. Summary of the Invention

[0004] The present invention addresses the aforementioned problems and overcomes the shortcomings of the prior art by providing a solar cell and its fabrication method to solve the problems mentioned in the background art.

[0005] The first aspect of the present invention provides a method for preparing a solar cell, comprising the following steps:

[0006] S1 cleans and polishes the substrate silicon wafer;

[0007] S2 forms the dielectric region and the polysilicon layer;

[0008] S3 forms a dopant source layer for impurities of the first conductivity type;

[0009] S4 is co-doped with impurities of different conductivity types in one step;

[0010] S5 forms a dielectric layer;

[0011] S6 metallization;

[0012] The thickness of the dopant source layer of the first type of conductivity impurity is 10nm-100nm.

[0013] Preferably, the thickness of the dopant source layer for the first type of conductivity impurity is 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm. More preferably, the thickness of the dopant source layer for the first type of conductivity impurity is 50nm-100nm.

[0014] In this invention, the thickness of the dopant source layer of the first type of conductivity impurity is 10nm-100nm. When the thickness is less than 10nm, it cannot effectively act as a barrier layer for the second type of conductivity impurity, resulting in severe recombination and a decrease in photoelectric conversion efficiency. When the thickness is greater than 100nm, it will result in a high oxygen content in the silicon wafer, leading to severe recombination, a decrease in photoelectric conversion efficiency, and light-induced degradation.

[0015] The dopant source layer of the first conductivity type impurity needs to have a certain thickness. The purpose is to ensure that the first doping region has sufficient doping concentration after one-step co-doping, and to act as a mask layer to prevent the dopant of the second conductivity type impurity from doping into the first doping region, while also preventing the opening of the film from damaging the polysilicon or c-Si. The complete removal of the dopant source layer of the first conductivity type impurity and the dopant source layer of the second conductivity type impurity will be completely removed in the subsequent RCA cleaning step.

[0016] Preferably, the solar cell includes a substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, wherein the dielectric region and the polycrystalline silicon layer are sequentially disposed on the back side of the substrate silicon wafer in a direction away from the substrate silicon wafer, and a dopant source layer of the first conductivity type impurity is located outside the polycrystalline silicon layer.

[0017] Preferably, the preparation method further includes a texturing step, wherein the texturing step forms a front textured surface on the front side of the substrate silicon wafer, or the texturing step forms a front textured surface on the front side of the substrate silicon wafer and a partial back textured surface on the back side, wherein the morphology and size of the front textured surface and the partial back textured surface are the same or different.

[0018] Preferably, the texturing step is performed before the formation of the dielectric region and polysilicon layer in S2, and the texturing step further includes a mask preparation step, in which a mask layer is formed on the back side of the substrate silicon wafer; or, the texturing step is performed after the formation of the dopant source layer of the first conductivity type impurity in S3.

[0019] Preferably, the substrate silicon wafer in S1 is N-type or P-type.

[0020] Preferably, in the S3 formation of the dopant source layer of the first conductivity type impurity, the formation is carried out by CVD at a temperature of 300℃-800℃ for 1min-90min. The raw materials include boron source gas or phosphorus source gas. The boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0021] Preferably, the raw materials further include other gases, which are one or more of SiH4, N2O, NH3, and Ar.

[0022] Preferably, in step S3, which forms a dopant source layer of a first conductivity type impurity, the dopant source layer of the first conductivity type impurity is a silicon-containing compound layer containing a first conductivity type impurity, and the first conductivity type impurity is boron, gallium, or phosphorus.

[0023] Preferably, in the step-by-step co-doping of impurities of different conductivity types in S4, a doping source of a second conductivity type impurity with an electrical polarity opposite to that of the first conductivity type impurity is used, thereby simultaneously forming a first conductivity type impurity region and a second conductivity type impurity region. The first conductivity type impurity region and the second conductivity type impurity region have opposite electrical polarities, and the step-by-step co-doping of impurities of different conductivity types is performed at least once.

[0024] Preferably, the doping source of the second type of conductivity impurity is a boron source gas or a phosphorus source gas, wherein the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0025] Preferably, the doping temperature for one-step co-doping of impurities of different conductivity types in S4 is 600℃-1000℃, more preferably, the doping temperature is 600℃-980℃, and the doping time is 5min-180min, wherein the doping time does not include the time required for heating and cooling.

[0026] Preferably, after the S4 step of co-doping with impurities of different conductivity types, laser selective doping is further included. The wavelength of the laser selective doping is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, and the frequency is 200kHz-2000kHz. The laser selective doping obtains a locally heavily doped region in the region of the conductivity type impurities.

[0027] Preferably, after laser selective doping, the process further includes a dopant source layer for removing impurities of the first conductivity type. The dopant source layer for removing impurities of the first conductivity type is acid-washed with hydrofluoric acid at a concentration of 0.5%-50% for a washing time of 10s-1200s.

[0028] A second aspect of the present invention also provides a solar cell, including a silicon substrate wafer; the silicon substrate wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the silicon substrate wafer having a front textured surface, a second conductivity type impurity region, a second dielectric layer and a front metal electrode; the back side of the silicon substrate wafer having a first dielectric region, a first conductivity type impurity region, a first dielectric layer and a back metal electrode;

[0029] The first dielectric region is a first tunneling oxide layer; the first conductivity type impurity region is a c-Si region or a polysilicon layer doped with a first conductivity type impurity; and the second conductivity type impurity region is a c-Si region or a polysilicon layer doped with a second conductivity type impurity.

[0030] The dopant source layer of the first type of conductivity impurity serves as the dopant source of the c-Si region or polysilicon layer of the first type of conductivity impurity, and the thickness of the dopant source layer of the first type of conductivity impurity is 10nm-100nm.

[0031] The second conductivity type impurity region and the first conductivity type impurity region are formed simultaneously in one or more one-step co-doping steps of impurities of different conductivity types;

[0032] At least once in the one-step co-doping step of the impurities of different conductivity types, a doping source having a second conductivity type that is opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer;

[0033] The first type of conductivity impurity region has the opposite electrical properties to the second type of conductivity impurity region, and a local region of the back metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

[0034] Preferably, a second dielectric region is further provided on the front textured surface in the direction away from the substrate silicon wafer; a back partial textured surface and an edge textured surface are further provided below the first dielectric region in the direction close to the substrate silicon wafer, and a heavily doped region is further provided in the first conductivity type impurity region and / or the second conductivity type impurity region.

[0035] Preferably, the c-Si region is formed by a film-opening and cleaning process, wherein the film-opening process is at least one of laser, etching paste, and photolithography; and the polycrystalline silicon layer is formed by CVD (Chemical Vapor Deposition) deposition.

[0036] A second aspect of the present invention provides another solar cell, the solar cell comprising a substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite the front side, wherein the front side of the substrate silicon wafer is provided with, from the inside to the outside, a front textured surface, a second conductivity type impurity region, a second dielectric layer, and a front metal electrode; and the back side of the substrate silicon wafer is provided with, from the inside to the outside, a first dielectric region, a first conductivity type impurity region, a first dielectric layer, and a back metal electrode.

[0037] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with the second type of conductivity impurity region; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with the first type of conductivity impurity region.

[0038] The first dielectric region is a first tunneling oxide layer; the first conductivity type impurity region is a c-Si region or polysilicon layer doped with a first conductivity type impurity, and the second conductivity type impurity region is a c-Si region or polysilicon layer doped with a second conductivity type impurity.

[0039] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0040] This invention improves photoelectric conversion efficiency by first forming a dopant source layer for impurities of the first conductivity type, thereby reducing the number of high-temperature doping and cleaning cycles, lowering the doping temperature, shortening the process time, simplifying the process flow, reducing equipment investment costs, and reducing internal recombination in solar cells. Specifically, by first forming a dopant source layer for impurities of the first conductivity type, this invention allows the dopant source layer formed during one-step co-doping of impurities of different conductivity types to serve as both a doping source and a barrier layer during the doping of another element. This achieves simultaneous high-temperature doping of impurities of different conductivity types in one step to form a region of the first conductivity type impurity. In the second conductivity type impurity region, only one high-temperature doping is required, reducing the number of high-temperature doping steps. Since this invention only involves one co-doping step, a thick BSG layer is not needed before phosphorus doping to block the alkaline polishing and RCA washing tanks, thus reducing the oxygen content of the silicon wafer, reducing the recombination effect inside the solar cell, and improving the photoelectric conversion efficiency. Since the conventional production line route is boron doping first and then phosphorus doping, the boron doping temperature is as high as 1000℃, requiring high temperature to grow a thick oxide layer and advance boron doping. However, the preparation route of this invention does not require the growth of a thick oxide layer, eliminating the high-temperature boron doping process, simplifying the process flow, and reducing equipment investment costs. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the TOPCon battery structure in Example 1;

[0042] Figure 2 This is a flowchart of the TOPCon battery fabrication process in Example 1;

[0043] Figure 3 This is a schematic diagram of the TOPCon battery structure in Example 9;

[0044] Figure 4 The flowcharts are for the TOPCon battery fabrication process in Examples 9 and 15-16.

[0045] Figure 5 This is a schematic diagram of the TOPCon battery structure in Example 15;

[0046] Figure 6 This is a schematic diagram of the TOPCon battery structure in Example 16.

[0047] In the figure: 1-front metal electrode, 2-second dielectric layer, 3-second conductivity type impurity polysilicon layer, 4-N-type silicon wafer, 5-first tunneling oxide layer, 6-first conductivity type impurity polysilicon layer, 7-first dielectric layer, 8-back metal electrode, 9-heavily doped region of second conductivity type impurity polysilicon layer, 10-second tunneling oxide layer, 11-second conductivity type impurity c-Si region, 12-first conductivity type impurity c-Si region, 13-heavily doped region of first conductivity type impurity polysilicon layer. Detailed Implementation

[0048] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0049] This embodiment provides a method for preparing a solar cell, including the following steps:

[0050] S1 cleans and polishes the substrate silicon wafer;

[0051] S2 forms the dielectric region and the polysilicon layer;

[0052] S3 forms a dopant source layer for impurities of the first conductivity type;

[0053] S4 is co-doped with impurities of different conductivity types in one step;

[0054] S5 forms a dielectric layer;

[0055] S6 metallization;

[0056] The thickness of the dopant source layer of the first type of conductivity impurity is 10nm-100nm.

[0057] This invention improves photoelectric conversion efficiency by first forming a dopant source layer for impurities of the first conductivity type, thereby reducing the number of high-temperature doping and cleaning cycles, lowering the doping temperature, shortening the process time, simplifying the process flow, reducing equipment investment costs, and reducing internal recombination in solar cells. Specifically, by first forming a dopant source layer for impurities of the first conductivity type, this invention allows the dopant source layer formed during one-step co-doping of impurities of different conductivity types to serve as both a doping source and a barrier layer during the doping of another element. This achieves simultaneous high-temperature doping of impurities of different conductivity types in one step to form a region of the first conductivity type impurity. In the second conductivity type impurity region, only one high-temperature doping is performed, reducing the number of high-temperature doping steps. Since this invention only involves one co-doping step, a thicker BSG layer is not needed before phosphorus doping to block the alkaline polishing and RCA washing tanks. Therefore, the oxygen content of the silicon wafer is reduced, which reduces the recombination effect inside the solar cell and thus improves the photoelectric conversion efficiency. Since the conventional production line route is boron doping followed by phosphorus doping, the boron doping temperature is as high as 1000℃, requiring high temperature to grow a thick oxide layer and advance boron doping. However, the preparation route of this invention does not require the growth of a thick oxide layer, eliminating the high-temperature boron doping process, simplifying the process flow, and reducing equipment investment costs.

[0058] In a preferred embodiment, the thickness of the dopant source layer for the first conductivity type impurity is 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm. More preferably, the thickness of the dopant source layer for the first conductivity type impurity is 50 nm to 100 nm.

[0059] In this invention, the thickness of the dopant source layer of the first type of conductivity impurity is 10nm-100nm. When the thickness is less than 10nm, it cannot effectively act as a barrier layer for the second type of conductivity impurity, resulting in severe recombination and a decrease in photoelectric conversion efficiency. When the thickness is greater than 100nm, it will result in a high oxygen content in the silicon wafer, leading to severe recombination, a decrease in photoelectric conversion efficiency, and light-induced degradation.

[0060] The dopant source layer of the first conductivity type impurity needs to have a certain thickness. The purpose is to ensure that the first doping region has sufficient doping concentration after one-step co-doping, and to act as a mask layer to prevent the dopant of the second conductivity type impurity from doping into the first doping region, while also preventing the opening of the film from damaging the polysilicon or c-Si. The complete removal of the dopant source layer of the first conductivity type impurity and the dopant source layer of the second conductivity type impurity will be completely removed in the subsequent RCA cleaning step.

[0061] In a preferred embodiment, the solar cell includes a substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side. The back side of the substrate silicon wafer has the dielectric region and the polycrystalline silicon layer sequentially disposed along a direction away from the substrate silicon wafer, and the dopant source layer of the first conductivity type impurity is outside the polycrystalline silicon layer.

[0062] In a preferred embodiment, the preparation method further includes a texturing step, wherein the texturing step forms a front textured surface on the front side of the substrate silicon wafer, or the texturing step forms a front textured surface on the front side of the substrate silicon wafer and a back partial textured surface on the back side, wherein the morphology and size of the front textured surface and the back partial textured surface are the same or different.

[0063] In a preferred embodiment, the texturing step is performed before the formation of the dielectric region and the polysilicon layer in S2, and the texturing step further includes a mask preparation step, in which a mask layer is formed on the back side of the substrate silicon wafer; or, the texturing step is performed after the formation of the dopant source layer of the first conductivity type impurity in S3.

[0064] As a preferred embodiment, a mask layer is formed by CVD. In a CVD furnace tube, a mask layer is formed on the back side of a silicon wafer through chemical and plasma reactions. The mask layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 10nm-100nm.

[0065] In a preferred embodiment, the texturing process uses one or more of KOH and NaOH at a concentration of 0.5 wt%-2 wt% for etching, with an etching time of 400s-600s.

[0066] In a preferred embodiment, a film-forming step is included before the texturing step. The film-forming step employs at least one of laser, etching paste, and photolithography. More preferably, laser film-forming is used, with the following parameters: wavelength 355nm-1064nm, power ≥1W, scanning speed 5m / s-50m / s, and frequency 200kHz-2000kHz. This film-forming step forms a c-Si region.

[0067] In a preferred embodiment, the substrate silicon wafer in S1 is N-type or P-type, with a resistivity of 0.1Ωcm-3.0Ωcm and a thickness of 100μm-200μm.

[0068] In a preferred embodiment, the cleaning and polishing in S1 utilizes acid and alkali chemicals to remove organic contaminants and metallic impurities from the silicon wafer surface, thereby etching and polishing the surface of the monocrystalline silicon wafer.

[0069] In a preferred embodiment, step S2 employs CVD to form the dielectric region and polycrystalline silicon layer. In a CVD furnace tube, N₂O is used as the oxidant, with an oxidation temperature of 300℃-650℃ and a time of 60s-600s to form a tunneling oxide layer with a thickness of 1 nm-3 nm. SiH₄ is ​​used as the reaction gas, and Ar is used as the dilution gas, with a formation temperature of 300-650℃ and a time of 300s-3600s to form a polycrystalline silicon layer with a thickness of 50 nm-400 nm on the surface of the tunneling oxide layer. The CVD method is either PECVD or LPCVD.

[0070] In a preferred embodiment, the dopant source layer for forming the first conductivity type impurity in step S3 is formed by CVD at a temperature of 300℃-800℃ for 1min-90min. The raw materials include boron source gas or phosphorus source gas. The boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3. The CVD method is PECVD or LPCVD.

[0071] In a preferred embodiment, the raw materials also include other gases, namely one or more of SiH4, N2O, NH3, and Ar.

[0072] In a preferred embodiment, the dopant source layer of the first conductivity type impurity in S3 is a silicon-containing compound layer containing the first conductivity impurity, which is boron, gallium, or phosphorus.

[0073] In a preferred embodiment, S4 involves one-step co-doping of impurities of different conductivity types. A silicon wafer is placed in a doping tube for doping, using a doping source of a second conductivity type impurity with an electrical polarity opposite to that of the first conductivity type impurity. The doping temperature is 600℃-1000℃. In a more preferred embodiment, the doping temperature is 600℃-980℃, and the doping time is 5min-180min. The dopant source layer of the first conductivity type impurity formed on the back of the silicon wafer can serve as both a doping source and a barrier layer during doping with another element. This achieves simultaneous one-step high-temperature doping of impurities of different conductivity types, forming a first conductivity type impurity region and a second conductivity type impurity region. The first and second conductivity type impurity regions have opposite electrical polarities, and the one-step co-doping of impurities of different conductivity types is performed at least once.

[0074] In a preferred embodiment, the doping source of the second conductivity type impurity is a boron source gas or a phosphorus source gas, wherein the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0075] In a preferred embodiment, after the S4 step of co-doping with impurities of different conductivity types, laser selective doping is further included. The wavelength of the laser selective doping is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, and the frequency is 200kHz-2000kHz. The laser selective doping results in a locally heavily doped region in the region of the conductivity type impurities.

[0076] In a preferred embodiment, after laser selective doping, the process further includes removing a dopant source layer for impurities of the first conductivity type. The dopant source layer for removing impurities of the first conductivity type is pickled with hydrofluoric acid at a concentration of 0.5%-50% for a pickling time of 10s-1200s. Then, the silicon wafer is subjected to RCA standard cleaning to remove surface contaminants.

[0077] In a preferred embodiment, S5 forms a dielectric layer, which is at least composed of an antireflective film. The antireflective film layer of 50 nm to 120 nm is formed by CVD. The antireflective film layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0078] In a preferred embodiment, the dielectric layer further includes a passivation film layer with a thickness of 2-15 nm, and the passivation film layer is aluminum oxide.

[0079] In a preferred embodiment, the S6 metallization involves forming a front metal electrode and a back metal electrode on a silicon wafer, preferably a silver electrode, to obtain the solar cell structure.

[0080] In a preferred embodiment, the formation of the polysilicon layer in S2, the formation of the dopant source layer of the first conductivity type impurity in S3, the doping in S4, and the formation of the dielectric layer in S5 are in a double-intercalation mode.

[0081] Since many processes in this invention have been changed from single-insertion mode to double-insertion mode, production costs are saved, output is increased, and large-scale production is facilitated.

[0082] This embodiment also provides a solar cell, including a silicon substrate wafer; the silicon substrate wafer has a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the silicon substrate wafer is provided with a front textured surface, a second conductivity type impurity region, a second dielectric layer and a front metal electrode; the back side of the silicon substrate wafer is provided with a first dielectric region, a first conductivity type impurity region, a first dielectric layer and a back metal electrode;

[0083] The first dielectric region is a first tunneling oxide layer, the first conductivity type impurity region is a c-Si region or a polysilicon layer doped with a first conductivity type impurity, and the second conductivity type impurity region is a c-Si region or a polysilicon layer doped with a second conductivity type impurity.

[0084] The dopant source layer of the first type of conductivity impurity serves as the dopant source of the c-Si region or polysilicon layer of the first type of conductivity impurity, and the thickness of the dopant source layer of the first type of conductivity impurity is 10nm-100nm.

[0085] The second conductivity type impurity region and the first conductivity type impurity region are formed simultaneously in one or more one-step co-doping steps of impurities of different conductivity types;

[0086] At least once in the one-step co-doping step of the impurities of different conductivity types, a doping source having a second conductivity type that is opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer;

[0087] The first type of conductivity impurity region has the opposite electrical properties to the second type of conductivity impurity region, and a local region of the back metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

[0088] In a preferred embodiment, a second dielectric region is further provided on the front textured surface in the direction away from the substrate silicon wafer; a back partial textured surface and an edge textured surface are further provided below the first dielectric region in the direction close to the substrate silicon wafer, and a heavily doped region is further provided in the first conductivity type impurity region and / or the second conductivity type impurity region.

[0089] In a preferred embodiment, the c-Si region is formed by a film-opening and cleaning process, wherein the film-opening process is at least one of laser, etching paste, and photolithography; and the polycrystalline silicon layer is formed by CVD deposition.

[0090] This embodiment also provides another solar cell structure, the solar cell including a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer having, from the inside to the outside, a front textured surface, a second conductivity type impurity region, a second dielectric layer, and a front metal electrode; the back side of the substrate silicon wafer having, from the inside to the outside, a first dielectric region, a first conductivity type impurity region, a first dielectric layer, and a back metal electrode;

[0091] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with the second type of conductivity impurity region; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with the first type of conductivity impurity region.

[0092] The first dielectric region is a first tunneling oxide layer; the first conductivity type impurity region is a c-Si region or polysilicon layer doped with a first conductivity type impurity, and the second conductivity type impurity region is a c-Si region or polysilicon layer doped with a second conductivity type impurity.

[0093] The solar cell and its preparation method of the present invention will be further described below through specific embodiments and comparative examples.

[0094] Example 1

[0095] like Figure 1 As shown, an N-type TOPCon cell includes an N-type silicon wafer 4, which serves as a substrate silicon wafer. The front side of the N-type silicon wafer 4 is provided with a second conductivity type impurity polycrystalline silicon layer 3, a second dielectric layer 2, and a front metal electrode 1, arranged sequentially from the inside to the outside. The back side of the N-type silicon wafer 4 is provided with a first tunneling oxide layer 5, a first conductivity type impurity polycrystalline silicon layer 6, a first dielectric layer 7, and a back metal electrode 8, arranged sequentially from the inside to the outside.

[0096] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with the second type of conductivity impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with the first type of conductivity impurity polysilicon layer.

[0097] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 50 nm.

[0098] like Figure 2 As shown, the fabrication method of the N-type TOPCon battery in this embodiment includes the following steps:

[0099] ① Select a P-doped N-type silicon wafer with a resistivity of 1.5 Ωcm and a thickness of 150 μm; use acid and alkali chemicals to remove organic contaminants and metallic impurities from the surface of the silicon wafer, and then etch and polish the surface of the single crystal silicon wafer.

[0100] ② In the PECVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 500℃ and the time is 300s, and a first tunneling oxide layer with a thickness of 3nm is formed on the back of the silicon wafer; SiH4 is used as the reaction gas and Ar is used as the dilution gas, the formation temperature is 500℃ and the time is 1800s, and a polycrystalline silicon layer with a thickness of 250nm is formed on the surface of the first tunneling oxide layer.

[0101] ③ In a PECVD furnace tube, using PH3, SiH4, N2O, Ar, and NH3 as raw materials, a phosphorus-containing silicon oxide layer with a thickness of 50 nm is formed on a polycrystalline silicon layer at a temperature of 600℃ for 50 minutes.

[0102] ④ Use a 1.3% NaOH solution for etching for 500 seconds to form a pyramidal textured surface on the front side of the silicon wafer (not shown in the figure).

[0103] ⑤ The silicon wafer is placed in a boron-doped tube for boron-phosphorus co-doping at a doping temperature of 800℃ for 100 minutes. The boron doping source is BBr3, forming a second conductivity type impurity polycrystalline silicon layer on the front side of the silicon wafer. The phosphorus-containing silicon oxide layer on the back side can serve as a doping source for the first conductivity type impurity polycrystalline silicon layer, or as a boron doping barrier layer. The boron-phosphorus co-doping is performed twice in one step.

[0104] ⑥ Immerse the silicon wafer in 25% HF for 600 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0105] ⑦ Using ALD atomic layer formation method, with TMA as precursor, and reaction temperature controlled at 300℃, a dense Al2O3 passivation layer with a thickness of 8nm is formed on the front and back of the silicon wafer. Then, an 80nm SiNx antireflection layer is formed on the front and back of the silicon wafer using LPCVD method. The passivation layer and the antireflection layer form a dielectric layer.

[0106] ⑧ Print Ag paste on the front and back sides of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0107] Example 2

[0108] An N-type TOPCon cell includes an N-type silicon wafer. The front side of the N-type silicon wafer is provided with, from the inside to the outside, a second conductivity type impurity polycrystalline silicon layer, a heavily doped region of the second conductivity type impurity polycrystalline silicon layer, a second dielectric layer, and a front metal electrode. The back side of the N-type silicon wafer is provided with, from the inside to the outside, a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode.

[0109] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with a heavily doped region of the second conductivity type impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with a first conductivity type impurity polysilicon layer.

[0110] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 50 nm.

[0111] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps:

[0112] ① Select a P-doped N-type silicon wafer with a resistivity of 1.5 Ωcm and a thickness of 150 μm; use acid and alkali chemicals to remove organic contaminants and metallic impurities from the surface of the silicon wafer, and then etch and polish the surface of the single crystal silicon wafer.

[0113] ② In the LPCVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 500℃ and the time is 300s, and a first tunneling oxide layer with a thickness of 3nm is formed on the back of the silicon wafer; SiH4 is used as the reaction gas and Ar is used as the dilution gas, the formation temperature is 500℃ and the time is 1800s, and a polycrystalline silicon layer with a thickness of 250nm is formed on the surface of the first tunneling oxide layer.

[0114] ③ In the LPCVD furnace tube, using PH3, SiH4, N2O, Ar, and NH3 as raw materials, a phosphorus-containing silicon oxide layer with a thickness of 50 nm is formed on the polycrystalline silicon layer at a temperature of 600℃ for 50 min.

[0115] ④ Use a 1.3% NaOH solution for etching for 500 seconds to form a pyramidal textured surface on the front side of the silicon wafer (not shown in the figure).

[0116] ⑤ The silicon wafer is placed in a boron-doped tube for boron-phosphorus co-doping at a doping temperature of 950℃ for 100 min. The boron doping source is BBr3, forming a second-conductivity type impurity polycrystalline silicon layer on the front side of the silicon wafer. The phosphorus-containing silicon oxide layer on the back side can serve as a doping source for the first-conductivity type impurity polycrystalline silicon layer, or as a boron doping barrier layer. The boron-phosphorus co-doping is performed twice in one step. During laser selective doping, the wavelength is set to 532 nm, the scanning speed to 25 m / s, and the frequency to 1000 kHz. The metal contact area forms a heavily doped region of the second-conductivity type impurity polycrystalline silicon layer, while the open-film region of the non-metal contact area forms the second-conductivity type impurity polycrystalline silicon layer.

[0117] ⑥ Immerse the silicon wafer in 25% HF for 600 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0118] ⑦ Using ALD atomic layer formation method, with TMA as precursor, and reaction temperature controlled at 300℃, a dense Al2O3 passivation layer with a thickness of 8nm is formed on the front and back of the silicon wafer. Then, an 80nm SiNx antireflection layer is formed on the front and back of the silicon wafer using LPCVD method. The passivation layer and the antireflection layer form a dielectric layer.

[0119] ⑧ Print Ag paste on the front and back sides of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0120] Example 3

[0121] An N-type TOPCon cell includes a polished N-type silicon wafer. The front side of the polished N-type silicon wafer is provided with a front textured surface, a second conductivity type impurity polycrystalline silicon layer, a second dielectric layer, and a front metal electrode in sequence from the inside to the outside. The back side of the polished N-type silicon wafer is provided with a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode in sequence from the inside to the outside.

[0122] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with the second type of conductivity impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with the first type of conductivity impurity polysilicon layer.

[0123] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 50 nm.

[0124] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps:

[0125] ① Select a P-doped N-type silicon wafer with a resistivity of 1.5 Ωcm and a thickness of 150 μm; use acid and alkali chemicals to remove organic contaminants and metallic impurities from the surface of the silicon wafer, and then etch and polish the surface of the single crystal silicon wafer.

[0126] ② In the LPCVD furnace tube, a mask layer is formed on the back side of the silicon wafer through chemical and plasma reactions; the mask layer is SiO2 and its thickness is 100nm.

[0127] ③ Use a 1.3% NaOH solution for etching for 500 seconds to form a front-side pyramid texture on the silicon wafer.

[0128] ④ In the PECVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 500℃ and the time is 300s, and a first tunneling oxide layer with a thickness of 3nm is formed on the back of the silicon wafer; SiH4 is used as the reaction gas and Ar is used as the dilution gas, the formation temperature is 500℃ and the time is 1800s, and a polycrystalline silicon layer with a thickness of 250nm is formed on the surface of the first tunneling oxide layer.

[0129] ⑤ In the LPCVD furnace tube, using PH3, SiH4, N2O, Ar, and NH3 as raw materials, a phosphorus-containing silicon oxide layer with a thickness of 50 nm is formed on the polycrystalline silicon layer at a temperature of 600℃ for 50 min.

[0130] ⑥ The silicon wafer is placed in a boron-doped tube for boron-phosphorus co-doping at a doping temperature of 800℃ for 100 minutes. The boron doping source is BBr3, forming a second conductivity type impurity polycrystalline silicon layer on the front side of the silicon wafer. The phosphorus-containing silicon oxide layer on the back side can serve as a doping source for the first conductivity type impurity polycrystalline silicon layer, or as a boron doping barrier layer. The boron-phosphorus co-doping is performed twice in one step.

[0131] ⑦ Immerse the silicon wafer in 25% HF for 600 seconds to remove the phosphorus-containing silicon oxide layer, boron-containing silicon oxide layer, and mask layer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0132] ⑧ An 80nm SiNx antireflection layer is formed on the front and back sides of a silicon wafer using LPCVD. The passivation layer and the antireflection layer form a dielectric layer.

[0133] ⑨ Print Ag paste on the front and back sides of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0134] Example 4

[0135] An N-type TOPCon cell includes an N-type silicon wafer. The front side of the N-type silicon wafer is provided with a second conductivity type impurity polycrystalline silicon layer, a second dielectric layer, and a front metal electrode in sequence from the inside to the outside. The back side of the N-type silicon wafer is provided with a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode in sequence from the inside to the outside.

[0136] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with the second type of conductivity impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with the first type of conductivity impurity polysilicon layer.

[0137] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 10 nm.

[0138] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps:

[0139] ① Select a P-doped N-type silicon wafer with a resistivity of 0.1Ωcm and a thickness of 100μm; use acid and alkali chemicals to remove organic contaminants and metallic impurities from the surface of the silicon wafer, and then etch and polish the surface of the single crystal silicon wafer.

[0140] ② In the PECVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 300℃ and the time is 600s, and a first tunneling oxide layer with a thickness of 2nm is formed on the back of the silicon wafer; SiH4 is used as the reaction gas and Ar is used as the dilution gas, the formation temperature is 300℃ and the time is 3600s, and a polycrystalline silicon layer with a thickness of 50nm is formed on the surface of the first tunneling oxide layer.

[0141] ③ In a PECVD furnace tube, using POCl, SiH4, N2O, Ar, and NH3 as raw materials, a phosphorus-containing silicon oxide layer with a thickness of 10 nm is formed on a polycrystalline silicon layer at a temperature of 300℃ for 5 minutes.

[0142] ④ Use a 0.5% NaOH solution for etching for 600 seconds to form a pyramidal textured surface on the front side of the silicon wafer.

[0143] ⑤ The silicon wafer is placed in a boron-doped tube for boron-phosphorus co-doping at a doping temperature of 600℃ for 180 minutes. The boron doping source is BBr3, forming a second conductivity type impurity polycrystalline silicon layer on the front side of the silicon wafer. The phosphorus-containing silicon oxide layer on the back side can serve as a doping source for the first conductivity type impurity polycrystalline silicon layer, or as a boron doping barrier layer. The boron-phosphorus co-doping is performed four times in one step.

[0144] ⑥ Immerse the silicon wafer in 0.5% HF for 1200 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0145] ⑦ Using ALD atomic layer formation method, with TMA as precursor, and reaction temperature controlled at 300℃, a dense Al2O3 passivation layer with a thickness of 2nm is formed on the front and back of the silicon wafer. Then, a 50nm SiNx antireflection layer is formed on the front and back of the silicon wafer using LPCVD method. The passivation layer and the antireflection layer form a dielectric layer.

[0146] ⑧ Print Ag paste on the front and back sides of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0147] Example 5

[0148] An N-type TOPCon cell includes an N-type silicon wafer. The front side of the N-type silicon wafer is provided with a second conductivity type impurity polycrystalline silicon layer, a second dielectric layer, and a front metal electrode in sequence from the inside to the outside. The back side of the N-type silicon wafer is provided with a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode in sequence from the inside to the outside.

[0149] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with the second type of conductivity impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with the first type of conductivity impurity polysilicon layer.

[0150] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 100 nm.

[0151] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps:

[0152] ① Select a P-doped N-type single crystal silicon wafer with a resistivity of 3Ωcm and a thickness of 200μm; use acid and alkali chemicals to remove organic contaminants and metallic impurities from the surface of the silicon wafer, and then etch and polish the surface of the single crystal silicon wafer.

[0153] ② In the LPCVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 650℃ and the time is 60s, and a first tunneling oxide layer with a thickness of 4nm is formed on the back of the silicon wafer; SiH4 is used as the reaction gas and Ar is used as the dilution gas, the formation temperature is 650℃ and the time is 300s, and a polycrystalline silicon layer with a thickness of 400nm is formed on the surface of the first tunneling oxide layer.

[0154] ③ In the LPCVD furnace tube, using PH3, SiH4, N2O, Ar, and NH3 as raw materials, a phosphorus-containing silicon oxide layer with a thickness of 100nm is formed on the polycrystalline silicon layer at a temperature of 800℃ for 90 minutes.

[0155] ④ Use a 2% NaOH solution for etching for 400 seconds to create a pyramidal textured surface on the front side of the silicon wafer.

[0156] ⑤ The silicon wafer is placed in a boron-doped tube for boron-phosphorus co-doping at a doping temperature of 1000℃ for 5 minutes. The boron doping source is BBr3, forming a second conductivity type impurity polycrystalline silicon layer on the front side of the silicon wafer. The phosphorus-containing silicon oxide layer on the back side can serve as a doping source for the first conductivity type impurity polycrystalline silicon layer, or as a boron doping barrier layer. The boron-phosphorus co-doping is performed once.

[0157] ⑥ Immerse the silicon wafer in 50% HF for 10 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0158] ⑦ Using ALD atomic layer formation method, with TMA as precursor, and reaction temperature controlled at 300℃, a dense Al2O3 passivation layer with a thickness of 15nm is formed on the front and back of the silicon wafer. Then, a 120nm SiNx antireflection layer is formed on the front and back of the silicon wafer using LPCVD method. The passivation layer and the antireflection layer form a dielectric layer.

[0159] ⑧ Print Ag paste on the front and back sides of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0160] Example 6

[0161] A P-type TOPCon cell includes a P-type silicon wafer. The front side of the P-type silicon wafer is provided with a second conductivity type impurity polycrystalline silicon layer, a second dielectric layer, and a front metal electrode in sequence from the inside to the outside. The back side of the P-type silicon wafer is provided with a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode in sequence from the inside to the outside.

[0162] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with the second type of conductivity impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with the first type of conductivity impurity polysilicon layer.

[0163] The dopant source layer of the first conductivity type impurity is a silicon oxide layer containing the first conductivity type impurity, the first conductivity type impurity is boron, and the thickness of the dopant source layer of the first conductivity type impurity is 50 nm.

[0164] The preparation method in this embodiment differs from that in Example 1 in that:

[0165] ① The single-crystal silicon wafer is a B-doped P-type single-crystal silicon wafer;

[0166] ③ Using BH3, SiH4, N2O, Ar, and NH3 as raw materials, a boron-containing silicon oxide layer with a thickness of 50 nm is formed;

[0167] ⑤ The silicon wafer is placed in a phosphorus doping tube for boron-phosphorus co-doping. The doping temperature is 800℃ and the doping time is 100min. The phosphorus doping source is POCl3. A second conductivity type impurity polycrystalline silicon layer is formed on the front side of the silicon wafer. The boron-containing silicon oxide layer on the back side can be used as a doping source for the first conductivity type impurity polycrystalline silicon layer to form the first conductivity type impurity polycrystalline silicon layer, or it can be used as a phosphorus doping barrier layer.

[0168] Everything else is the same.

[0169] Example 7

[0170] An N-type TOPCon cell includes an N-type silicon wafer. The front side of the N-type silicon wafer is provided with a second conductivity type impurity polycrystalline silicon layer, a second dielectric layer, and a front metal electrode in sequence from the inside to the outside. The back side of the N-type silicon wafer is provided with a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode in sequence from the inside to the outside.

[0171] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with the second type of conductivity impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with the first type of conductivity impurity polysilicon layer.

[0172] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 8 nm.

[0173] The preparation method in this embodiment differs from that in Example 4 in that:

[0174] ③ A phosphorus-silicon oxide layer with a thickness of 8 nm is formed in the process;

[0175] Everything else is the same.

[0176] Example 8

[0177] An N-type TOPCon cell includes an N-type silicon wafer. The front side of the N-type silicon wafer is provided with a second conductivity type impurity polycrystalline silicon layer, a second dielectric layer, and a front metal electrode in sequence from the inside to the outside. The back side of the N-type silicon wafer is provided with a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode in sequence from the inside to the outside.

[0178] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with the second type of conductivity impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with the first type of conductivity impurity polysilicon layer.

[0179] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 103 nm.

[0180] The preparation method in this embodiment differs from that in Example 5 in that:

[0181] A phosphorus-containing silicon oxide layer with a thickness of 103 nm is formed in ③;

[0182] Everything else is the same.

[0183] Example 9

[0184] like Figure 3As shown, an N-type TOPCon cell includes an N-type silicon wafer 4. The front side of the N-type silicon wafer 4 is provided with, from the inside to the outside, a second conductivity type impurity c-Si region 11, a second dielectric layer 2, a second tunneling oxide layer 10, a second conductivity type impurity polycrystalline silicon layer heavily doped region 9, and a front metal electrode 1. The back side of the N-type silicon wafer 4 is provided with, from the inside to the outside, a first tunneling oxide layer 5, a first conductivity type impurity polycrystalline silicon layer 6, a first dielectric layer 7, and a back metal electrode 8.

[0185] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with a heavily doped region of the second conductivity type impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with a first conductivity type impurity polysilicon layer.

[0186] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 50 nm.

[0187] like Figure 4 As shown, the preparation method in this embodiment differs from that in Example 1 in that:

[0188] ② In the PECVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 500℃ and the time is 300s, and a second tunneling oxide layer and a first tunneling oxide layer with a thickness of 3nm are formed on the front and back sides of the silicon wafer, respectively; SiH4 is used as the reaction gas and Ar is used as the dilution gas, the formation temperature is 500℃ and the time is 1800s, and a polycrystalline silicon layer with a thickness of 250nm is formed on the surface of the tunneling oxide layer.

[0189] In step ④, laser delamination is first used before texturing. Laser delamination is performed on the non-metallic contact area on the front side of the silicon wafer to form a c-Si region. The parameters for laser delamination are set as follows: wavelength 600nm, power ≥1W, scanning speed 25m / s, and frequency 1000kHz.

[0190] ⑤ When selectively doping with laser, the wavelength is set to 532nm, the scanning speed to 25m / s, and the frequency to 1000kHz. The metal contact area forms a heavily doped region of the polysilicon layer with a second type of conductivity, and the open film area of ​​the non-metal contact forms a c-Si region with a second type of conductivity.

[0191] Everything else is the same.

[0192] Example 10

[0193] An N-type TOPCon cell includes an N-type silicon wafer. The front side of the N-type silicon wafer is provided with, from the inside to the outside, a second conductivity type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a heavily doped region of the second conductivity type impurity polycrystalline silicon layer, and a front metal electrode. The back side of the N-type silicon wafer is provided with, from the inside to the outside, a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode.

[0194] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with a heavily doped region of the second conductivity type impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with a first conductivity type impurity polysilicon layer.

[0195] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 10 nm.

[0196] The preparation method in this embodiment differs from that in Example 4 in that:

[0197] ② In the PECVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 300℃ and the time is 600s, and a second tunneling oxide layer and a first tunneling oxide layer with a thickness of 2nm are formed on the front and back sides of the silicon wafer, respectively; SiH4 is used as the reaction gas and Ar is used as the dilution gas, the formation temperature is 300℃ and the time is 3600s, and a polycrystalline silicon layer with a thickness of 50nm is formed on the surface of the tunneling oxide layer.

[0198] ④ First, laser delamination is used, followed by texturing. Laser delamination is performed on the non-metallic contact area on the front side of the silicon wafer to form a c-Si region. The parameters for laser delamination are set as follows: wavelength 355nm, power ≥1W, scanning speed 5m / s, and frequency 2000kHz.

[0199] ⑤ When selectively doping with laser, the wavelength is set to 1064nm, the scanning speed to 50m / s, and the frequency to 2000kHz. The metal contact area forms a heavily doped region of the polysilicon layer with a second type of conductivity, and the open film area of ​​the non-metal contact forms a c-Si region with a second type of conductivity.

[0200] Everything else is the same.

[0201] Example 11

[0202] An N-type TOPCon cell includes an N-type silicon wafer. The front side of the N-type silicon wafer is provided with, from the inside to the outside, a second conductivity type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a heavily doped region of the second conductivity type impurity polycrystalline silicon layer, and a front metal electrode. The back side of the N-type silicon wafer is provided with, from the inside to the outside, a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode.

[0203] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with a heavily doped region of the second conductivity type impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with a first conductivity type impurity polysilicon layer.

[0204] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 100 nm.

[0205] The preparation method in this embodiment differs from that in Example 5 in that:

[0206] ② In the PECVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 650℃ and the time is 60s, and a second tunneling oxide layer and a first tunneling oxide layer with a thickness of 4nm are formed on the front and back sides of the silicon wafer, respectively; SiH4 is used as the reaction gas and Ar is used as the dilution gas, the formation temperature is 650℃ and the time is 300s, and a polycrystalline silicon layer with a thickness of 400nm is formed on the surface of the tunneling oxide layer.

[0207] ④ First, laser delamination is used, followed by texturing. Laser delamination is performed on the non-metallic contact area on the front side of the silicon wafer to form a c-Si region. The parameters for laser delamination are set as follows: wavelength 1064nm, power ≥1W, scanning speed 50m / s, and frequency 200kHz.

[0208] ⑤ When selectively doping with laser, the wavelength is set to 200nm, the scanning speed to 5m / s, and the frequency to 200kHz. The metal contact area forms a heavily doped region of the polycrystalline silicon layer with a second type of conductivity, and the open film area of ​​the non-metal contact forms a c-Si region with a second type of conductivity.

[0209] Everything else is the same.

[0210] Example 12

[0211] A P-type TOPCon cell includes a P-type silicon wafer. The front side of the P-type silicon wafer is provided with, from the inside to the outside, a second conductivity type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a heavily doped region of the second conductivity type impurity polycrystalline silicon layer, and a front metal electrode. The back side of the P-type silicon wafer is provided with, from the inside to the outside, a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode.

[0212] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with a heavily doped region of the second conductivity type impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with a first conductivity type impurity polysilicon layer.

[0213] The dopant source layer of the first conductivity type impurity is a silicon oxide layer containing the first conductivity type impurity, the first conductivity type impurity is boron, and the thickness of the dopant source layer of the first conductivity type impurity is 50 nm.

[0214] The preparation method in this embodiment differs from that in Example 9 in that:

[0215] ① The single-crystal silicon wafer is a B-doped P-type single-crystal silicon wafer;

[0216] ③ Using BH3, SiH4, N2O, Ar, and NH3 as raw materials, a boron-silicon oxide layer with a thickness of 50 nm is formed;

[0217] In ⑤, the doping source is POCl3. When selectively doping with laser, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact area forms a heavily doped region of the polysilicon layer with a second type of conductivity, and the open film area of ​​the non-metal contact forms a c-Si region with a second type of conductivity.

[0218] Everything else is the same.

[0219] Example 13

[0220] An N-type TOPCon cell includes an N-type silicon wafer. The front side of the N-type silicon wafer is provided with, from the inside to the outside, a second conductivity type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a heavily doped region of the second conductivity type impurity polycrystalline silicon layer, and a front metal electrode. The back side of the N-type silicon wafer is provided with, from the inside to the outside, a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode.

[0221] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with a heavily doped region of the second conductivity type impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with a first conductivity type impurity polysilicon layer.

[0222] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 8 nm.

[0223] The preparation method in this embodiment differs from that in Example 10 in that:

[0224] The thickness of the phosphorus-containing silicon oxide layer formed in ③ is 8 nm;

[0225] Everything else is the same.

[0226] Example 14

[0227] An N-type TOPCon cell includes an N-type silicon wafer. The front side of the N-type silicon wafer is provided with, from the inside to the outside, a second conductivity type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a heavily doped region of the second conductivity type impurity polycrystalline silicon layer, and a front metal electrode. The back side of the N-type silicon wafer is provided with, from the inside to the outside, a first tunneling oxide layer, a first conductivity type impurity polycrystalline silicon layer, a first dielectric layer, and a back metal electrode.

[0228] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with a heavily doped region of the second conductivity type impurity polysilicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with a first conductivity type impurity polysilicon layer.

[0229] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 103 nm.

[0230] The preparation method in this embodiment differs from that in Example 11 in that:

[0231] The thickness of the phosphorus-containing silicon oxide layer formed in ③ is 103 nm;

[0232] Everything else is the same.

[0233] Example 15

[0234] like Figure 5 As shown, an N-type TOPCon cell includes an N-type silicon wafer 4. The front side of the N-type silicon wafer 4 is provided with a second conductivity type impurity polycrystalline silicon layer 3, a second dielectric layer 2, and a front metal electrode 1, arranged sequentially from the inside to the outside. The back side of the N-type silicon wafer 4 is provided with a first conductivity type impurity c-Si region 12, a first dielectric layer 7, a first tunneling oxide layer 5, a heavily doped region of the first conductivity type impurity polycrystalline silicon layer 13, and a back metal electrode 8, arranged sequentially from the inside to the outside.

[0235] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with the second conductivity type impurity polycrystalline silicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with the heavily doped region of the first conductivity type impurity polycrystalline silicon layer.

[0236] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 50 nm.

[0237] The preparation method in this embodiment differs from that in Example 9 in that:

[0238] In step ④, laser delamination is first used followed by texturing. Laser delamination is performed on the non-metallic contact area on the back of the silicon wafer to form a c-Si region. The laser delamination parameters are set as follows: wavelength 600nm, power ≥1W, scanning speed 25m / s, and frequency 1000kHz. Then, a 1.3% NaOH solution is used for etching for 500s to form a pyramid textured surface on the front and back of the silicon wafer (not shown in the figure). Then, the pyramid textured surface on the back is polished with an acid-base solution to make the pyramid textured surface on the back smooth and flat.

[0239] ⑤ When selectively doping with laser, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact area on the back of the silicon wafer forms a heavily doped region of the polycrystalline silicon layer with a second type of conductivity, and the open film area of ​​the non-metal contact area on the back of the silicon wafer forms a c-Si region with a second type of conductivity.

[0240] Everything else is the same.

[0241] Example 16

[0242] like Figure 6 As shown, an N-type TOPCon cell includes an N-type silicon wafer 4. The front side of the N-type silicon wafer 4, from the inside out, is sequentially provided with a second conductivity type impurity c-Si region 11, a second dielectric layer 2, a second tunneling oxide layer 10, a heavily doped polycrystalline silicon layer region 9 of the second conductivity type impurity, and a front metal electrode 1. The back side of the N-type silicon wafer 4, from the inside out, is sequentially provided with a first conductivity type impurity c-Si region 12, a first dielectric layer 7, a first tunneling oxide layer 5, a heavily doped polycrystalline silicon layer region 13 of the first conductivity type impurity, and a back metal electrode 8.

[0243] A localized area of ​​the front metal electrode penetrates the second dielectric layer and forms an ohmic contact with a heavily doped region of the second conductivity type impurity polycrystalline silicon layer; a localized area of ​​the back metal electrode penetrates the first dielectric layer and forms an ohmic contact with a heavily doped region of the first conductivity type impurity polycrystalline silicon layer.

[0244] The dopant source layer of the first conductivity type impurity is a silicon oxide compound layer containing the first conductivity type impurity, the first conductivity type impurity is phosphorus, and the thickness of the dopant source layer of the first conductivity type impurity is 50 nm.

[0245] The preparation method in this embodiment differs from that in Example 15 in that:

[0246] In step ④, laser delamination is first used followed by texturing. Laser delamination is performed on the non-metallic contact areas on the front and back sides of the silicon wafer to form c-Si regions. The laser delamination parameters are set as follows: wavelength 600nm, power ≥1W, scanning speed 25m / s, and frequency 1000kHz. Then, a 1.3% NaOH solution is used for etching for 500s to form a pyramid textured surface on the front and back sides of the silicon wafer (not shown in the figure). Then, the pyramid textured surface on the back side is polished with an acid-base solution to make the pyramid textured surface on the back side smooth and flat.

[0247] ⑤ When selectively doping with laser, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact areas on the front and back sides of the silicon wafer form a heavily doped region of polysilicon layer with second conductivity type impurity and a heavily doped region of polysilicon layer with first conductivity type impurity, respectively. The open film areas on the non-metal contact areas on the front and back sides of the silicon wafer form a c-Si region with second conductivity type impurity and a c-Si region with first conductivity type impurity, respectively.

[0248] Comparative Example 1

[0249] This comparative example demonstrates the conventional method for preparing TOPCon batteries:

[0250] ① Select a P-doped N-type silicon wafer with a resistivity of 1.5 Ωcm and a thickness of 150 μm; use acid and alkali chemicals to remove organic contaminants and metallic impurities from the silicon wafer surface;

[0251] ② A 1.3% NaOH solution was used for etching for 60 minutes to create a textured surface on the front side of the silicon wafer;

[0252] ③ The silicon wafer is placed in a boron doping tube for boron doping. The doping temperature is 1000℃ and the doping time is 180min. The boron doping source is BBr3, and a 150nm BSG layer is formed on the silicon wafer.

[0253] ④ Remove the front-side BSG by etching one side of the silicon wafer, retaining the BSG barrier layer on the back side; perform etching and polishing on the surface of the monocrystalline silicon wafer for 60 minutes;

[0254] ⑤ In the LPCVD furnace tube, using N2O as the oxidant, at an oxidation temperature of 600℃ for 3 minutes, a tunneling oxide layer with a thickness of 3nm is formed on the back side of the silicon wafer; using SiH4 as the reactant gas and Ar as the diluent gas, at a formation temperature of 600℃ for 90 minutes, a polycrystalline silicon layer with a thickness of 250nm is formed on the surface of the tunneling oxide layer.

[0255] ⑥ Place the silicon wafer into a phosphorus doping tube for phosphorus doping. The doping temperature is 1000℃ and the doping time is 150min. The boron doping source is BBr3.

[0256] ⑦ Immerse the silicon wafer in 25% HF for 600 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0257] ⑧ Using the ALD atomic layer formation method, with TMA as the precursor, and the reaction temperature controlled at 300℃, a dense Al2O3 passivation layer with a thickness of 10nm is formed on the front and back sides of the silicon wafer. Then, a 100nm SiNx antireflection layer is formed on the front and back sides of the silicon wafer using the PECVD method. The passivation layer and the antireflection layer form a dielectric layer.

[0258] ⑨ Print Ag paste on the front and back sides of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0259] The batteries in Examples 1-16 and Comparative Example 1 were tested under the same conditions, and the test results are shown in Table 1.

[0260] Table 1. Battery test results for the examples and comparative examples.

[0261]

[0262] As shown in Table 1, a comparison of the test data from Examples 1-16 and Comparative Example 1 reveals that when a doped source layer of a first type of conductivity impurity is first formed, the open-circuit voltage, short-circuit current, and fill factor of the solar cell are all improved, thereby increasing the cell's conversion efficiency; the cell fabrication process time is also shortened. Test data from Examples 1-6 and Examples 7-8 show that when the thickness of the doped source layer of the first type of conductivity impurity is between 10 nm and 100 nm, the cell's open-circuit voltage, short-circuit current, fill factor, and conversion efficiency are even better. Similarly, test data from Examples 9-12 and Examples 13-14 show that when the thickness of the doped source layer of the first type of conductivity impurity is between 10 nm and 100 nm, the cell's open-circuit voltage, short-circuit current, fill factor, and conversion efficiency are even better.

[0263] The present invention has been further described above with reference to specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the nature and scope of the present invention. Various modifications made to the above embodiments by those skilled in the art after reading this specification are all within the scope of protection of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that, Includes the following steps: S1 cleans and polishes the substrate silicon wafer; S2 forms the dielectric region and the polysilicon layer; S3 forms a dopant source layer for impurities of the first conductivity type; S4 is co-doped with impurities of different conductivity types in one step; S5 forms a dielectric layer; S6 metallization; The thickness of the dopant source layer of the first type of conductivity impurity is 10nm-100nm; The solar cell includes a silicon substrate having a front side facing the sun during normal operation and a back side opposite to the front side. The back side of the silicon substrate has the dielectric region and the polycrystalline silicon layer sequentially disposed along a direction away from the silicon substrate, and the dopant source layer of the first conductivity type impurity is outside the polycrystalline silicon layer. The doping temperature for one-step co-doping of impurities of different conductivity types in S4 is 600℃-800℃, and the doping time is 5min-100min. In the dopant source layer in S3 where the first type of conductivity impurity is formed, it is formed by CVD at a temperature of 300℃-800℃, and the raw materials include boron source gas or phosphorus source gas. The boron source gas is at least one of BH3, TMB, BCl3, and BBr3; The phosphorus source gas is at least one of PH3 and POCl3; In step S3, which forms a dopant source layer for a first type of conductivity impurity, the dopant source layer for the first type of conductivity impurity is a silicon-containing compound layer containing a first type of conductivity impurity, and the first type of conductivity impurity is boron, gallium, or phosphorus. In the S4 one-step co-doping of impurities of different conductivity types, the silicon wafer is placed in a doping tube for doping, and a doping source of a second conductivity type impurity with the opposite electrical charge to the first conductivity type impurity is used, thereby simultaneously forming a first conductivity type impurity region and a second conductivity type impurity region. The first conductivity type impurity region and the second conductivity type impurity region have opposite electrical charges, and the one-step co-doping of impurities of different conductivity types is at least once. The doping source for the second type of conductivity impurity is a boron source gas or a phosphorus source gas, wherein the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POC13.

2. The method for preparing a solar cell according to claim 1, characterized in that, It also includes a texturing step, wherein the texturing step forms a front textured surface on the front side of the substrate silicon wafer, or the texturing step forms a front textured surface on the front side of the substrate silicon wafer and a back partial textured surface on the back side, wherein the morphology and size of the front textured surface and the back partial textured surface are the same or different.

3. The method for preparing a solar cell according to claim 2, characterized in that, The texturing step is performed before the formation of the dielectric region and polysilicon layer in S2. The texturing step also includes a mask preparation step before the texturing step, in which a mask layer is formed on the back side of the substrate silicon wafer; or, the texturing step is performed after the formation of the dopant source layer of the first conductivity type impurity in S3.

4. The method for preparing a solar cell according to claim 1, characterized in that, After the S4 step of co-doping with impurities of different conductivity types, a laser selective doping step is also included. The wavelength of the laser selective doping step is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, and the frequency is 200kHz-2000kHz. The laser selective doping results in a locally heavily doped region in the region of the conductivity type impurities.

5. The method for preparing a solar cell according to claim 4, characterized in that, After selective laser doping, the process further includes a step of removing the dopant source layer of the first conductivity type impurities. The removal of the dopant source layer of the first conductivity type impurities is carried out by acid washing with hydrofluoric acid at a concentration of 0.5%-50% for a time of 10s-1200s.

6. A solar cell prepared by the method for preparing a solar cell according to any one of claims 1-5, characterized in that, The substrate silicon wafer includes a front side facing the sun during normal operation and a back side opposite to the front side. The front side of the substrate silicon wafer is provided with a front textured surface, a second conductivity type impurity region, a second dielectric layer, and a front metal electrode. The back side of the substrate silicon wafer is provided with a first dielectric region, a first conductivity type impurity region, a first dielectric layer, and a back metal electrode. The first dielectric region is a first tunneling oxide layer; the first conductivity type impurity region is a c-Si region or a polysilicon layer doped with a first conductivity type impurity; and the second conductivity type impurity region is a c-Si region or a polysilicon layer doped with a second conductivity type impurity. The dopant source layer of the first type of conductivity impurity serves as the dopant source of the c-Si region or polysilicon layer of the first type of conductivity impurity, and the thickness of the dopant source layer of the first type of conductivity impurity is 10nm-100nm. The second conductivity type impurity region and the first conductivity type impurity region are formed simultaneously in one or more one-step co-doping steps of impurities of different conductivity types; At least once in the one-step co-doping step of the impurities of different conductivity types, a doping source having a second conductivity type that is opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first type of conductivity impurity region has the opposite electrical properties to the second type of conductivity impurity region, and a local region of the back metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

7. A solar cell according to claim 6, characterized in that, A second dielectric region is also provided on the front textured surface in the direction away from the substrate silicon wafer; a back partial textured surface and an edge textured surface are also provided below the first dielectric region in the direction close to the substrate silicon wafer, and a heavily doped region is also provided in the first conductivity type impurity region and / or the second conductivity type impurity region.

8. A solar cell according to claim 6, characterized in that, The c-Si region is formed by a film-opening and cleaning process, wherein the film-opening process is at least one of laser, etching paste, and photolithography; the polycrystalline silicon layer is formed by CVD deposition.

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