Substrate processing method and substrate processing apparatus

Abstract

The invention relates to a substrate processing method and a substrate processing apparatus. A substrate processing method for processing a substrate in which a plurality of first electrode layers and an insulating layer that surrounds the first electrode layers and protrudes further upward than the first electrode layers are disposed on the surface of the substrate, and a light-emitting layer is formed on each of the first electrode layers, a second electrode layer is formed so as to cover the light-emitting layer and the insulating layer, a temporary sealing film is formed so as to cover the second electrode layer, and a mask is formed on the temporary sealing film. Removing at least portions of each of the temporary sealing film and the second electrode layer on the insulating layer using the mask; and a step (B) for forming a sealing film that covers the upper surfaces of the temporary sealing film and the second electrode layer, and the side end surfaces formed by the step (A).

Description

Technical Field

[0001] The present disclosure relates to a substrate processing method and a substrate processing device. Background Art

[0002] Patent document 1 discloses a display device having a plurality of pixels arranged in a matrix. The display device comprises: a substrate; a plurality of first electrodes, which are arranged on an insulating surface of the substrate and correspond to a plurality of pixels; and an insulator partition wall, which surrounds the first electrode and protrudes upward from the surface of the first electrode. Furthermore, the display device comprises: an organic conductor film, which is arranged on the insulator partition wall and the first electrode; an organic thin film, which is arranged on the organic conductor and contains an organic compound capable of electroluminescence; and a second electrode, which is arranged on the organic thin film. The relationship between the film thickness T1 of the organic conductor film on the first electrode, the film thickness T2 of the organic conductor film on the boundary between the first electrode and the insulator partition wall, and the film thickness T3 of the organic conductor film on the insulator partition wall is T2>T1>T3.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-178136 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] The technology according to the present disclosure suppresses electrical crosstalk between adjacent pixels without impairing the sealing performance of the sealing film.

[0008] Solutions for solving problems

[0009] One embodiment of the present disclosure is a substrate processing method for processing a substrate, in which a plurality of first electrode layers and an insulating layer surrounding the first electrode layers and protruding upward compared to the first electrode layers are arranged on the surface of the substrate, a light-emitting layer is formed on each of the first electrode layers, a second electrode layer is formed in a manner covering the light-emitting layer and the insulating layer, a temporary sealing film covering the second electrode layer is formed, and a mask is formed on the temporary sealing film. The substrate processing method includes the following steps: step (A), using the mask to remove at least the portions of the temporary sealing film and the second electrode layer respectively located on the insulating layer; and step (B), forming a sealing film covering the upper surfaces of the temporary sealing film and the second electrode layer respectively and the side end surfaces formed by the step (A).

[0010] Effects of the Invention

[0011] According to the present disclosure, it is possible to suppress electrical crosstalk between adjacent pixels without impairing the sealing performance of the sealing film. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a plan view schematically showing the structure of the substrate processing apparatus according to the present embodiment.

[0013] Figure 2 It is a longitudinal sectional view schematically showing the structure of the processing module.

[0014] Figure 3 This is a flowchart for explaining an example of a substrate processing sequence.

[0015] Figure 4 It is a partial schematic cross-sectional view showing the state of the substrate after each step of the substrate processing sequence.

[0016] Figure 5 It is a schematic cross-sectional view for explaining the state of the organic film layer on the substrate prepared in the preparation step.

[0017] Figure 6 It is a partially enlarged schematic diagram showing the state of the surface of the substrate after the removal step.

[0018] Figure 7 It is a diagram for explaining the edge frame region of the substrate. DETAILED DESCRIPTION

[0019] In recent years, organic EL (Electro-Luminescence) display devices have attracted attention as display devices. An organic EL display device has a plurality of organic EL elements, each of which has a structure in which an organic EL layer including a light-emitting layer is sandwiched between a pair of electrode layers. In addition, among the materials constituting the organic EL element, such as organic compounds as materials of the organic EL layer, there are materials that are easily modified by moisture, oxygen, etc. Therefore, a sealing film is provided in the organic EL display device to seal the easily modified portion.

[0020] In such an organic EL display device, when the organic EL element is small, electrical crosstalk between the organic EL elements, i.e., between pixels, sometimes becomes a problem. Therefore, various structures for suppressing crosstalk in organic EL devices (hereinafter referred to as crosstalk suppression structures) have been proposed. In addition, in the case where the crosstalk suppression structure is a structure that may expose the above-mentioned easily modifiable portion, the structure also needs to be covered with the above-mentioned sealing film. However, depending on the shape of the crosstalk suppression structure, etc., the sealing performance of the sealing film may sometimes be impaired.

[0021] Therefore, the technology according to the present disclosure suppresses electrical crosstalk between adjacent pixels without impairing the sealing performance of the sealing film.

[0022] Hereinafter, a substrate processing method and a substrate processing apparatus according to the present embodiment will be described with reference to the accompanying drawings. In addition, in the present specification and the accompanying drawings, elements having substantially the same functional configuration are denoted by the same reference numerals, and repeated descriptions are omitted.

[0023] <Substrate processing apparatus 1>

[0024] Figure 1 It is a plan view schematically showing the structure of the substrate processing apparatus according to the present embodiment.

[0025] Figure 1 The substrate processing device 1 is used to process a substrate, specifically, to manufacture an OLED (Organic Light Emitting Diode) device such as an organic EL display device including a plurality of organic EL elements.

[0026] The substrate processing system 1 has a structure in which a carrier station 10 and a processing station 11 are integrally connected. The carrier station 10 is used to carry in and out a carrier C capable of accommodating a plurality of substrates G. The processing station 11 has a plurality of processing modules 40 for performing a predetermined process on the substrates G under reduced pressure. The carrier station 10 and the processing station 11 are connected via a load lock module 12.

[0027] The load lock module 12 includes a load lock chamber 13 configured to switch the interior of the chamber between an atmospheric pressure state and a vacuum state.

[0028] The carrier station 10 includes a conveying mechanism 20 .

[0029] The transfer mechanism 20 transfers the substrate G between the carrier C placed on the carrier stage 21 and the load lock module 12 (specifically, the load lock chamber 13) under atmospheric pressure. The transfer mechanism 20 includes a transfer arm 20a that supports the substrate G when transferring the substrate G.

[0030] The processing station 11 includes a vacuum transfer module 30 and a processing module 40. A plurality of processing modules 40 are provided in the processing station 11 (three in the example shown in the figure).

[0031] The vacuum transfer module 30 has a vacuum transfer chamber 31 in which the interior is maintained in a reduced pressure state (vacuum state). The vacuum transfer chamber 31 is connected to the load lock chamber 13 of the load lock module 12 via a gate valve G1. In addition, a gate valve G2 is also provided on the transfer mechanism 20 side of the load lock chamber 13.

[0032] In addition, the vacuum transfer chamber 31 is connected to each vacuum processing chamber 41 described later via a gate valve G3. A transfer mechanism 32 for transferring a substrate G is provided in the vacuum transfer chamber 31. The transfer mechanism 32 transfers the substrate G in and out of the processing module 40 (specifically, the vacuum processing chamber 41) and the load lock module 12 (specifically, the load lock chamber 13). The transfer mechanism 32 has a transfer arm 32a for supporting the substrate G when transferring the substrate G.

[0033] In the present embodiment, the processing module 40 performs etching of the first insulating inorganic film described later, etching of the cathode layer described later, etching of the organic film layer described later, formation of the second inorganic insulating film described later, etc. That is, in the present embodiment, the processing module 40 functions as a removal unit and a film forming unit involved in the present disclosure.

[0034] Each of the processing modules 40 includes a vacuum processing chamber 41 in which the above-mentioned etching, film formation, etc. are performed on the substrate G in a reduced pressure chamber.

[0035] Furthermore, the substrate processing apparatus 1 includes a control unit 50 .

[0036] The control unit 50 includes, for example, a computer having a processor such as a CPU, a memory, etc., and has a storage unit (not shown) for storing various information. A program including instructions for a processing sequence to be executed by the substrate processing apparatus 1 is stored in the storage unit. In addition, the program may be recorded in a computer-readable storage medium and installed from the storage medium to the control unit 50. In addition, the storage medium may be a transient storage medium or a non-transient storage medium.

[0037] <Processing module 40>

[0038] Figure 2 It is a longitudinal sectional view schematically showing the structure of the process module 40 .

[0039] The processing module 40 is configured as, for example, a plasma processing apparatus that performs a process using plasma, ie, plasma processing, on the substrate G. As shown in the drawing, the processing module 40 includes a container body 100 having a bottomed polygonal cylindrical shape.

[0040] The container body 100 is formed of a conductive material such as aluminum, and the container body 100 is electrically grounded. Corrosive gases are often used in plasma processing, and therefore, in order to improve corrosion resistance, the inner wall surface of the container body 100 may also be subjected to corrosion-resistant coating treatment such as anodizing treatment. In addition, an opening is formed on the upper surface of the container body 100. The opening is airtightly blocked by a rectangular metal window 120 that is insulated from the container body 100, specifically, by the metal window 120 and a metal frame 110 described later. The space surrounded by the container body 100 and the metal window 120 becomes a processing space K1 where the substrate G that is the processing object during plasma processing is located, and the space above the metal window 120 becomes an antenna chamber K2 where a high-frequency antenna (plasma antenna) 190 described later is arranged. At the vacuum transfer chamber 31 (refer to FIG. 3 ) of the container body 100, a high-frequency antenna (plasma antenna) 190 described later is disposed. Figure 1 ) side wall is provided with a loading / unloading port (not shown) for loading / unloading the substrate G into / from the processing space K1 and a gate valve G3 (see Figure 1 ).

[0041] A mounting table 130 is provided at the lower side of the processing space K1 to face the metal window 120 . The mounting table 130 includes a table body 131 whose upper surface is a substrate mounting surface for mounting the substrate G. The table body 131 is provided on the bottom surface of the container body 100 via legs 132 .

[0042] The stage main body 131 is provided with a base 131 a made of a conductive material such as aluminum and an electrostatic holding plate 131 b for holding the substrate G by electrostatic attraction.

[0043] The base 131a is connected to a high frequency power source 141 via a matching device 140. The high frequency power source 141 supplies high frequency power for bias, for example, high frequency power of 3.2 MHz, to the base 131a, thereby attracting ions in the plasma generated in the processing space K1 to the substrate G.

[0044] An exhaust port 101 is formed in the bottom wall of the container body 100 , and an exhaust unit 150 including a vacuum pump or the like is connected to the exhaust port 101 . The exhaust unit 150 reduces the pressure in the processing space K1 .

[0045] A metal frame 110, which is a rectangular frame body formed of a metal material such as aluminum, is provided on the upper surface side of the side wall of the container body 100. A sealing member 111 for keeping the processing space K1 airtight is provided between the container body 100 and the metal frame 110. The container body 100, the metal frame 110, and the metal window 120 constitute a processing container that is configured in a decompressible manner and accommodates the mounting table 130, and also constitutes the aforementioned vacuum processing chamber 41.

[0046] The metal window 120 is formed, for example, in a rectangular shape when viewed from above. In addition, the metal window 120 functions as a shower head for supplying a processing gas to the processing space K1. For example, a large number of gas ejection holes 121 for ejecting the processing gas downward and a diffusion chamber 122 for diffusing the processing gas are formed in the metal window 120, and the gas ejection holes 121 are connected to the diffusion chamber 122.

[0047] In addition, the metal window 120 is electrically insulated from the metal frame 110 by the insulating member 123 .

[0048] For example, etching gas supply units 200 to 202 and a film-forming gas supply unit 203 are connected to the diffusion chamber 122 via a supply pipe 210 .

[0049] The etching gas supply unit 200 supplies etching gas for the inorganic insulating film.

[0050] The etching gas supply unit 201 supplies etching gas for the cathode layer.

[0051] The etching gas supply unit 202 supplies etching gas for the organic film layer.

[0052] The film-forming gas supply unit 204 supplies a film-forming gas for forming an inorganic insulating film.

[0053] The etching gas supply units 200 to 202 and the film-forming gas supply unit 203 each include an on-off valve (not shown) for switching between starting and stopping gas supply, a flow controller (not shown) for adjusting the flow rate of the supplied gas, etc. The etching gas supply units 200 to 202 and the film-forming gas supply unit 203 are configured to be able to adjust the mixing ratio when supplying a mixed gas in which a plurality of gases are mixed.

[0054] Furthermore, a purge gas supply unit (not shown) for supplying a purge gas such as an inert gas is connected to the diffusion chamber 122 .

[0055] The space surrounded by the metal window 120 , the side wall portion 181 , and the top plate portion 180 constitutes an antenna chamber K2 . The high-frequency antenna 190 is disposed inside the antenna chamber K2 so as to face the metal window 120 .

[0056] The high frequency antenna 190 is disposed to be separated from the metal window 120 via a spacer (not shown) formed of, for example, an insulating material.

[0057] The high frequency antenna 190 is connected to the high frequency power supply 143 via the matching device 142. For example, a high frequency power of 13.56 MHz is supplied from the high frequency power supply 143 via the matching device 142 to the high frequency antenna 190. Thus, during the plasma processing, an induced electric field is formed inside the processing space K1 via the metal window 120, and the processing gas ejected from the gas ejection hole 121 is plasmatized by the induced electric field.

[0058] <Substrate Processing Sequence>

[0059] Next, an example of a substrate processing sequence including a processing sequence executed by the substrate processing apparatus 1 will be described. Figure 3 This is a flowchart for explaining an example of a substrate processing sequence. Figure 4 1 is a partial schematic cross-sectional view showing the state of the substrate G after each step in the substrate processing sequence. Figure 5 It is a schematic cross-sectional view for explaining the state of an organic film layer described later on the substrate G prepared in step S1. Figure 6 It is a partially enlarged schematic diagram showing the state of the surface of the substrate G after step S2.

[0060] (Step S1)

[0061] First, if Figure 3 As shown, the following substrate G is prepared.

[0062] like Figure 4 As shown in (A), the substrate G prepared in this step S1 has a plurality of anode layers Ca as first electrode layers formed on the substrate surface. In addition, the substrate G prepared in this step S1 has an insulating layer Di formed on the substrate surface that surrounds the anode layer Ca and protrudes upward from the anode layer Ca. Furthermore, the substrate G prepared in this step S1 has a light-emitting layer formed on each anode layer Ca. Specifically, an EL layer EL including a light-emitting layer is formed on each anode layer Ca. In addition, the substrate G prepared in this step S1 has a cathode layer Cc as a second electrode layer formed in a manner covering the EL layer EL and the insulating layer Di. Specifically, an organic film layer OL is formed in a manner covering the EL layer EL and the insulating layer Di, and a cathode layer Cc is formed on the organic film layer OL, that is, an organic film layer OL covering the EL layer EL and the insulating layer Di is formed under the cathode layer Cc. Furthermore, the substrate G prepared in this step S1 has a first inorganic insulating film Zi1 as a temporary sealing film covering the cathode layer Cc formed. Furthermore, on the substrate G prepared in this step S1 , a photoresist mask (hereinafter referred to as a resist mask) PRM is formed as a mask on the first inorganic insulating film Zi1 .

[0063] The substrate G is composed of, for example, a glass substrate, but may also be composed of a ceramic substrate, a plastic substrate, a metal substrate, or the like.

[0064] The anode layer Ca is formed on the substrate surface in an aligned manner. For example, indium tin oxide (ITO) is used as the material of the anode layer Ca. A known method can be used to form the anode layer Ca.

[0065] The insulating layer Di divides the pixel area. The anode layer Ca is formed in the pixel area on the surface of the substrate. The insulating layer Di electrically insulates the adjacent anode layers Ca. The insulating layer Di can be formed by a known method. Specifically, the insulating layer Di is formed by a lithography process using a resist (e.g., a photolithography process using a photoresist).

[0066] The EL layer EL is formed on the anode layer Ca, specifically, in contact with the upper surface of the anode layer Ca. Regarding the color of the light-emitting layer included in the EL layer EL, for example, any one of R (red), G (green), and B (blue) is predetermined for each anode layer Ca. The EL layer EL may also have other layers such as a hole transport layer in addition to the light-emitting layer. As the material of the light-emitting layer of the EL layer EL, an organic light-emitting substance is used that can be injected with electrons and holes and the injected charges move so that the holes and electrons recombine to emit light. The layers constituting the EL layer are formed, for example, using a mask (not shown) that only exposes the anode layer Ca. For the formation method and material of the EL layer EL, a known formation method and material can be used.

[0067] A plurality of (specifically, two) EL layers EL may be provided at intervals in the up-down direction for each anode layer Ca. In this case, the lowermost EL layer EL is formed in contact with the upper surface of the anode layer Ca. In this embodiment, as the EL layer EL, the lower EL layer ELb is provided on the lower side, and the upper EL layer ELt is provided on the upper side.

[0068] The organic film layer OL is a layer composed of an organic material that covers the EL layer EL and the insulating layer Di together, for example, Figure 5 As shown, it includes an electron injection layer (EIL: Electron Injection Layer) Li and an electron transport layer (ETL: Electron Transport Layer) Lt.

[0069] When a plurality of EL layers EL are vertically spaced apart for each anode layer Ca, the organic film layer OL includes a charge generation layer (CGL) Lc as an intermediate electrode layer serving as a third electrode layer. The charge generation layer Lc is formed between the EL layers EL arranged vertically.

[0070] The electron injection layer Li, the electron transport layer Lt, and the charge generation layer Lc are common between pixel regions, that is, between pixels.

[0071] In the present embodiment, the organic film layer OL has a tandem structure in which OLED structures are stacked in the up-and-down direction, and includes, for example, a lower organic film layer OLb and an upper organic film layer OLt.

[0072] like Figure 4 As shown in (A), the lower organic film layer OLb is formed in contact with the upper surfaces of the lower EL layer ELb and the insulating layer Di. The upper EL layer ELt is formed in contact with the upper surface of the portion of the lower organic film layer OLb located above the anode layer Ca. Figure 5 As shown, the lower organic film layer OLb includes a charge generation layer Lc. Specifically, the lower organic film layer OLb includes an electron transport layer Lt, an electron injection layer Li, and a charge generation layer Lc in order from the bottom. Thus, an upper EL layer ELt is formed in contact with the charge generation layer Lc of the lower organic film layer OLb.

[0073] like Figure 4 As shown in (A), the upper organic film layer OLt is formed in contact with the upper surface of the upper EL layer ELt and the upper surface of the portion of the lower organic film layer OLb located above the insulating layer Di. Figure 5 As shown, the upper organic film layer OLt includes an electron transport layer Lt and an electron injection layer Li in order from the bottom.

[0074] Above the anode layer Ca, an EL layer EL (specifically, an upper EL layer ELt) is formed between the lower organic film layer OLb and the upper organic film layer OLt, and above the insulating layer Di, no EL layer EL is formed between the lower organic film layer OLb and the upper organic film layer OLt.

[0075] In addition, each layer constituting the organic film layer OL is formed as a continuous film without using a mask, for example, over the entire surface. As for the formation method and material of each layer constituting the organic film layer OL, a known formation method and material can be used. In addition, when the substrate G has a plurality of device formation regions described later, each layer constituting the organic film layer OL can be formed as a continuous film for each device formation region.

[0076] In addition, the thickness of the organic film layer OL is, for example, 0.1 μm to 1.0 μm on the insulating layer Di.

[0077] like Figure 4 As shown in (A), the cathode layer Cc covers the EL layer EL and the insulating layer Di together. Specifically, the cathode layer Cc is formed in contact with the upper surface of the organic film layer OL that covers the EL layer EL and the insulating layer Di together, and more specifically, is formed in contact with the upper surface of the upper organic film layer OLt.

[0078] This cathode layer Cc is common among pixels, similarly to the electron injection layer Li and the like.

[0079] In addition, the cathode layer Cc is formed as a continuous film by forming a film on the entire surface without using a mask, similarly to each layer constituting the organic film layer OL. As the formation method and material of the cathode layer Cc, a known formation method and material can be used.

[0080] In addition, the thickness of the cathode layer Cc is, for example, 0.01 μm to 0.1 μm.

[0081] The first inorganic insulating film Zi1 is a film that seals the cathode layer Cc, specifically, a film that seals the cathode layer Cc and the organic film layer OL. The first inorganic insulating film Zi1 is formed in contact with the upper surface of the cathode layer Cc. The first inorganic insulating film Zi1 can suppress the cathode layer Cc and the organic film layer OL from being modified by moisture, oxygen, etc. when the resist mask PRM is formed.

[0082] In addition, the first inorganic insulating film Zi1 is formed as a continuous film without using a mask and on the entire surface, similarly to the cathode layer Cc, etc. The material of the first inorganic insulating film Zi1 can be, for example, any one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON) or a combination thereof. The first inorganic insulating film Zi1 can be formed by a known method.

[0083] In addition, the thickness of the first inorganic insulating film Zi1 is, for example, 0.1 μm to 1.5 μm.

[0084] The formation of the resist mask PRM is performed, for example, by exposing and developing a photoresist film after forming the photoresist film in a manner covering the first inorganic insulating film Zi1. The resist mask PRM is formed in a manner that exposes the portion of the first inorganic insulating film Zi1 between adjacent pixels and covers the other portions of the first inorganic insulating film Zi1. Specifically, the resist mask PRM is formed in a manner that exposes the portion of the first inorganic insulating film Zi1 between pixels where the distance between pixels is the shortest and covers the other portions of the first inorganic insulating film Zi1.

[0085] In addition, the thickness of the resist mask PRM is, for example, 0.5 μm to 2.5 μm.

[0086] In this step S1, specifically, first, the above-mentioned substrate G is taken out from the carrier C by the conveying arm 20a of the conveying mechanism 20, and the gate valve G2 is set to an open state. After that, the substrate G is moved into the load interlock module 12 (specifically, into the load interlock chamber 13) by the conveying arm 20a. Next, the gate valve G2 is set to a closed state to seal the load interlock chamber 13 and reduce the pressure. When the pressure in the load interlock chamber 13 becomes below the specified pressure, the gate valve G1 is set to an open state, and the substrate G is taken out from the load interlock chamber 13 by the conveying arm 32a of the conveying mechanism 32, and moved into the vacuum conveying chamber 31. Next, after the gate valve G1 is set to a closed state, the gate valve G3 corresponding to the desired processing module 40 is set to an open state. Next, the substrate G is carried into the processing module 40 (specifically, into the vacuum processing chamber 41) by the transfer arm 32a and placed on the upper surface of the table body 131 of the mounting table 130. After that, the gate valve G3 is set to a closed state. Then, the exhaust unit 150 exhausts the processing space K1 until the pressure in the processing space K1 reaches a predetermined pressure.

[0087] In addition, this step S1 may include at least any one of the steps of forming the anode layer Ca, forming the insulating layer Di, forming the EL layer EL, forming the cathode layer Cc, and forming the first inorganic insulating film Zi1. Furthermore, this step S1 may include the step of forming the organic film layer OL. In the case where this step S1 includes both the step of forming the anode layer Ca and the step of forming the insulating layer Di, for example, the former step is performed first.

[0088] (Step S2)

[0089] Next, portions of the first inorganic insulating film Zi1 and the cathode layer Cc located on the insulating layer Di are removed using the resist mask PRM. Specifically, portions of the first inorganic insulating film Zi1, the cathode layer Cc, and the organic film layer OL located on the insulating layer Di are removed using the resist mask PRM.

[0090] This step S2 includes step S2a and step S2b.

[0091] (Step S2a)

[0092] In step S2a, if Figure 4 As shown in (B), a portion of the first inorganic insulating film Zi1 located on the insulating layer Di is removed using the resist mask PRM, thereby forming a mask ZiM for the first inorganic insulating film Zi1.

[0093] Specifically, for example, while the exhaust of the processing space K1 by the exhaust unit 150 continues, an etching gas for an inorganic insulating film is supplied from the etching gas supply unit 200 to the processing space K1 via the diffusion chamber 122 and the gas ejection hole 121 as a processing gas. Thereafter, when the pressure in the processing space K1 reaches a desired level, high-frequency power is supplied from the high-frequency power supply 143 to the high-frequency antenna 190, thereby generating an induced electric field in the processing space K1 via the metal window 120. In addition, the etching gas in the processing space K1 is plasmatized by the induced electric field, generating a high-density inductively coupled plasma. Then, the ions in the plasma are attracted to the substrate G by the high-frequency power for bias supplied from the high-frequency power supply 141 to the table body 131 of the mounting table 130. As a result, the first inorganic insulating film Zi1 is removed via the resist mask PRM, and the pattern of the resist mask PRM is transferred to the first inorganic insulating film Zi1. Thus, a mask (hereinafter referred to as an inorganic mask) ZiM for the first inorganic insulating film Zi1 is formed.

[0094] In addition, the removal, i.e., etching, of the first inorganic insulating film Zi1 is performed, for example, until the portion of the first inorganic insulating film Zi1 exposed from the resist mask PRM disappears. At the time point when the removal of the first inorganic insulating film Zi1 is completed, the resist mask PRM may remain on the first inorganic insulating film Zi1. That is, the inorganic mask ZiM may also be a mask formed by stacking the removed first inorganic insulating film Zi1 and the resist mask PRM.

[0095] After the removal of the first inorganic insulating film Zi1 is completed, the power supply from the high frequency power supplies 141 and 143 and the supply of the etching gas from the etching gas supply unit 200 are stopped, and the processing space K1 is purged.

[0096] (Step S2b)

[0097] In step S2b following step S2a, if Figure 4 As shown in (C), the portions of the cathode layer Cc and the organic film layer OL located on the insulating layer Di are removed using the inorganic mask ZiM.

[0098] Specifically, the portion of the cathode layer Cc located on the insulating layer Di is removed using the inorganic mask ZiM, and then the portion of the organic film layer OL located on the insulating layer Di is removed using the inorganic mask ZiM.

[0099] More specifically, for example, while the exhaust of the processing space K1 by the exhaust unit 150 continues, the etching gas for the cathode layer is supplied from the etching gas supply unit 201 to the processing space K1 via the diffusion chamber 122 and the gas ejection hole 121 as the processing gas. Thereafter, when the pressure in the processing space K1 reaches the desired pressure, high-frequency power is supplied from the high-frequency power supply 143 to the high-frequency antenna 190, thereby generating an induced electric field in the processing space K1 via the metal window 120. In addition, the etching gas in the processing space K1 is plasmatized by the induced electric field, generating a high-density inductively coupled plasma. Then, the ions in the plasma are attracted to the substrate G by the high-frequency power for bias supplied from the high-frequency power supply 141 to the table body 131 of the mounting table 130. As a result, the cathode layer Cc is removed via the inorganic mask ZiM.

[0100] The cathode layer Cc is removed, that is, the etching is performed until the portion of the cathode layer Cc exposed from the inorganic mask ZiM disappears, for example.

[0101] After the cathode layer Cc is removed, the power supply from the high frequency power supplies 141 and 143 and the supply of the etching gas from the etching gas supply unit 201 are stopped, and the processing space K1 is purged.

[0102] Afterwards, for example, while the exhaust of the processing space K1 by the exhaust unit 150 is continued, an etching gas for the organic film layer OL is supplied from the etching gas supply unit 202 via the diffusion chamber 122 and the gas ejection hole 121 into the processing space K1 as a processing gas. Afterwards, when the pressure in the processing space K1 reaches the desired pressure, high-frequency power is supplied from the high-frequency power supply 143 to the high-frequency antenna 190, thereby generating an induced electric field in the processing space K1 via the metal window 120. In addition, the etching gas in the processing space K1 is plasmatized by the induced electric field, generating a high-density inductively coupled plasma. Then, the ions in the plasma are attracted to the substrate G by the high-frequency power for bias supplied from the high-frequency power supply 141 to the stage body 131 of the mounting table 130. As a result, the layers constituting the organic film layer OL are removed sequentially from the top through the inorganic mask ZiM.

[0103] Alternatively, the etching gas may be different for each type of layer constituting the organic film layer OL.

[0104] The removal of the organic film layer OL, namely etching, is performed until at least the portion of the charge generation layer Lc of the organic film layer OL exposed from the inorganic mask ZiM disappears. Alternatively, the removal of the organic film layer OL may be performed until all portions of the organic film layer OL exposed from the inorganic mask ZiM disappear.

[0105] After the removal of the organic film layer OL is completed, the power supply from the high frequency power supplies 141 and 143 and the supply of the etching gas from the etching gas supply unit 202 are stopped, and the processing space K1 is purged.

[0106] Through this step S2, if Figure 4 (C) and Figure 6 As shown, a groove T penetrating the cathode layer Cc is formed between adjacent anode layers Ca, i.e., adjacent pixels, on the surface of the substrate G. As a result, the cathode layer Cc of one pixel is physically discontinuous with the cathode layers Cc of other pixels adjacent to the one pixel in the adjacent direction of the pixels. That is, the cathode layer Cc is cut off by the groove T between adjacent pixels. In addition, in the case where a plurality of EL layers EL are provided at intervals in the up-down direction for each anode layer Ca, i.e., each pixel, the groove T penetrates to at least the charge generation layer Lc from the top layer of the organic film layer OL. As a result, the charge generation layer Lc of one pixel is physically discontinuous with the charge generation layer Lc of the other pixels mentioned above in the adjacent direction of the pixels. That is, the charge generation layer Lc is cut off by the groove T between adjacent pixels.

[0107] Furthermore, the cathode layer Cc of one pixel may be physically continuous with the cathode layer Cc of the other pixel via a portion other than the groove T. Similarly, the charge generation layer Lc of one pixel may be physically continuous with the charge generation layer Lc of the other pixel via a portion other than the groove T.

[0108] In addition, at the stage where step S2 is completed, the side end surface of the cathode layer Cc formed by step S2 is not covered by other layers and is exposed. At the stage where step S2 is completed, the side end surface of the cathode layer Cc constituting the groove T formed by step S2 is not covered by other layers and is exposed. More specifically, at the stage where step S2b is completed, the side end surfaces of the cathode layer Cc constituting the groove T and the organic film layer OL formed by steps S2a and S2b are not covered by other layers and are exposed.

[0109] Furthermore, in step S2, the portion of the cathode layer Cc located on the insulating layer Di may be removed in such a manner that the side end surfaces of the first inorganic insulating film Zi1 and the cathode layer Cc become non-parallel inclined surfaces relative to the thickness direction of the substrate G. More specifically, in step S2, the portion of the cathode layer Cc located on the insulating layer Di may be removed in such a manner that the side end surfaces of the first inorganic insulating film Zi1, the cathode layer Cc, and the organic film layer OL become non-parallel inclined surfaces relative to the thickness direction of the substrate G. This can be achieved by adjusting the selectivity of the etching target layer relative to the etching mask. Specifically, this can be achieved by adjusting the etching selectivity of the first inorganic insulating film Zi1 relative to the resist mask PRM, the etching selectivity of the cathode layer Cc relative to the inorganic mask ZiM, and the etching selectivity of the organic film layer OL relative to the inorganic mask ZiM. The etching selectivity can be changed, for example, by adjusting any one of the following (a) to (c).

[0110] (a) Pressure in the processing space K1 during etching

[0111] (b) Output ratio of high frequency power for plasma generation and high frequency power for bias

[0112] (c) Mixing ratio when the etching gas is composed of a mixed gas.

[0113] In addition, the thickness of the resist mask PRM formed on the substrate G is adjusted in advance so that the resist mask PRM disappears at the stage of completing step S2, or a process of reducing the thickness of the resist mask PRM is performed before the process of removing the cathode layer Cc. The thickness of the resist mask PRM is reduced by, for example, ashing.

[0114] (Step S3)

[0115] Afterwards, if Figure 4 As shown in (D), a second inorganic insulating film Zi2 is formed as a sealing film covering the upper surfaces of the first inorganic insulating film Zi1 and the cathode layer Cc and the side end surfaces formed by step S2. The second inorganic insulating film Zi2 is formed in a manner that is in contact with the upper surface of the first inorganic insulating film Zi1 and in contact with the above-mentioned side end surfaces of the first inorganic insulating film Zi1 and the cathode layer Cc constituting the groove T.

[0116] In this step S3, specifically, a second inorganic insulating film Zi2 is formed to cover the upper surfaces of the first inorganic insulating film Zi1, the cathode layer Cc, and the organic film layer OL, and the side end surfaces formed by step S2. The second inorganic insulating film Zi2 is formed in contact with the upper surface of the first inorganic insulating film Zi1 and in contact with the above-mentioned side end surfaces of the first inorganic insulating film Zi1, the cathode layer Cc, and the organic film layer OL constituting the groove T.

[0117] In this step S3, more specifically, without exposing the substrate G to the atmosphere after step S2, the substrate processing device 1 that performs step S2 forms a second inorganic insulating film Zi2 by CVD to seal the first inorganic insulating film Zi1, the cathode layer Cc, and the organic film layer OL. Thus, the side end surfaces of the cathode layer Cc and the organic film layer OL exposed after step S2 are covered together by the second inorganic insulating film Zi2. In the case where a portion of the organic film layer OL other than the above-mentioned side end surface is exposed after step S2, the portion is also covered by the second inorganic insulating film Zi2.

[0118] The second inorganic insulating film Zi2 is formed as a continuous film. Also, the second inorganic insulating film Zi2 is formed of, for example, any one of SiN, SiO, and SiON or a combination thereof, similarly to the first inorganic insulating film Zi1.

[0119] In this step S3, more specifically, for example, while the exhaust of the processing space K1 by the exhaust unit 150 continues, the film-forming gas for the inorganic insulating film is supplied from the film-forming gas supply unit 203 via the diffusion chamber 122 and the gas ejection hole 121 into the processing space K1 as the processing gas. Thereafter, when the pressure in the processing space K1 reaches the desired pressure, high-frequency power is supplied from the high-frequency power supply 143 to the high-frequency antenna 190, thereby generating an induced electric field in the processing space K1 via the metal window 120. In addition, the film-forming gas in the processing space K1 is plasmatized by the induced electric field, generating a high-density inductively coupled plasma. Then, the ions in the plasma are attracted to the substrate G by the high-frequency power for bias supplied from the high-frequency power supply 141 to the table body 131 of the mounting table 130. As a result, the second inorganic insulating film Zi2 is formed on the entire surface of the substrate G.

[0120] The formation of the second inorganic insulating film Zi2 is performed until the second inorganic insulating film Zi2 is formed to a desired thickness.

[0121] After the formation of the second inorganic insulating film Zi2 is completed, the power supply from the high frequency power supplies 141 and 143 and the supply of the film forming gas from the film forming gas supply unit 203 are stopped, and the processing space K1 is purged.

[0122] Thereafter, the substrate G is carried out.

[0123] Specifically, the substrate G is unloaded from the processing module 40 to the carrier C on the carrier mounting table 21 in the reverse process of the process of loading the substrate G into the processing module 40 .

[0124] Thus, a series of substrate processing sequences are completed.

[0125] In addition, the above-mentioned step S2 and step S3 are performed under the control of the control unit 50.

[0126] <Main effects of this embodiment)

[0127] As described above, the substrate processing sequence involved in the present embodiment includes a removal process, in which the resist mask PRM is used to remove the first inorganic insulating film Zi1 and the cathode layer Cc, respectively, which are located on the insulating layer Di. Through this removal process, the cathode layer Cc to be removed is formed in a manner covering the organic EL layer and the insulating layer Di, that is, it is formed across the adjacent pixel regions divided by the insulating layer Di. In addition, through this removal process, a groove T is formed on the surface of the substrate G, and the cathode layer Cc is cut off by the groove T between the pixel regions, that is, between the pixels. Therefore, according to the substrate processing sequence involved in the present embodiment, electrical crosstalk between adjacent pixels can be suppressed. Specifically, electrical crosstalk applied to the cathode layer Cc between adjacent pixels can be suppressed.

[0128] Furthermore, the substrate processing sequence according to the present embodiment includes a sealing step, in which, after the removal step, a second inorganic insulating film Zi2 is formed to cover the upper surfaces of the first inorganic insulating film Zi1 and the cathode layer Cc and the side end surfaces formed by the removal step. Thus, the entire cathode layer Cc including the side end surfaces constituting the groove T is sealed.

[0129] As a method for cutting the cathode layer between adjacent pixels that is different from the present embodiment (hereinafter referred to as a comparative method), the following method is considered. That is, the following method: before forming the cathode layer, a groove with a high aspect ratio (i.e., depth relative to width) is formed in advance between adjacent pixels on the surface of the substrate, and then the cathode layer is formed. However, in this comparative method, if the aspect ratio of the groove is not high, the coverage of the surface constituting the groove is not reduced, and the groove is covered by the cathode layer, so that the cathode layer cannot be cut between adjacent pixels. In addition, if the aspect ratio of the groove is high, when the surface constituting the groove is easily modified by moisture, oxygen, etc., it is sometimes difficult to properly seal the surface constituting the groove with a sealing film because the coverage of the surface constituting the groove is low.

[0130] In contrast, in the substrate processing sequence according to the present embodiment, the cathode layer Cc formed in advance so as to straddle adjacent pixels is cut between adjacent pixels by forming a groove T on the surface of the substrate G. According to this method, the cathode layer can be cut between adjacent pixels without increasing the aspect ratio of the groove T, that is, without reducing the coverage of the surface constituting the groove T. Therefore, after the above-mentioned removal step of forming the groove T, the side end surface of the cathode layer Cc constituting the groove T can be covered with a high coverage by the second inorganic insulating film Zi2 as a sealing film after the groove T is formed. That is, it is possible to suppress the sealing performance of the sealing film from being damaged by the groove T.

[0131] As described above, according to the present embodiment, electrical crosstalk between adjacent pixels can be suppressed without impairing the sealing performance of the sealing film.

[0132] Furthermore, according to the present embodiment, the side end surfaces of the organic film layer OL formed in advance so as to straddle between adjacent pixels, which constitute the groove T, can be covered with high coverage by the second inorganic insulating film Zi2 .

[0133] In particular, the charge generation layer Lc can be cut between adjacent pixels by the groove T, similarly to the cathode layer Cc, and the side end surface of the groove T can be covered with the second inorganic insulating film Zi2 with high coverage. Therefore, according to this embodiment, the electrical crosstalk applied to the charge generation layer Lc between adjacent pixels can be suppressed without impairing the sealing performance of the sealing film.

[0134] Furthermore, in the aforementioned comparative method, the groove needs to be formed with high precision, and the film forming conditions of the cathode layer to be cut need to be strict. In contrast, in the substrate processing involved in this embodiment, the shape of the groove is not required to be highly precise, and the film forming conditions of the cathode layer to be cut are relatively loose. Therefore, it is easy to set the conditions for groove formation and cathode layer film formation. The same is true for the charge generation layer Lc.

[0135] In addition, in the present embodiment, the cathode layer Cc is physically cut off between adjacent pixels by the groove T. Therefore, compared with the case where the thickness of the cathode layer is adjusted to electrically cut off the cathode layer between adjacent pixels as in the technique disclosed in Japanese Patent Application Laid-Open No. 2020-178136, according to the present embodiment, the electrical crosstalk applied to the cathode layer Cc between adjacent pixels can be more reliably suppressed. The same is true for the electrical crosstalk applied to the charge generation layer Lc between adjacent pixels.

[0136] In the substrate processing sequence involved in this embodiment, unlike the technology disclosed in Japanese Patent Publication No. 2020-178136, when forming the cathode layer Cc, it is not necessary to make the thickness of the cathode layer Cc locally different. Therefore, the cathode layer Cc can be easily formed. The same is true for the charge generation layer Lc.

[0137] Furthermore, according to the substrate processing sequence involved in this embodiment, by adjusting the selectivity of the etching target layer with respect to the mask, the side end surfaces of the first inorganic insulating film Zi1, the cathode layer Cc, and the organic film layer OL constituting the groove T can be inclined surfaces that are not parallel to the thickness direction of the substrate G. As a result, the coverage of the second inorganic insulating film Zi2 on the side end surfaces can be improved, that is, the second inorganic insulating film Zi2 can be more reliably formed on the side end surfaces. As a result, the side end surfaces can be more appropriately sealed.

[0138] In addition, in this embodiment, the cathode layer Cc and the organic film layer OL are formed on the entire surface without using a mask. Therefore, the throughput is higher than when the cathode layer Cc and the organic film layer OL are formed for each color such as red, blue, and green.

[0139] (Variation Example)

[0140] In addition, Figure 4 In the example (C), the groove T is formed at the center between adjacent pixels of the insulating layer Di, but the groove T is not limited to this position as long as it exists above the insulating layer Di. That is, according to this embodiment, the formation position of the groove T can be adjusted within the range above the insulating layer Di.

[0141] like Figure 7 As shown, the substrate G includes a device forming region DR where an anode layer Ca and an insulating layer Di are formed, and a frame region FR surrounding the device forming region DR when viewed from above. Alternatively, the first inorganic insulating film Zi1 and the cathode layer Cc may be formed not only in the device forming region DR of the substrate G prepared in step S1, but also in the frame region FR, and the first inorganic insulating film Zi1 and the cathode layer Cc may be removed from the frame region FR in step S2. Specifically, the first inorganic insulating film Zi1, the cathode layer Cc, and the organic film layer OL may be formed in the frame region FR of the substrate G prepared in step S1, and the first inorganic insulating film Zi1, the cathode layer Cc, and the organic film layer OL may be removed from the frame region FR in step S2.

[0142] Thus, even if a mask is not used when forming the first inorganic insulating film Zi1 and the like, the first inorganic insulating film Zi1 and the like can be prevented from existing in the edge frame region FR at the stage of forming the second inorganic insulating film Zi2 as a sealing film. Therefore, the number of masks can be reduced, and thus, cost reduction can be achieved. In addition, it is possible to suppress the adverse effects of substances attached to the mask on the substrate G and the device during film formation.

[0143] In the above example, step S2 and step S3 are performed by one processing module 40 , but part of step S2 and step S3 may also be performed by another one or more processing modules 40 .

[0144] However, by performing all the processes of step S2 and step S3 in one processing module 40, that is, by performing all the processes of step S2 and step S3 in one vacuum processing chamber 41, it is not necessary to transport the substrate G between the processes. Therefore, it is possible to suppress a decrease in productivity due to the introduction of a new process and the attachment of foreign matter to the substrate G during transportation.

[0145] It should be considered that all points of the embodiments disclosed this time are illustrative and not restrictive. The above embodiments may be omitted, replaced, or changed in various ways without departing from the attached claims and their gist. For example, the constituent elements of the above embodiments may be combined arbitrarily. According to the arbitrary combination, the functions and effects of each structural element involved in the combination can be obtained, and other functions and effects that are clearly defined by those skilled in the art based on the description of this specification can be obtained.

[0146] In addition, the effects described in this specification are only illustrative or exemplary effects and not limiting effects. That is, the technology involved in this disclosure can play other effects that can be clearly identified by those skilled in the art based on the description of this specification as a supplement or replacement for the above-mentioned effects.

[0147] In addition, the following structural examples also belong to the technical scope of the present disclosure.

[0148] (1) A substrate processing method, wherein a substrate is processed, wherein:

[0149] In the substrate,

[0150] A plurality of first electrode layers and an insulating layer surrounding the first electrode layers and protruding upward from the first electrode layers are arranged on the surface of the substrate.

[0151] A light-emitting layer is formed on each of the first electrode layers.

[0152] A second electrode layer is formed so as to cover the light emitting layer and the insulating layer.

[0153] A temporary sealing film covering the second electrode layer is formed,

[0154] A mask is formed on the temporary sealing film,

[0155] The substrate processing method comprises the following steps:

[0156] Step (A), removing at least the portions of the temporary sealing film and the second electrode layer located on the insulating layer using the mask; and

[0157] Step (B) of forming a sealing film that covers the upper surfaces of the temporary sealing film and the second electrode layer and the side end surfaces formed in the step (A).

[0158] (2) The substrate processing method according to (1), wherein:

[0159] In the substrate, an organic film layer covering the light-emitting layer and the insulating layer is formed under the second electrode layer.

[0160] In the step (A), the temporary sealing film, the second electrode layer, and the organic film layer are removed from their respective portions located on the insulating layer using the mask.

[0161] In the step (B), the sealing film is formed to cover the upper surfaces of the temporary sealing film, the second electrode layer, and the organic film layer, and the side end surfaces formed in the step (A).

[0162] (3) The substrate processing method according to (2), wherein:

[0163] In the step (A), the mask of the temporary sealing film is formed by removing the portion of the temporary sealing film located on the insulating layer using the mask, and the portion of each of the second electrode layer and the organic film layer located on the insulating layer is removed using the mask of the temporary sealing film.

[0164] (4) A substrate processing method according to (3), wherein:

[0165] The organic film layer includes a third electrode layer,

[0166] In the step (A), a portion of the organic film layer located on the insulating layer up to at least the third electrode layer is removed using the mask of the temporary sealing film.

[0167] (5) A substrate processing method according to any one of (1) to (4), wherein:

[0168] The mask is a photoresist mask.

[0169] (6) The substrate processing method according to any one of (1) to (5), wherein:

[0170] The temporary sealing film is an inorganic insulating film.

[0171] (7) A substrate processing method according to any one of (1) to (6), wherein:

[0172] In the step (A), the portion located on the insulating layer is removed so that the side end surface becomes an inclined surface that is not parallel to the thickness direction of the substrate.

[0173] (8) The substrate processing method according to any one of (1) to (7), wherein:

[0174] The substrate has a device forming region where the plurality of first electrode layers and the insulating layer are formed and a frame region surrounding the device forming region.

[0175] In the step (A), the temporary sealing film and the second electrode layer are each removed from the portion located on the frame region.

[0176] (9) A substrate processing device for processing a substrate, wherein:

[0177] In the substrate,

[0178] A plurality of first electrode layers and an insulating layer surrounding the first electrode layers and protruding upward from the first electrode layers are arranged on the surface of the substrate.

[0179] A light-emitting layer is formed on each of the first electrode layers.

[0180] A second electrode layer is formed so as to cover the light emitting layer and the insulating layer.

[0181] A temporary sealing film covering the second electrode layer is formed,

[0182] A mask is formed on the temporary sealing film,

[0183] The substrate processing device comprises:

[0184] a removing section that uses the mask to remove at least a portion of each of the temporary sealing film and the second electrode layer located on the insulating layer; and

[0185] A film forming section forms a sealing film covering the upper surfaces of the temporary sealing film and the second electrode layer and the side end surfaces formed by the removal section.

[0186] Description of Reference Numerals

[0187] 1: substrate processing device; 40: processing module; Ca: anode layer; Cc: cathode layer; Di: insulating layer; EL: organic EL layer; G: substrate; PRM: resist mask; Zi1: first inorganic insulating film; Zi2: second inorganic insulating film.

Claims

1. A substrate processing method, processing a substrate, wherein: In the substrate, A plurality of first electrode layers and an insulating layer surrounding the first electrode layers and protruding upward from the first electrode layers are arranged on the surface of the substrate. A light-emitting layer is formed on each of the first electrode layers. A second electrode layer is formed so as to cover the light emitting layer and the insulating layer. A temporary sealing film covering the second electrode layer is formed, A mask is formed on the temporary sealing film, The substrate processing method comprises the following steps: Step (A), removing at least the portions of the temporary sealing film and the second electrode layer located on the insulating layer using the mask; and Step (B) of forming a sealing film that covers the upper surfaces of the temporary sealing film and the second electrode layer and the side end surfaces formed in the step (A).

2. The substrate processing method according to claim 1, wherein: In the substrate, an organic film layer covering the light-emitting layer and the insulating layer is formed under the second electrode layer. In the step (A), the temporary sealing film, the second electrode layer, and the organic film layer are removed from their respective portions located on the insulating layer using the mask. In the step (B), the sealing film is formed to cover the upper surfaces of the temporary sealing film, the second electrode layer, and the organic film layer, and the side end surfaces formed in the step (A).

3. The substrate processing method according to claim 2, wherein: In the step (A), the mask of the temporary sealing film is formed by removing the portion of the temporary sealing film located on the insulating layer using the mask, and the portion of each of the second electrode layer and the organic film layer located on the insulating layer is removed using the mask of the temporary sealing film.

4. The substrate processing method according to claim 3, wherein: The organic film layer includes a third electrode layer, In the step (A), a portion of the organic film layer located on the insulating layer up to at least the third electrode layer is removed using the mask of the temporary sealing film.

5. The substrate processing method according to any one of claims 1 to 4, wherein: The mask is a photoresist mask.

6. The substrate processing method according to any one of claims 1 to 4, wherein: The temporary sealing film is an inorganic insulating film.

7. The substrate processing method according to any one of claims 1 to 4, wherein: In the step (A), the portion located on the insulating layer is removed so that the side end surface becomes an inclined surface that is not parallel to the thickness direction of the substrate.

8. The substrate processing method according to any one of claims 1 to 4, wherein: The substrate has a device forming region where the plurality of first electrode layers and the insulating layer are formed and a frame region surrounding the device forming region. In the step (A), the temporary sealing film and the second electrode layer are each removed from the portion located on the frame region.

9. A substrate processing device for processing a substrate, wherein: In the substrate, A plurality of first electrode layers and an insulating layer surrounding the first electrode layers and protruding upward from the first electrode layers are arranged on the surface of the substrate. A light-emitting layer is formed on each of the first electrode layers. A second electrode layer is formed so as to cover the light emitting layer and the insulating layer. A temporary sealing film covering the second electrode layer is formed, A mask is formed on the temporary sealing film, The substrate processing device comprises: a removing section that uses the mask to remove at least a portion of each of the temporary sealing film and the second electrode layer located on the insulating layer; and A film forming section forms a sealing film covering the upper surfaces of the temporary sealing film and the second electrode layer and the side end surfaces formed by the removal section.

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