Analog front-end circuit with rapid monitoring function and working method of analog front-end circuit

Abstract

The invention discloses a fast monitoring analog front-end circuit and a working method thereof. The fast monitoring analog front-end circuit comprises a capacitive coupling chopping instrument amplifier module, an electrode imbalance elimination module and a fast stabilization module. The capacitive coupling chopping instrument amplifier module is used for amplifying an input signal in proportion and modulating noise to a high frequency band; the electrode imbalance elimination module is used for eliminating interference of electrode imbalance; and the rapid stabilization module is used for pulling the initial working voltage of key nodes in the capacitive coupling chopping instrument amplifier module and the electrode imbalance elimination module to common-mode voltage. According to the invention, the waiting time of the analog front-end circuit in the early stage of measuring the bio-electricity signal is greatly shortened, and compared with the traditional bio-signal analog front-end circuit, the real and effective bio-electricity signal can be obtained in a shorter time.

Description

Technical Field

[0001] The invention relates to a fast monitoring analog front-end circuit and a working method thereof, belonging to the technical field of integrated circuits. Background Art

[0002] With the development of electronic science and technology, concepts such as smart healthcare and telemedicine have been proposed. Smart healthcare builds an interconnected platform between patients and medical institutions. Based on the rapidly developing Internet of Things technology, patients' real-time physical data is recorded and transmitted to the medical care platform, which not only relieves the pressure of tight medical resources, but also improves the efficiency of monitoring the condition.

[0003] The devices that support the monitoring of human health data mainly include wearable devices, implantable chips, etc., which mainly extract the bioelectric signals of the human body. Among them, the electrocardiograph (ECG) signal can provide information on heart rate and heart rate variability, and can be used to monitor the heart, sleep, psychological stress, etc.; the electroencephalogram (EEG) signal can be used to monitor brain health, and has applications: using an implantable closed-loop stimulation system to suppress epileptic seizures in real time.

[0004] Bioelectric signals are often collected through electrodes and need to be effectively amplified before they can be processed to generate useful biological information. Therefore, as the core part of the bioelectric signal acquisition system, the design quality of the analog front end (AFE) directly determines the quality of signal extraction, which needs to overcome various interferences such as electrode imbalance, 50 / 60 Hz power frequency signals, various noises, motion artifacts, etc.

[0005] In order to obtain high-quality bioelectric signals, it is necessary to take into account various indicators such as noise, electrode offset suppression, common mode rejection ratio, and passband. Since signal acquisition uses electrodes to contact the surface to be measured, considering the differences in the contact environment, there is often a DC electrode offset of more than ten to several hundred millivolts. On the basis of using chopper capacitor coupling instrument amplification technology, a special circuit must be designed to eliminate the interference of electrode offset. Engineering and academia often use DC servo loop technology to suppress electrode offset. Its core is the integrator, which includes RC integrator, switched capacitor integrator, Gm-C integrator, etc. When using an RC integrator, an extremely large RC constant is often required to limit the high-pass frequency point of the circuit, so its integration time is very long. It may even take several seconds from the start of measuring the signal to the entire analog front-end circuit entering a steady state.

[0006] Therefore, the technical problem to be solved by the present invention is how to shorten the time it takes for the biological signal acquisition analog front-end circuit to reach a steady state during measurement. Summary of the invention

[0007] Purpose: To overcome the deficiencies in the prior art, the present invention provides a fast monitoring analog front-end circuit and a working method thereof.

[0008] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is:

[0009] In a first aspect, a fast monitoring analog front-end circuit includes: a capacitive coupled chopper instrument amplifier module, an electrode offset elimination module and a fast stabilization module.

[0010] The capacitive coupled chopper instrument amplifier module is used to amplify the input signal in proportion and modulate the noise to a high frequency band.

[0011] The electrode offset elimination module is used to eliminate interference caused by electrode offset.

[0012] The fast stabilization module is used to pull the initial working voltage of key nodes in the capacitive coupling chopper instrument amplifier module and the electrode offset elimination module to the common mode voltage.

[0013] As a preferred solution, the capacitive-coupled chopper instrument amplifier module includes: a first input end of the chopper CH1 is connected to the input end Vinp, a second input end is connected to the input end Vinn, a first output end of the chopper CH1 is connected to one end of the capacitor Cin1, a second output end of the chopper CH1 is connected to one end of the capacitor Cin2, the first output end of the chopper CH1 serves as a node A, the second output end of the chopper CH1 serves as a node B, the other end of the capacitor Cin1 serves as a node C, and the other end of the capacitor Cin2 serves as a node D.

[0014] The node C and the node D are connected to the input end of the transconductance amplifier Gm1 respectively, the output end of the transconductance amplifier Gm1 is connected to the input end of the chopper CH2, the first output end of the chopper CH2 is connected to the first input end of the transconductance amplifier Gm2, the second output end of the chopper CH2 is connected to the second input end of the transconductance amplifier Gm2, the first output end of the transconductance amplifier Gm2 is used as the output end Voutp, and the second output end of the transconductance amplifier Gm2 is used as the output end Voutn. The output end Voutp is connected to the first input end of the chopper CH4, the output end Voutn is connected to the second input end of the chopper CH4, the first output end of the chopper CH4 is used as the node E, the second output end of the chopper CH4 is used as the node F, the node E is connected to one end of the capacitor Cfb1, the node F is connected to one end of the capacitor Cfb2, the other end of the capacitor Cfb1 is also connected to the node D, and the capacitor Cfb2 is also connected to the node C.

[0015] The electrode offset elimination module includes: the output end Voutn is connected to the first input end of the RC integrator, the output end Voutp is connected to the second input end of the RC integrator, the output end of the RC integrator is connected to the input end of the chopper CH3, the first output end of the chopper CH3 is used as a node G, the second output end of the chopper CH3 is used as a node H, the node G is connected to one end of the capacitor Chp2, the node H is connected to one end of the capacitor Chp1, the other end of the capacitor Chp2 is also connected to the node D, and the capacitor Chp1 is also connected to the node C.

[0016] The node C is also connected to one end of the first pseudo resistor, and the other end of the first pseudo resistor is connected to the common mode potential Vcom.

[0017] The node D is also connected to one end of the second pseudo resistor, and the other end of the second pseudo resistor is connected to the common mode potential Vcom.

[0018] The fast stabilization module comprises: a first switch tube, the source of the first switch tube is connected to the output end V of the pseudo resistor R1 in the integration circuit P The gate of the first switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0019] A second switch tube, the source of which is connected to the output terminal V of the pseudo resistor R2 in the integration circuit. N The gate of the second switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0020] A third switch tube, wherein the source of the third switch tube is connected to the output terminal Voutn, and the gate of the third switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0021] A fourth switch tube, wherein the source of the fourth switch tube is connected to the output terminal Voutp, and the gate of the fourth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0022] A fifth switch tube, the source of the fifth switch tube is connected to the node A, and the gate of the fifth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0023] The sixth switch tube, the source of the sixth switch tube is connected to the node B, and the gate of the sixth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0024] A seventh switch tube, wherein the source of the seventh switch tube is connected to the node C, and the gate of the seventh switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0025] The source of the eighth switch tube is connected to the node D, and the gate of the eighth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0026] The ninth switch tube, the source of the ninth switch tube is connected to the node E, and the gate of the ninth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0027] The tenth switch tube, the source of the tenth switch tube is connected to the node F, and the gate of the tenth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0028] The eleventh switch tube, the source of the eleventh switch tube is connected to the node G, and the gate of the eleventh switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0029] A twelfth switch tube, the source of the twelfth switch tube is connected to the node H, and the gate of the twelfth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0030] As a preferred solution, it also includes: a ripple elimination module, wherein the first input end of the ripple elimination module is connected to the output end Voutp, the second input end of the ripple elimination module is connected to the output end Voutn, the first output end of the ripple elimination module is connected to the first input end of the chopper CH2, and the second output end of the ripple elimination module is connected to the second input end of the chopper CH2. The ripple elimination module is used to extract high-frequency ripples in the signal, the high-frequency ripples are demodulated to the baseband, and the baseband signal is integrated to obtain the offset compensation current.

[0031] As a preferred solution, it further includes: an impedance enhancement module, wherein a first input end of the impedance enhancement module is connected to the output end Voutp, a second input end of the impedance enhancement module is connected to the output end Voutn, a first output end of the impedance enhancement module is also connected to a node A, and a second output end of the impedance enhancement module is also connected to a node B. The impedance enhancement module is used to increase the input impedance.

[0032] As a preferred solution, the ripple elimination module includes: a capacitor Ch1 and a capacitor Ch2, the output end Voutp is connected to one end of the capacitor Ch1, the output end Voutn is connected to one end of the capacitor Ch2, the other end of the capacitor Ch1 is connected to the first input end of the chopper CH6, the other end of the capacitor Ch2 is connected to the second input end of the chopper CH6, the first output end of the chopper CH6 is connected to the first input end of the chopper CH7, the second output end of the chopper CH6 is connected to the second input end of the chopper CH7, and the first output end of the chopper CH7 is connected to the first input end of the transconductance amplifier Gm3. The second output end of the chopper CH7 is connected to the second input end of the transconductance amplifier Gm3, the first output end of the transconductance amplifier Gm3 is connected to the first input end of the chopper CH8, the second output end of the transconductance amplifier Gm3 is connected to the second input end of the chopper CH8, the first output end of the chopper CH8 is connected to the first input end of the transconductance amplifier Gm4, the second output end of the chopper CH8 is connected to the second input end of the transconductance amplifier Gm4, the first output end of the transconductance amplifier Gm4 is connected to the first output end of the transconductance amplifier Gm1, and the second output end of the transconductance amplifier Gm4 is connected to the second output end of the transconductance amplifier Gm1. A capacitor Ci1 is connected between the first output end of the chopper CH6 and the first output end of the chopper CH8, and a capacitor Ci2 is connected between the second output end of the chopper CH6 and the second output end of the chopper CH8.

[0033] As a preferred solution, the RC integration circuit includes: a pseudo resistor R1 and a pseudo resistor R2, wherein the input end and the output end Voutp of the pseudo resistor R1, and the output end Voutp of the pseudo resistor R1 P The output terminal V of the pseudo resistor R1 is connected to the first input terminal of the transconductance amplifier Gm5. N It is connected to the second input terminal of the transconductance amplifier Gm5, the first output terminal of the transconductance amplifier Gm5 is connected to the first output terminal of the chopper CH3, the second output terminal of the transconductance amplifier Gm5 is connected to the second output terminal of the chopper CH3, a capacitor Cint1 is connected between the first input terminal of the transconductance amplifier Gm5 and the first output terminal of the transconductance amplifier Gm5, and a capacitor Cint2 is connected between the second input terminal of the transconductance amplifier Gm5 and the second output terminal of the transconductance amplifier Gm5.

[0034] As a preferred solution, the circuit for generating the common-mode potential Vcom includes: a transconductance amplifier Gm6, a first input terminal of the transconductance amplifier Gm6 is connected to a reference voltage VBG output by a reference circuit, an output terminal of the transconductance amplifier Gm6 is connected in series with a resistor R1 and a resistor R2, and the other end of the resistor R2 is grounded, the output terminal of the transconductance amplifier Gm6 is also connected to a second input terminal of the transconductance amplifier Gm6, and the output of the common end of the resistor R1 and the resistor R2 is used as the common-mode potential Vcom.

[0035] As a preferred solution, it also includes: a peripheral circuit, which includes a reference circuit, a low-dropout linear regulator and a clock circuit.

[0036] Wherein, the reference circuit is used to provide reference current and reference voltage required for the operation of each module.

[0037] The low voltage drop linear regulator is used to provide a stable power supply voltage to the overall circuit.

[0038] The clock circuit is used to provide clock signals required for the operation of each module.

[0039] In a second aspect, a method for operating a fast monitoring analog front-end circuit comprises the following steps:

[0040] Power up the analog front-end circuit for fast monitoring.

[0041] When the bioelectric signal is input and measured, the control potential V is given to all the first switch tube to the twelfth switch tube. CTRL Input a high level delay to turn on the first switch to the twelfth switch, and the node V P , node V N , node V OUTP , node V OUTN , the potentials of node A, node B, node C, node D, node E, node F, node G, and node H are pulled to the common mode potential Vcom.

[0042] The control potential V CTRL It returns to a low level, the first to twelfth switch tubes are turned off, waiting for the electrode offset elimination module to eliminate the offset interference, and the analog front-end circuit for rapid monitoring outputs the amplified effective bioelectric signal.

[0043] As a preferred solution, the duration of the high-level delay is 1 ms.

[0044] Beneficial effects: The present invention provides a fast monitoring analog front-end circuit and its working method, including peripheral circuits (reference circuit, low voltage drop linear regulator and clock circuit), capacitive coupling chopper instrument amplifier module, impedance enhancement module, electrode offset elimination module, ripple elimination module, and fast stabilization module. Its main advantages are: the time to eliminate electrode offset interference to achieve steady state is greatly shortened, and it has a wider application prospect.

[0045] The present invention gives an initial potential to some endpoints in the circuit when the analog front-end circuit measures the initial state of the bioelectric signal, so as to greatly shorten the waiting time in the early stage of the analog front-end circuit measuring the bioelectric signal. Compared with the traditional biosignal analog front-end circuit, the present invention can obtain real and effective bioelectric signals in a shorter time. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a schematic diagram of the structure of the analog front-end circuit of the present invention.

[0047] Figure 2 It is a schematic diagram of the structure of the ripple elimination module of the present invention.

[0048] Figure 3 It is a schematic diagram of the structure of the integration circuit of the present invention.

[0049] Figure 4 It is a timing diagram of the fast stabilization module of the present invention.

[0050] Figure 5 Schematic diagram of the Vcom generating circuit structure of the present invention. DETAILED DESCRIPTION

[0051] The following is a clear and complete description of the technical solutions in the examples of the present invention in conjunction with the accompanying drawings in the examples of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the protection scope of the present invention.

[0052] The present invention will be further described below in conjunction with specific embodiments.

[0053] Embodiment 1:

[0054] This embodiment introduces a fast monitoring analog front-end circuit, including: a peripheral circuit, a capacitive coupling chopper instrument amplifier module, a ripple elimination module, an electrode offset elimination module, an impedance enhancement module and a fast stabilization module.

[0055] Wherein, the peripheral circuit includes a reference circuit, a low voltage difference linear regulator and a clock circuit.

[0056] Wherein, the reference circuit is used to provide reference current and reference voltage required for the operation of each module.

[0057] The low voltage drop linear regulator is used to provide a stable power supply voltage to the overall circuit.

[0058] The clock circuit is used to provide clock signals required for the operation of each module.

[0059] The capacitive coupled chopper instrument amplifier module is used to amplify the input signal in proportion and modulate the noise to a high frequency band.

[0060] Among them, there are choppers CH1, CH2 and CH4, transconductance amplifiers Gm1 and Gm2, input capacitors Cin1 and Cin2, feedback capacitors Cfb1 and Cfb2, and miller compensation capacitors Cm1 and Cm2. CH1 modulates the input signal to high frequency, Cin1 and Cin2 are the input capacitors of the capacitor feedback structure, and the feedback capacitors Cfb1 and Cfb2 define the signal amplification factor, which is Cin1,2 / Cfb1,2. Gm1 and Gm2 are the first and second stages of the transconductance amplifier respectively. The purpose of using a two-stage structure is to obtain a larger open-loop gain. CH2 demodulates the signal modulated to high frequency by CH1 to the baseband, and obtains the output signal after amplification by Gm2. The capacitors Cm1 and Cm2 across Gm2 are miller compensation capacitors, and the purpose is to maintain the stability of the loop. CH4 is the chopper of the feedback path.

[0061] The ripple elimination module is used to extract high-frequency ripples in the signal. The high-frequency ripples are demodulated to the base frequency, and then the base frequency signal is integrated to obtain the offset compensation current.

[0062] Among them, it includes input capacitors Ch1 and Ch2, choppers CH7, CH8 and CH9, transconductance amplifiers Gm3 and Gm4, and integral capacitors Ci1 and Ci2. Function of Gm1: The equivalent input offset of the amplifier will be modulated into a square wave by the chopper CH2, and then integrated on the miller capacitor to generate high-frequency ripple. Using the ripple elimination module, Ch1 and Ch2 extract the output high-frequency ripple, demodulate it to the base frequency through the chopper CH7, and then integrate it and convert it into an offset compensation current by Gm4, which is injected into the output end of Gm1 to compensate for the input offset. Among them, CH8 and CH9 can eliminate the influence of the equivalent input offset of Gm3.

[0063] The impedance enhancement module is used to enhance the input impedance.

[0064] The chopper CH5 and the positive feedback capacitors Cpf1 and Cpf2 are included, and the input impedance is improved by compensating the charge and discharge of the input capacitors Cin1 and Cin2 by the chopper CH1.

[0065] The electrode offset elimination module is used to eliminate the interference of electrode offset.

[0066] Among them, it includes an integrator, a chopper CH3 and coupling capacitors Chp1 and Chp2, wherein the integrator is composed of pseudo resistors R1 and R2, a transconductance amplifier Gm5, and integral capacitors Cint1 and Cint2. The RC integrator integrates the low-frequency component of the output voltage, and then generates a compensation voltage for the input electrode offset by CH3, Chp1 and Chp2, and finally eliminates the interference of the electrode offset.

[0067] The fast stabilization module is used to pull the initial working voltage of key nodes in the capacitive coupling chopper instrument amplifier module and the electrode offset elimination module to the common mode voltage.

[0068] Among them, it is composed of 12 MOS tubes NMOS<1:12>. By pulling the input and output voltages of capacitors Cin1, Cin2, Cfb1, Cfb2, Chp1, Chp2 and the amplifier in the offset cancellation module to the common mode voltage at the beginning of the circuit operation, the time it takes to reach a steady state after the circuit is powered on is reduced.

[0069] Further, such as Figure 1 As shown, the capacitive coupling chopper instrument amplifier module includes: a chopper CH1, a first input end of the chopper CH1 is connected to an input end Vinp, a second input end is connected to an input end Vinn, a first output end of the chopper CH1 is connected to one end of a capacitor Cin1, a second output end of the chopper CH1 is connected to one end of a capacitor Cin2, a first output end of the chopper CH1 is used as a node A, a second output end of the chopper CH1 is used as a node B, the other end of the capacitor Cin1 is used as a node C, and the other end of the capacitor Cin2 is used as a node D.

[0070] The node C and the node D are connected to the input end of the transconductance amplifier Gm1 respectively, the output end of the transconductance amplifier Gm1 is connected to the input end of the chopper CH2, the first output end of the chopper CH2 is connected to the first input end of the transconductance amplifier Gm2, the second output end of the chopper CH2 is connected to the second input end of the transconductance amplifier Gm2, the first output end of the transconductance amplifier Gm2 is used as the output end Voutp, and the second output end of the transconductance amplifier Gm2 is used as the output end Voutn. The output end Voutp is connected to the first input end of the chopper CH4, the output end Voutn is connected to the second input end of the chopper CH4, the first output end of the chopper CH4 is used as the node E, the second output end of the chopper CH4 is used as the node F, the node E is connected to one end of the capacitor Cfb1, the node F is connected to one end of the capacitor Cfb2, the other end of the capacitor Cfb1 is also connected to the node D, and the capacitor Cfb2 is also connected to the node C.

[0071] The output terminal Voutn is connected to the first input terminal of the RC integrator, the output terminal Voutp is connected to the second input terminal of the RC integrator, the output terminal of the RC integrator is connected to the input terminal of the chopper CH3, the first output terminal of the chopper CH3 serves as the node G, the second output terminal of the chopper CH3 serves as the node H, the node G is connected to one end of the capacitor Chp2, the node H is connected to one end of the capacitor Chp1, the other end of the capacitor Chp2 is also connected to the node D, and the capacitor Chp1 is also connected to the node C.

[0072] The node C is also connected to one end of the first pseudo resistor, and the other end of the first pseudo resistor is connected to the common mode potential Vcom.

[0073] The node D is also connected to one end of the second pseudo resistor, and the other end of the second pseudo resistor is connected to the common mode potential Vcom.

[0074] The invention also includes: a first switch tube, the source of which is connected to the output end V of the pseudo resistor R1 in the integration circuit. P The gate of the first switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0075] A second switch tube, the source of which is connected to the output terminal V of the pseudo resistor R2 in the integration circuit. N The gate of the second switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0076] A third switch tube, wherein the source of the third switch tube is connected to the output terminal Voutn, and the gate of the third switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0077] A fourth switch tube, wherein the source of the fourth switch tube is connected to the output terminal Voutp, and the gate of the fourth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0078] A fifth switch tube, the source of the fifth switch tube is connected to the node A, and the gate of the fifth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0079] The sixth switch tube, the source of the sixth switch tube is connected to the node B, and the gate of the sixth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0080] A seventh switch tube, wherein the source of the seventh switch tube is connected to the node C, and the gate of the seventh switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0081] The source of the eighth switch tube is connected to the node D, and the gate of the eighth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0082] The ninth switch tube, the source of the ninth switch tube is connected to the node E, and the gate of the ninth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0083] The tenth switch tube, the source of the tenth switch tube is connected to the node F, and the gate of the tenth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0084] The eleventh switch tube, the source of the eleventh switch tube is connected to the node G, and the gate of the eleventh switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0085] A twelfth switch tube, the source of the twelfth switch tube is connected to the node H, and the gate of the twelfth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

[0086] Furthermore, it also includes: a ripple elimination module, wherein the first input end of the ripple elimination module is connected to the output end Voutp, the second input end of the ripple elimination module is connected to the output end Voutn, the first output end of the ripple elimination module is connected to the first input end of the chopper CH2, and the second output end of the ripple elimination module is connected to the second input end of the chopper CH2.

[0087] Furthermore, it also includes: an impedance enhancement module, wherein the first input end of the impedance enhancement module is connected to the output end Voutp, the second input end of the impedance enhancement module is connected to the output end Voutn, the first output end of the impedance enhancement module is also connected to node A, and the second output end of the impedance enhancement module is also connected to node B.

[0088] Further, such as Figure 2 As shown, the ripple elimination module includes: a capacitor Ch1 and a capacitor Ch2, the output end Voutp is connected to one end of the capacitor Ch1, the output end Voutn is connected to one end of the capacitor Ch2, the other end of the capacitor Ch1 is connected to the first input end of the chopper CH6, the other end of the capacitor Ch2 is connected to the second input end of the chopper CH6, the first output end of the chopper CH6 is connected to the first input end of the chopper CH7, the second output end of the chopper CH6 is connected to the second input end of the chopper CH7, the first output end of the chopper CH7 is connected to the first input end of the transconductance amplifier Gm3, and the The second output end of the chopper CH7 is connected to the second input end of the transconductance amplifier Gm3, the first output end of the transconductance amplifier Gm3 is connected to the first input end of the chopper CH8, the second output end of the transconductance amplifier Gm3 is connected to the second input end of the chopper CH8, the first output end of the chopper CH8 is connected to the first input end of the transconductance amplifier Gm4, the second output end of the chopper CH8 is connected to the second input end of the transconductance amplifier Gm4, the first output end of the transconductance amplifier Gm4 is connected to the first output end of the transconductance amplifier Gm1, and the second output end of the transconductance amplifier Gm4 is connected to the second output end of the transconductance amplifier Gm1. A capacitor Ci1 is connected between the first output end of the chopper CH6 and the first output end of the chopper CH8, and a capacitor Ci2 is connected between the second output end of the chopper CH6 and the second output end of the chopper CH8.

[0089] Further, such as Figure 3 As shown, the RC integration circuit includes: a pseudo resistor R1 and a pseudo resistor R2, an input end and an output end Voutp of the pseudo resistor R1, and an output end Voutp of the pseudo resistor R1. P The output terminal V of the pseudo resistor R1 is connected to the first input terminal of the transconductance amplifier Gm5. NIt is connected to the second input terminal of the transconductance amplifier Gm5, the first output terminal of the transconductance amplifier Gm5 is connected to the first output terminal of the chopper CH3, the second output terminal of the transconductance amplifier Gm5 is connected to the second output terminal of the chopper CH3, a capacitor Cint1 is connected between the first input terminal of the transconductance amplifier Gm5 and the first output terminal of the transconductance amplifier Gm5, and a capacitor Cint2 is connected between the second input terminal of the transconductance amplifier Gm5 and the second output terminal of the transconductance amplifier Gm5.

[0090] Further, such as Figure 5 As shown, the common mode potential Vcom generating circuit includes: a transconductance amplifier Gm6, a first input terminal of the transconductance amplifier Gm6 is connected to a reference voltage VBG output by a reference circuit, an output terminal of the transconductance amplifier Gm6 is connected in series with a resistor R1 and a resistor R2, and the other end of the resistor R2 is grounded, the output terminal of the transconductance amplifier Gm6 is also connected to a second input terminal of the transconductance amplifier Gm6, and the output of the common end of the resistor R1 and the resistor R2 is used as the common mode potential Vcom.

[0091] Furthermore, all 12 switch tubes are MOS tubes.

[0092] The reference circuit is used to provide reference voltage and current to the low voltage difference linear regulator, the clock circuit, the transconductance amplifier Gm1, the transconductance amplifier Gm2, the transconductance amplifier Gm3, the transconductance amplifier Gm4, and the transconductance amplifier Gm5.

[0093] The low dropout linear regulator is used to provide a stable power supply voltage to all modules except the reference circuit.

[0094] The clock circuit is used for providing non-overlapping clock signals to chopper CH1, chopper CH2, chopper CH3, chopper CH4, chopper CH5, chopper CH6, chopper CH7 and chopper CH8.

[0095] Embodiment 2:

[0096] This embodiment introduces a working method of a fast monitoring analog front-end circuit, including the following steps:

[0097] Power up the analog front-end circuit for fast monitoring.

[0098] When the input measures bioelectric signals, such as Figure 4 As shown, all control potentials V are given to the first switch tube to the twelfth switch tube. CTRL Input a high level delay to turn on the first switch to the twelfth switch, and the node V P , node V N , node V OUTP , node VOUTN , the potentials of node A, node B, node C, node D, node E, node F, node G, and node H are pulled to the common mode potential Vcom.

[0099] The control potential V CTRL It returns to a low level, the first to twelfth switch tubes are turned off, waiting for the electrode offset elimination module to eliminate the offset interference, and the analog front-end circuit for rapid monitoring outputs the amplified effective bioelectric signal.

[0100] Furthermore, the duration of the high-level delay is 1 ms.

[0101] Embodiment 3:

[0102] This embodiment introduces an analysis of the working principle of shortening the time required for a fast monitoring analog front-end circuit to reach a steady state after power-on, as follows:

[0103] Case 1: If capacitors Cin1, Cin2, Cfb1, Cfb2, Chp1, and Chp2 have no residual charge, after the circuit starts working, V C =V D , that is, there is no residual DC offset voltage between node C and node D. If there is an electrode offset voltage at the input terminals Vinp and Vinn, the output of the amplifier will be saturated. In the initial state, the voltage at the input terminal of the integrator is unknown, so the circuit will first adjust the input gate voltage of the integrator amplifier to the common mode level, so:

[0104]

[0105]

[0106] Where R and C are the integrating resistance and integrating capacitance of the RC integrator respectively, and V P / N (0 + ) and V N / P (0 + ) are the initial potentials of the gate of the integrating amplifier, and VDD is the saturation voltage of the amplifier output. From formula (1) and formula (2), it can be obtained that the time required for the circuit to pull the gate potential of the integrator amplifier to the common mode voltage is:

[0107]

[0108] After this, the output of the integrating amplifier needs to be integrated to the common-mode level, and the time required is:

[0109]

[0110] At this time, both the input and output of the integrating amplifier are at the common-mode potential, and finally enter the stage of eliminating electrode offset. The offset compensation voltage that the integrator needs to output is:

[0111]

[0112] Among them, Vedo is the electrode offset voltage, and the time required for this step is:

[0113]

[0114] The total time required for the whole process is:

[0115]

[0116] Case 2: If there are residual offset charges in capacitors Cin1, Cin2, Cfb1, Cfb2, Chp1, and Chp2. Considering that the input of Gm1 uses a pseudo-resistor bias, the driving ability of Vcom for nodes C and D is very weak. Then, at the beginning of the circuit operation, there is often a large offset voltage Vos between nodes C and D, sometimes even up to several hundred millivolts. If there is an electrode offset voltage at the input terminals Vinp and Vinn at this time, such that Vinp > Vinn, but if Vos is too large, making VC << VD, then Voutp < Voutn. The integrator in the electrode offset suppression module will first integrate in the opposite direction, increasing the amplitude of the square wave at the input of Gm1, which in turn increases the influence of the electrode offset interference. At the same time, Vcom pulls nodes C and D towards the common-mode point through the pseudo-resistor, continuously weakening Vos, and finally causing the output voltages Voutp and Voutn to be inverted, and the integrator will enter the offset elimination stage. Then, compared with Case 1, Case 2 has an additional time t4, which is the time for the integrator to return from reverse integration to the common-mode point again. Therefore, the total time required for Case 2 is:

[0117]

[0118] To avoid t1 and t2 mentioned in Case 1, the present invention sets the voltage V P at the amplifier input terminal of the integrator and the voltage V N , as well as the voltage V ON at the output terminal and the voltage V OPAdjust to the common mode potential. In order to avoid the time t4 mentioned in the second situation, the capacitors Cin1, Cin2, Cfb1, Cfb2, Chp1, and Chp2 should be discharged at the beginning of the circuit operation, so that the input node C and node D of the transconductance amplifier Gm1 are always at the common mode voltage. Then, the same control scheme can be adopted for the eight points of node A, node B, node C, node D, node E, node F, node G, and node H, that is, they are also pulled to the common mode voltage at the same time. Therefore, at the beginning of the present invention, by adjusting the node V P , node V N , node V OUTP , node V OUTN , the 12 nodes of node A, node B, node C, node D, node E, node F, node G, and node H are charged and discharged to the common mode voltage Vcom, and the steady-state recovery time T can be reduced to T':

[0119]

[0120] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A fast monitoring analog front-end circuit, characterized in that: include: Capacitive coupled chopper instrumentation amplifier module, electrode offset cancellation module and fast stabilization module; Wherein, the capacitive coupled chopper instrument amplifier module is used to amplify the input signal in proportion and modulate the noise to a high frequency band; The electrode offset elimination module is used to eliminate interference caused by electrode offset; The fast stabilization module is used to pull the initial working voltage of key nodes in the capacitive coupling chopper instrument amplifier module and the electrode offset elimination module to the common mode voltage.

2. The fast monitoring analog front-end circuit according to claim 1, characterized in that: The capacitive coupling chopper instrument amplifier module comprises: a first input end of a chopper CH1 is connected to an input end Vinp, a second input end is connected to an input end Vinn, a first output end of the chopper CH1 is connected to one end of a capacitor Cin1, a second output end of the chopper CH1 is connected to one end of a capacitor Cin2, a first output end of the chopper CH1 is used as a node A, a second output end of the chopper CH1 is used as a node B, another end of the capacitor Cin1 is used as a node C, and another end of the capacitor Cin2 is used as a node D; The node C and the node D are respectively connected to the input end of the transconductance amplifier Gm1, the output end of the transconductance amplifier Gm1 is connected to the input end of the chopper CH2, the first output end of the chopper CH2 is connected to the first input end of the transconductance amplifier Gm2, the second output end of the chopper CH2 is connected to the second input end of the transconductance amplifier Gm2, the first output end of the transconductance amplifier Gm2 is used as the output end Voutp, and the second output end of the transconductance amplifier Gm2 is used as the output end Voutn; the output end Voutp is connected to the first input end of the chopper CH4, the output end Voutn is connected to the second input end of the chopper CH4, the first output end of the chopper CH4 is used as the node E, the second output end of the chopper CH4 is used as the node F, the node E is connected to one end of the capacitor Cfb1, the node F is connected to one end of the capacitor Cfb2, the other end of the capacitor Cfb1 is also connected to the node D, and the capacitor Cfb2 is also connected to the node C; The node C is also connected to one end of the first pseudo resistor, and the other end of the first pseudo resistor is connected to the common mode potential Vcom; The node D is also connected to one end of the second pseudo resistor, and the other end of the second pseudo resistor is connected to the common mode potential Vcom; The electrode offset elimination module includes: the output end Voutn is connected to the first input end of the RC integrator, the output end Voutp is connected to the second input end of the RC integrator, the output end of the RC integrator is connected to the input end of the chopper CH3, the first output end of the chopper CH3 is used as a node G, the second output end of the chopper CH3 is used as a node H, the node G is connected to one end of the capacitor Chp2, the node H is connected to one end of the capacitor Chp1, the other end of the capacitor Chp2 is also connected to the node D, and the capacitor Chp1 is also connected to the node C; The fast stabilization module comprises: a first switch tube, the source of the first switch tube is connected to the output end V of the pseudo resistor R1 in the integration circuit P The gate of the first switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom; A second switch tube, the source of which is connected to the output terminal V of the pseudo resistor R2 in the integration circuit. N The gate of the second switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom; A third switch tube, wherein the source of the third switch tube is connected to the output terminal Voutn, and the gate of the third switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom; A fourth switch tube, wherein the source of the fourth switch tube is connected to the output terminal Voutp, and the gate of the fourth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom; A fifth switch tube, the source of the fifth switch tube is connected to the node A, and the gate of the fifth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom; The sixth switch tube, the source of the sixth switch tube is connected to the node B, and the gate of the sixth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom; A seventh switch tube, wherein the source of the seventh switch tube is connected to the node C, and the gate of the seventh switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom; The source of the eighth switch tube is connected to the node D, and the gate of the eighth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom; The ninth switch tube, the source of the ninth switch tube is connected to the node E, and the gate of the ninth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom; The tenth switch tube, the source of the tenth switch tube is connected to the node F, and the gate of the tenth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom; The eleventh switch tube, the source of the eleventh switch tube is connected to the node G, and the gate of the eleventh switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom; A twelfth switch tube, the source of the twelfth switch tube is connected to the node H, and the gate of the twelfth switch tube is connected to the control potential V CTRL , the drain is connected to the common mode potential Vcom.

3. The fast monitoring analog front-end circuit according to claim 1, characterized in that: Also includes: A ripple elimination module, wherein the first input end of the ripple elimination module is connected to the output end Voutp, the second input end of the ripple elimination module is connected to the output end Voutn, the first output end of the ripple elimination module is connected to the first input end of the chopper CH2, and the second output end of the ripple elimination module is connected to the second input end of the chopper CH2; the ripple elimination module is used to extract high-frequency ripples in the signal, the high-frequency ripples are demodulated to the baseband, and the baseband signal is integrated to obtain the offset compensation current.

4. The fast monitoring analog front-end circuit according to claim 3, characterized in that: Also includes: An impedance enhancement module, wherein the first input end of the impedance enhancement module is connected to the output end Voutp, the second input end of the impedance enhancement module is connected to the output end Voutn, the first output end of the impedance enhancement module is also connected to node A, and the second output end of the impedance enhancement module is also connected to node B; the impedance enhancement module is used to increase the input impedance.

5. The fast monitoring analog front-end circuit according to claim 3, characterized in that: The ripple elimination module includes: a capacitor Ch1 and a capacitor Ch2, the output end Voutp is connected to one end of the capacitor Ch1, the output end Voutn is connected to one end of the capacitor Ch2, the other end of the capacitor Ch1 is connected to the first input end of the chopper CH6, the other end of the capacitor Ch2 is connected to the second input end of the chopper CH6, the first output end of the chopper CH6 is connected to the first input end of the chopper CH7, the second output end of the chopper CH6 is connected to the second input end of the chopper CH7, the first output end of the chopper CH7 is connected to the first input end of the transconductance amplifier Gm3, the second output end of the chopper CH7 is connected to the second input end of the transconductance amplifier Gm3, and the transconductance amplifier Gm The first output end of the chopper CH3 is connected to the first input end of the chopper CH8, the second output end of the transconductance amplifier Gm3 is connected to the second input end of the chopper CH8, the first output end of the chopper CH8 is connected to the first input end of the transconductance amplifier Gm4, the second output end of the chopper CH8 is connected to the second input end of the transconductance amplifier Gm4, the first output end of the transconductance amplifier Gm4 is connected to the first output end of the transconductance amplifier Gm1, and the second output end of the transconductance amplifier Gm4 is connected to the second output end of the transconductance amplifier Gm1; a capacitor Ci1 is connected between the first output end of the chopper CH6 and the first output end of the chopper CH8, and a capacitor Ci2 is connected between the second output end of the chopper CH6 and the second output end of the chopper CH8.

6. The fast monitoring analog front-end circuit according to claim 1, characterized in that: The RC integration circuit includes: a pseudo resistor R1 and a pseudo resistor R2, an input end and an output end Voutp of the pseudo resistor R1, and an output end Voutp of the pseudo resistor R1. P The output terminal V of the pseudo resistor R1 is connected to the first input terminal of the transconductance amplifier Gm5. N It is connected to the second input terminal of the transconductance amplifier Gm5, the first output terminal of the transconductance amplifier Gm5 is connected to the first output terminal of the chopper CH3, the second output terminal of the transconductance amplifier Gm5 is connected to the second output terminal of the chopper CH3, a capacitor Cint1 is connected between the first input terminal of the transconductance amplifier Gm5 and the first output terminal of the transconductance amplifier Gm5, and a capacitor Cint2 is connected between the second input terminal of the transconductance amplifier Gm5 and the second output terminal of the transconductance amplifier Gm5.

7. The fast monitoring analog front-end circuit according to claim 1, characterized in that: The circuit for generating the common mode potential Vcom includes: a transconductance amplifier Gm6, a first input terminal of the transconductance amplifier Gm6 is connected to a reference voltage VBG output by a reference circuit, an output terminal of the transconductance amplifier Gm6 is connected in series with a resistor R1 and a resistor R2, and the other end of the resistor R2 is grounded, the output terminal of the transconductance amplifier Gm6 is also connected to a second input terminal of the transconductance amplifier Gm6, and the output of the common end of the resistor R1 and the resistor R2 is used as the common mode potential Vcom.

8. A fast monitoring analog front-end circuit according to any one of claims 1 to 7, characterized in that: Also includes: Peripheral circuits, including a reference circuit, a low-dropout linear regulator, and a clock circuit; Wherein, the reference circuit is used to provide reference current and reference voltage required for the operation of each module; The low voltage drop linear regulator is used to provide a stable power supply voltage to the overall circuit; The clock circuit is used to provide clock signals required for the operation of each module.

9. A method for operating a fast monitoring analog front-end circuit according to any one of claims 1 to 8, characterized in that: The steps include: Power on the fast monitoring analog front-end circuit; When the bioelectric signal is input and measured, the control potential V is given to all the first switch tube to the twelfth switch tube. CTRL Input a high level delay to turn on the first switch to the twelfth switch, and the node V P , node V N , node V OUTP , node V OUTN , the potentials of nodes A, B, C, D, E, F, G, and H are pulled to the common mode potential Vcom; The control potential V CTRL It returns to a low level, the first to twelfth switch tubes are turned off, waiting for the electrode offset elimination module to eliminate the offset interference, and the analog front-end circuit for rapid monitoring outputs the amplified effective bioelectric signal.

10. The working method according to claim 9, characterized in that: The duration of the high level delay is 1 ms.

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