Battery pack monitoring circuit integrated with switched capacitor temperature compensation

Abstract

The invention provides a battery pack monitoring circuit integrated with switched capacitor temperature compensation. The battery pack monitoring circuit comprises a battery pack, a low-voltage multiplexer, a high-voltage multiplexer, an incremental ADC and a digital filter. The battery pack is composed of a plurality of to-be-monitored battery modules which are connected in series; the incremental ADC is an incremental sigma-delta ADC and adopts a multi-channel input structure, and a discrete switched capacitor band-gap reference circuit is arranged in the incremental ADC; the discrete switched capacitor band-gap reference circuit and the incremental ADC adopt the same operational amplifier; a decoder for dynamically adjusting the on-off of an internal switch is arranged in the discrete switched capacitor band-gap reference circuit; the incremental ADC and the switched capacitor band-gap reference circuit share the same operational amplifier, so that the design area is saved; due to the fact that the dynamic element matching technology is arranged in the discrete switched capacitor band-gap reference circuit, the influence on the monitoring precision caused by mismatching between triodes is greatly reduced, and the monitoring precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a battery pack monitoring circuit with integrated switch capacitor temperature compensation. Background Art

[0002] Lithium-ion batteries have gradually become a widely used new energy source due to their long cycle life, low price, high energy ratio, high specific power, and no memory effect. However, the problems of differentiated performance degradation and safety hazards that often occur during the use of lithium batteries cannot be ignored. Therefore, in applications such as new energy vehicles, energy storage systems, and high-power equipment that require a large number of lithium-ion batteries, BMS (Battery Management System) is required to dynamically monitor the voltage, current, and temperature of the battery to calculate the battery status information. At the same time, it is of great significance to monitor the abnormal information of the battery, provide the battery with overvoltage protection, undervoltage protection, overtemperature protection, overcurrent protection, etc., and balance each battery according to the battery power to reduce the differences between batteries. Therefore, the research on high-precision ADC is very important.

[0003] Some lithium-ion battery pack monitoring structures are also disclosed in the prior art. For example, for a multi-cell battery monitoring chip with 6 lithium-ion batteries in series and 7 universal analog ports, 13 sets of first-order Sigma-Delta ADCs in parallel are used inside the chip to achieve parallel multi-channel monitoring. However, since this design method uses 13 first-order Sigma-Delta ADCs in parallel, the circuit power consumption and chip area are greatly increased, and the first-order Sigma-Delta ADC cannot have high accuracy. Some studies have also disclosed a complete stacked battery monitoring system, which has a built-in 12-bit SAR ADC and adopts a multiplexed low-voltage acquisition solution to monitor 7 lithium-ion battery channels. Although the SAR ADC has a high monitoring processing speed, it lacks accuracy, which makes the monitoring results inaccurate.

[0004] Therefore, the existing lithium-ion battery pack monitoring structure has the problems of high design power consumption, large occupied area and low monitoring accuracy. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a battery pack monitoring circuit with integrated switched capacitor temperature compensation.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] The present invention provides a battery pack monitoring circuit with integrated switch capacitor temperature compensation, comprising: a battery pack, a low voltage multiplexer, a high voltage multiplexer, an incremental ADC and a digital filter; the battery pack is composed of a plurality of battery modules to be monitored which are connected in series;

[0008] The low voltage multiplexer is used to select multiple control channels according to the parameters to be measured of the battery pack to obtain corresponding low voltage control channels;

[0009] The high-voltage multiplexer is used to sequentially select the voltages of the battery modules to be monitored in the battery pack to obtain a voltage selection signal;

[0010] The incremental ADC is used to convert the voltage selection signal from an analog signal to a digital signal under a low-voltage control channel to obtain a digital code stream signal; wherein the incremental ADC is an incremental Σ-Δ ADC, adopts a multi-channel input structure, and a discrete switched capacitor bandgap reference circuit is provided in the incremental ADC; the discrete switched capacitor bandgap reference circuit and the incremental ADC use the same operational amplifier; the discrete switched capacitor bandgap reference circuit is provided with a decoder for dynamically adjusting the on-off of an internal switch;

[0011] The digital filter is used to perform downsampling processing according to the digital code stream signal to obtain the monitoring result under the low-voltage channel signal corresponding to the battery module to be monitored.

[0012] Optionally, the high-voltage multiplexer is provided with an input port matching the output terminal of the battery pack; the battery pack is connected to the input terminal of the high-voltage multiplexer;

[0013] The low voltage multiplexer is provided with differential input ports having the same number as the control channels;

[0014] The output ends of the high voltage multiplexer and the low voltage multiplexer are both connected to the input end of the incremental ADC; the output end of the incremental ADC is connected to the digital filter.

[0015] Optionally, the incremental ADC comprises: a first-stage integrator, a second-stage integrator, a DAC circuit, a passive summing circuit, and a single-bit quantizer; the DAC circuit is a discrete switched capacitor bandgap reference circuit;

[0016] The first-stage integrator and the second-stage integrator have the same structure, and both include: a sampling and holding circuit and an operational amplifier;

[0017] The input end of the sampling and holding circuit in the first stage integrator is connected to the output ends of the high voltage multiplexer and the low voltage multiplexer; the output end of the sampling and holding circuit in the first stage integrator is connected to the input end of the operational amplifier in the first stage integrator; the output end of the operational amplifier in the first stage integrator is connected to the input end of the second stage integrator;

[0018] The output end of the second stage integrator is connected to the input end of the passive summing circuit; the output end of the operational amplifier in the second stage integrator is connected to the input end of the passive summing circuit;

[0019] The output end of the passive summing circuit is connected to the input end of the single-bit quantizer and the digital filter; the output end of the single-bit quantizer is connected to the input end of the DAC circuit;

[0020] The output end of the DAC circuit is connected to the output end of the sampling and holding circuit in the first stage integrator.

[0021] Optionally, the first-stage integrator is used to perform a first sampling integration process on the low-voltage channel signal and the voltage of the battery module to be monitored to obtain a first integrated output signal;

[0022] The second stage integrator is used to perform a second sampling integration process on the first integrated output signal to obtain a second integrated output signal;

[0023] The passive summing circuit is used to perform a summing operation on the first integral output signal and the second integral output signal to obtain a signal summing result;

[0024] The single-bit quantizer is used to compare the two outputs inside the signal summation result, and obtain the digital code stream signal according to the comparison result;

[0025] The DAC circuit is used to feed back different DAC output signals according to different digital code stream signals to the output end of the sampling and holding circuit in the first-stage integrator to adjust the first integrated output signal to avoid oversaturation of the first integrated output signal.

[0026] Optionally, the DAC circuit includes: a DAC feedback circuit and a VBE generating circuit.

[0027] Optionally, the DAC feedback circuit includes: switches S13 to S36, an adjustable capacitor Cf1, an adjustable capacitor Cf2, a capacitor Cf3, and a capacitor Cf4;

[0028] The first ends of switch S28, switch S26, switch S24, and switch S22 are connected to each other and to the first output terminal VBE1 of the VBE generating circuit; the first ends of switch S21, switch S23, switch S25, and switch S27 are connected to each other and to the second output terminal VBE2 of the VBE generating circuit; the second ends of switch S21 and switch S22 are connected to each other and to the first end of switch S13; the second ends of switch S23 and switch S24 are connected to each other and to the first end of switch S14; the second ends of switch S25 and switch S26 are connected to each other and to the first end of switch S15; the second ends of switch S27 and switch S28 are connected to each other and to the first end of switch S16; the second ends of switch S13 and switch S14 are connected to each other and to the first end of the adjustable capacitor Cf1; the second ends of switch S15 and switch S16 are connected to each other and to the first end of the adjustable capacitor Cf2;

[0029] The first ends of the switch S35, the switch S33, the switch S31, and the switch S29 are connected to each other and to the first output terminal VBE1 of the VBE generating circuit; the first ends of the switch S36, the switch S34, the switch S32, and the switch S30 are connected to each other and to the ground VSS; the second ends of the switch S29 and the switch S30 are connected to each other and to the first end of the switch S17; the second ends of the switch S31 and the switch S32 are connected to each other and to the first end of the switch S18; the second ends of the switch S33 and the switch S34 are connected to each other and to the first end of the switch S19; the second ends of the switch S35 and the switch S36 are connected to each other and to the first end of the switch S20; the second ends of the switch S17 and the switch S18 are connected to each other and to the first end of the capacitor Cf3; the second ends of the switch S19 and the switch S20 are connected to each other and to the first end of the capacitor Cf4;

[0030] The second end of capacitor Cf3 is connected to the second end of adjustable capacitor Cf1 and connected to the inverting input terminal Vin1p of the operational amplifier. The second end of capacitor Cf4 is connected to the first end of adjustable capacitor Cf2 and connected to the positive input terminal Vin1n of the operational amplifier.

[0031] Optionally, the VBE generating circuit includes: transistors Q1-Q16, PMOS tubes MP0-MP8, PMOS tubes MP11-MP12, PMOS tubes MP21-MP22, PMOS tubes MP31-MP32, PMOS tubes MP41-MP42, PMOS tubes MP51-MP52, PMOS tubes MP61-MP62, PMOS tubes MP71-MP72, PMOS tubes MP81-MP82, PMOS tubes MP13-MP16, PMOS tubes MP23-MP26, PMOS tubes MP33-MP36, PMOS tubes MP43-MP46, PMOS tubes MP53-MP53 -MP56, PMOS tubes MP63-MP66, PMOS tubes MP73-MP76, PMOS tubes MP83-MP86, switches S11-S12, switches S21-S22, switches S31-S32, switches S41-S42, switches S51-S52, switches S61-S62, switches S71-S72, switches S81-S82, switches S91-S92, switches S101-S102, switches S111-S112, switches S121-S122, switches S131-S132, switches S141-S142, switches S151-S152 and switches S161-S162;

[0032] The areas of transistors Q1-Q16 are equal, and the collectors of transistors Q1-Q16 are connected to their own bases; the collector of transistor Q1 is connected to the drains of PMOS tubes MP15 and MP16; the collector of transistor Q2 is connected to the drains of PMOS tubes MP13 and MP14; the collector of transistor Q3 is connected to the drains of PMOS tubes MP25 and MP26; the collector of transistor Q4 is connected to the drains of PMOS tubes MP23 and MP24; the collector of transistor Q5 is connected to the drains of PMOS tubes MP35 and MP36; the collector of transistor Q6 is connected to the drains of PMOS tubes MP35 and MP36; the collector of transistor Q7 is connected to the drains of PMOS tubes MP37 and MP38; the collector of transistor Q8 is connected to the drains of PMOS tubes MP39 and MP40; the collector of transistor Q9 is connected to the drains of PMOS tubes MP41 and MP42; the collector of transistor Q10 is connected to the drains of PMOS tubes MP43 and MP44; the collector of transistor Q11 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q12 is connected to the drains of PMOS tubes MP47 and MP42; the collector of transistor Q13 is connected to the drains of PMOS tubes MP43 and MP44; the collector of transistor Q14 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q15 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q16 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q17 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q18 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q19 is connected to the drains of PMOS tube The collector of transistor Q7 is connected to the drain of PMOS tube MP45 and PMOS tube MP46; the collector of transistor Q8 is connected to the drain of PMOS tube MP43 and PMOS tube MP44; the collector of transistor Q9 is connected to the drain of PMOS tube MP55 and PMOS tube MP56; the collector of transistor Q10 is connected to the drain of PMOS tube MP53 and PMOS tube MP54; the collector of transistor Q11 is connected to the drain of PMOS tube MP65 and PMOS tube MP66; the collector of transistor Q12 is connected to the PM The drains of the OS transistor MP63 and the PMOS transistor MP64; the collector of the transistor Q13 is connected to the drains of the PMOS transistor MP75 and the PMOS transistor MP76; the collector of the transistor Q14 is connected to the drains of the PMOS transistor MP73 and the PMOS transistor MP74; the collector of the transistor Q15 is connected to the drains of the PMOS transistor MP85 and the PMOS transistor MP86, and the collector of the transistor Q16 is connected to the drains of the PMOS transistor MP83 and the PMOS transistor MP84; the first end of the switch S11 is connected to the emitter of the transistor Q1, and the first output end VBE1 of the VBE generating circuit is connected to the switches S11, S21, and S 31. the second ends of the switches S41, S51, S61, S71, S81, S91, S101, S111, S121, S131, S141, S151 and S161; the second output end VBE2 of the VBE generating circuit is connected to the second ends of the switches S12, S22, S32, S42, S52, S62, S72, S82, S92, S102, S112, S122, S132, S142, S152 and S162;

[0033] The first ends of switch S12, switch S22, switch S32, switch S42, switch S52, switch S62, switch S72, switch S82, switch S92, switch S102, switch S112, switch S122, switch S132, switch S142, switch S152, and switch S162 are connected to the emitters of transistors Q1-Q16 in sequence; the first ends of switch S11, switch S31, switch S41, switch S51, and switch S 61. The first ends of switches S71, S81, S91, S101, S111, S121, S131, S141, S151 and S161 are connected to the emitters of transistors Q1-Q16 in sequence; the gates of PMOS tubes MP0-MP8 are connected to each other; the sources of PMOS tubes MP0-MP8 are connected to the power supply voltage VDD; the drain and gate of PMOS tube MP0 are connected to each other;

[0034] The drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP11 and the PMOS tube MP12; the drain of the PMOS tube MP2 is connected to the source of the PMOS tube MP21 and the PMOS tube MP22; the drain of the PMOS tube MP3 is connected to the source of the PMOS tube MP31 and the PMOS tube MP32; the drain of the PMOS tube MP4 is connected to the source of the PMOS tube MP41 and the PMOS tube MP42; the drain of the PMOS tube MP5 is connected to the source of the PMOS tube MP51 and the PMOS tube MP52; the drain of the PMOS tube MP6 is connected to the source of the PMOS tube MP61 and the PMOS tube MP62; the drain of the PMOS tube MP7 is connected to the source of the PMOS tube MP71 and the PMOS tube MP72; the drain of the PMOS tube MP8 is connected to the source of the PMOS tube MP81 and the PMOS tube MP82;

[0035] The gate of the PMOS tube MP11 is connected to the first output terminal A0 of the first inverter INV1; the gate of the PMOS tube MP12 is connected to the first output port B0 of the 3-8 decoder; the gate of the PMOS tube MP21 is connected to the second output terminal A1 of the first inverter INV1; the gate of the PMOS tube MP22 is connected to the second output port B1 of the 3-8 decoder; the gate of the PMOS tube MP31 is connected to the third output terminal A2 of the first inverter INV1; the gate of MP32 is connected to the third output port B2 of the 3-8 decoder; the gate of MP41 is connected to the fourth output terminal A3 of the first inverter INV1; the gate of MP42 is connected to the 3-8 decoder The gate of MP51 is connected to the fifth output terminal A4 of the first inverter INV1; the gate of MP52 is connected to the fifth output port B4 of the 3-8 decoder; the gate of MP61 is connected to the sixth output terminal A5 of the first inverter INV1; the gate of MP62 is connected to the sixth output port B5 of the 3-8 decoder; the gate of MP71 is connected to the seventh output terminal A6 of the first inverter INV1; the gate of the PMOS tube MP72 is connected to the seventh output port B6 of the 3-8 decoder; the gate of MP81 is connected to the eighth output terminal A7 of the first inverter INV1; the gate of MP82 is connected to the eighth output port B7 of the 3-8 decoder;

[0036] The drains of the PMOS tube MP11, the PMOS tube MP21, the PMOS tube MP31, the PMOS tube MP41, the PMOS tube MP51, the PMOS tube MP61, the PMOS tube MP71 and the PMOS tube MP81 are connected to each other and are all connected to the source of the PMOS tube MP83; the sources of the PMOS tube MP13, the PMOS tube MP23, the PMOS tube MP33, the PMOS tube MP43, the PMOS tube MP53, the PMOS tube MP63, the PMOS tube MP73, the PMOS tube MP83, the PMOS tube MP15, the PMOS tube MP25, the PMOS tube MP35, the PMOS tube MP45, the PMOS tube MP55, the PMOS tube MP65, the PMOS tube MP75 and the PMOS tube MP85 are connected to each other;

[0037] The drains of the PMOS tube MP12, the PMOS tube MP22, the PMOS tube MP32, the PMOS tube MP42, the PMOS tube MP52, the PMOS tube MP62, the PMOS tube MP72 and the PMOS tube MP82 are connected to each other and to the source of the PMOS tube MP84; the sources of the PMOS tube MP14, the PMOS tube MP24, the PMOS tube MP34, the PMOS tube MP44, the PMOS tube MP54, the PMOS tube MP64, the PMOS tube MP74, the PMOS tube MP84, the PMOS tube MP16, the PMOS tube MP26, the PMOS tube MP36, the PMOS tube MP46, the PMOS tube MP56, the PMOS tube MP66, the PMOS tube MP76 and the PMOS tube MP86 are connected to each other;

[0038] The gate of the PMOS tube MP83 is connected to the first output port C0 of the 4-16 decoder; the gate of the PMOS tube MP85 is connected to the second output port C1 of the 4-16 decoder; the gate of the PMOS tube MP73 is connected to the third output port C2 of the 4-16 decoder; the gate of the PMOS tube MP75 is connected to the fourth output port C3 of the 4-16 decoder; the gate of the PMOS tube MP63 is connected to the fifth output port C4 of the 4-16 decoder; the gate of the PMOS tube MP65 is connected to the sixth output port C5 of the 4-16 decoder; the gate of the PMOS tube MP53 is connected to the seventh output port C6 of the 4-16 decoder; the gate of the PMOS tube MP55 is connected to the eighth output port C7 ... The gate of P43 is connected to the ninth output port C8 of the 4-16 decoder; the gate of the PMOS tube MP45 is connected to the tenth output port C9 of the 4-16 decoder; the gate of the PMOS tube MP33 is connected to the eleventh output port C10 of the 4-16 decoder; the gate of the PMOS tube MP35 is connected to the twelfth output port C11 of the 4-16 decoder; the gate of the PMOS tube MP23 is connected to the thirteenth output port C12 of the 4-16 decoder; the gate of the PMOS tube MP25 is connected to the fourteenth output port C13 of the 4-16 decoder; the gate of the PMOS tube MP13 is connected to the fifteenth output port C14 of the 4-16 decoder; the gate of the PMOS tube MP15 is connected to the sixteenth output port C15 of the 4-16 decoder;

[0039] The gate of the PMOS tube MP84 is connected to the first output terminal D0 of the second inverter INV2; the gate of the PMOS tube MP86 is connected to the second output terminal D1 of the second inverter INV2; the gate of the PMOS tube MP74 is connected to the third output terminal D2 of the second inverter INV2; the gate of the PMOS tube MP76 is connected to the fourth output terminal D3 of the second inverter INV2; the gate of the PMOS tube MP64 is connected to the fifth output terminal D4 of the second inverter INV2; the gate of the PMOS tube MP66 is connected to the sixth output terminal D5 of the second inverter INV2; the gate of the PMOS tube MP54 is connected to the seventh output terminal D6 of the second inverter INV2; the gate of the PMOS tube MP56 is connected to the eighth output terminal D7 ... The gate of P44 is connected to the ninth output terminal D8 of the second inverter INV2; the gate of the PMOS tube MP46 is connected to the tenth output terminal D9 of the second inverter INV2; the gate of the PMOS tube MP34 is connected to the eleventh output terminal D10 of the second inverter INV2; the gate of the PMOS tube MP36 is connected to the twelfth output terminal D11 of the second inverter INV2; the gate of the PMOS tube MP24 is connected to the thirteenth output terminal D12 of the second inverter INV2; the gate of the PMOS tube MP26 is connected to the fourteenth output terminal D13 of the second inverter INV2; the gate of the PMOS tube MP14 is connected to the fifteenth output terminal D14 of the second inverter INV2; the gate of the PMOS tube MP16 is connected to the sixteenth output terminal D15 of the second inverter INV2.

[0040] The present invention provides a battery pack monitoring circuit with integrated switched capacitor temperature compensation, comprising: a battery pack, a low-voltage multiplexer, a high-voltage multiplexer, an incremental ADC and a digital filter; the battery pack is composed of a plurality of battery modules to be monitored connected in series; the low-voltage multiplexer is used to select a plurality of control channels according to the parameters to be measured of the battery pack to obtain the corresponding low-voltage control channel; the high-voltage multiplexer is used to sequentially select the voltages of the battery modules to be monitored in the battery pack to obtain a voltage selection signal; the incremental ADC is used to convert the voltage selection signal from an analog signal to a digital signal under the low-voltage control channel to obtain a digital code stream signal; wherein the incremental ADC is an incremental Σ-Δ ADC, adopts a multi-channel input structure, and a discrete switched capacitor bandgap reference circuit is provided in the incremental ADC; the discrete switched capacitor bandgap reference circuit and the incremental ADC adopt the same operational amplifier; a decoder for dynamically adjusting the on-off of an internal switch is provided in the discrete switched capacitor bandgap reference circuit; the digital filter is used to perform downsampling processing according to the digital code stream signal to obtain a monitoring result under the low-voltage channel signal corresponding to the battery module to be monitored. In the present invention, since the switched capacitor bandgap reference circuit in the incremental ADC is a discrete design structure, compared with the continuous switched capacitor bandgap reference circuit, the design power consumption is reduced; in addition, since the incremental ADC and the discrete switched capacitor bandgap reference circuit share the same operational amplifier, the design area is saved; finally, since the dynamic element matching technology is set in the discrete switched capacitor bandgap reference circuit, the influence of mismatch between transistors on the monitoring accuracy is greatly reduced, and the monitoring accuracy is improved.

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of the structure of a battery pack monitoring circuit with integrated switched capacitor temperature compensation provided by an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of the structure of an incremental ADC provided by an embodiment of the present invention;

[0044] Figure 3 A schematic diagram of the structure of a DAC feedback circuit provided by an embodiment of the present invention;

[0045] Figure 4 A schematic diagram of the structure of a VBE generating circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0047] In order to reduce design power consumption, save design area, and improve battery pack monitoring accuracy, an embodiment of the present invention provides a battery pack monitoring circuit with integrated switched capacitor temperature compensation. Figure 1 A schematic diagram of a battery pack monitoring circuit with integrated switch capacitor temperature compensation provided by an embodiment of the present invention. As shown in the figure, it includes: a battery pack, a low-voltage multiplexer, a high-voltage multiplexer, an incremental ADC and a digital filter; the battery pack is composed of a plurality of battery modules to be monitored that are connected in series;

[0048] The low voltage multiplexer is used to select multiple control channels according to the parameters to be measured of the battery pack to obtain corresponding low voltage control channels;

[0049] The high-voltage multiplexer is used to sequentially select the voltages of the battery modules to be monitored in the battery pack to obtain a voltage selection signal;

[0050] The incremental ADC is used to convert the voltage selection signal from an analog signal to a digital signal under a low-voltage control channel to obtain a digital code stream signal; wherein the incremental ADC is an incremental Σ-Δ ADC, adopts a multi-channel input structure, and a discrete switched capacitor bandgap reference circuit is provided in the incremental ADC; the discrete switched capacitor bandgap reference circuit and the incremental ADC use the same operational amplifier; the discrete switched capacitor bandgap reference circuit is provided with a decoder for dynamically adjusting the on-off of an internal switch;

[0051] The digital filter is used to perform downsampling processing according to the digital code stream signal to obtain the monitoring result under the low-voltage channel signal corresponding to the battery module to be monitored.

[0052] In the embodiment of the present invention, the dynamic component matching technology is specifically manifested as a process of switching the switch in the incremental ADC under the control of the 3-8 decoder and the 4-16 decoder.

[0053] The implementation process of battery pack monitoring based on the above module is as follows: a selection switch (i.e., a low-voltage multiplexer and a high-voltage multiplexer) is connected to the first stage of the incremental ADC, and different channels are switched as the input of the incremental ADC at regular intervals, and reset is performed before switching channels to clear the previous measurement results in order to obtain more accurate results. The analog voltage to be measured is converted into a digital code stream through the incremental ADC, and the input digital code stream is processed by the digital filter of the next stage, and finally can be sent to the processor for reading.

[0054] The embodiment of the present invention provides a battery pack monitoring circuit with integrated switched capacitor temperature compensation. The switched capacitor bandgap reference circuit in the incremental ADC is a discrete design structure, which reduces the design power consumption compared with the continuous switched capacitor bandgap reference circuit. In addition, the incremental ADC and the discrete switched capacitor bandgap reference circuit share the same operational amplifier, saving the design area. Finally, a dynamic element matching technology is set in the discrete switched capacitor bandgap reference circuit, which greatly reduces the influence of mismatch between transistors on the monitoring accuracy and improves the monitoring accuracy.

[0055] Optionally, the high-voltage multiplexer is provided with an input port matching the output terminal of the battery pack; the battery pack is connected to the input terminal of the high-voltage multiplexer;

[0056] The low voltage multiplexer is provided with differential input ports having the same number as the control channels;

[0057] The output ends of the high voltage multiplexer and the low voltage multiplexer are both connected to the input end of the incremental ADC; the output end of the incremental ADC is connected to the digital filter.

[0058] Figure 2 Schematic diagram of the structure of the incremental ADC provided by the embodiment of the present invention. Figure 2 As shown, the incremental ADC includes: a first-stage integrator, a second-stage integrator, a DAC circuit, a passive summing circuit, and a single-bit quantizer; the DAC circuit is a discrete switched capacitor bandgap reference circuit;

[0059] The first-stage integrator and the second-stage integrator have the same structure, and both include: a sampling and holding circuit and an operational amplifier;

[0060] The input end of the sampling and holding circuit in the first stage integrator is connected to the output ends of the high voltage multiplexer and the low voltage multiplexer; the output end of the sampling and holding circuit in the first stage integrator is connected to the input end of the operational amplifier in the first stage integrator; the output end of the operational amplifier in the first stage integrator is connected to the input end of the second stage integrator;

[0061] The output end of the second stage integrator is connected to the input end of the passive summing circuit; the output end of the operational amplifier in the second stage integrator is connected to the input end of the passive summing circuit;

[0062] The output end of the passive summing circuit is connected to the input end of the single-bit quantizer and the digital filter; the output end of the single-bit quantizer is connected to the input end of the DAC circuit;

[0063] The output end of the DAC circuit is connected to the output end of the sampling and holding circuit in the first stage integrator.

[0064] It should be noted that the low-voltage multiplexer uses differential input. Compared with the single-ended structure, the differential structure circuit can provide higher input and output swing. In addition, the differential structure can provide better linearity performance in the incremental ADC circuit, thereby optimizing the signal-to-noise ratio and other parameters of the circuit output, and suppressing even-order harmonics.

[0065] In addition, the input end of the incremental ADC has two multi-channel selection switches. Selection switch 1 (high-voltage multiplexer) is used to select the voltage across a single battery from the series-connected battery pack as the input of the incremental ADC to monitor whether the battery charging and discharging in the battery pack is unbalanced, overcharged or over-discharged. Selection switch 2 (high-voltage multiplexer) selects to measure other performance of the battery pack, such as temperature, battery pack top voltage and other analog quantities.

[0066] Optionally, the first-stage integrator is used to perform a first sampling integration process on the low-voltage channel signal and the voltage of the battery module to be monitored to obtain a first integrated output signal;

[0067] The second stage integrator is used to perform a second sampling integration process on the first integrated output signal to obtain a second integrated output signal;

[0068] The passive summing circuit is used to perform a summing operation on the first integral output signal and the second integral output signal to obtain a signal summing result;

[0069] The single-bit quantizer is used to compare the two outputs inside the signal summation result, and obtain the digital code stream signal according to the comparison result;

[0070] The DAC circuit is used to feed back different DAC output signals according to different digital code stream signals to the output end of the sampling and holding circuit in the first-stage integrator to adjust the first integrated output signal to avoid oversaturation of the first integrated output signal.

[0071] It should be noted that, in the embodiment of the present invention, by simultaneously providing the first-stage integrator and the second-stage integrator, accurate battery monitoring can be achieved while maintaining low power consumption and stability.

[0072] In addition, the single-bit quantizer compares the two outputs of the signal summation result and obtains a digital code stream signal according to the comparison result. Figure 2 When VIP is positive and VIN is negative, the comparison output result is 1, and when VIP is negative and VIN is positive, the comparison output result is 0. The digital code stream signal is a series of digital signals composed of "0" and "1".

[0073] Optionally, the DAC circuit includes: a DAC feedback circuit and a VBE generating circuit.

[0074] Figure 3 Schematic diagram of the structure of the DAC feedback circuit provided by the embodiment of the present invention. Figure 3 As shown, the DAC feedback circuit includes: switches S13-S36, adjustable capacitors Cf1, Cf2, capacitors Cf3 and Cf4;

[0075] The first ends of switch S28, switch S26, switch S24, and switch S22 are connected to each other and to the first output terminal VBE1 of the VBE generating circuit; the first ends of switch S21, switch S23, switch S25, and switch S27 are connected to each other and to the second output terminal VBE2 of the VBE generating circuit; the second ends of switch S21 and switch S22 are connected to each other and to the first end of switch S13; the second ends of switch S23 and switch S24 are connected to each other and to the first end of switch S14; the second ends of switch S25 and switch S26 are connected to each other and to the first end of switch S15; the second ends of switch S27 and switch S28 are connected to each other and to the first end of switch S16; the second ends of switch S13 and switch S14 are connected to each other and to the first end of the adjustable capacitor Cf1; the second ends of switch S15 and switch S16 are connected to each other and to the first end of the adjustable capacitor Cf2;

[0076] The first ends of the switch S35, the switch S33, the switch S31, and the switch S29 are connected to each other and to the first output terminal VBE1 of the VBE generating circuit; the first ends of the switch S36, the switch S34, the switch S32, and the switch S30 are connected to each other and to the ground VSS; the second ends of the switch S29 and the switch S30 are connected to each other and to the first end of the switch S17; the second ends of the switch S31 and the switch S32 are connected to each other and to the first end of the switch S18; the second ends of the switch S33 and the switch S34 are connected to each other and to the first end of the switch S19; the second ends of the switch S35 and the switch S36 are connected to each other and to the first end of the switch S20; the second ends of the switch S17 and the switch S18 are connected to each other and to the first end of the capacitor Cf3; the second ends of the switch S19 and the switch S20 are connected to each other and to the first end of the capacitor Cf4;

[0077] The second end of capacitor Cf3 is connected to the second end of adjustable capacitor Cf1 and connected to the inverting input terminal Vin1p of the operational amplifier. The second end of capacitor Cf4 is connected to the first end of adjustable capacitor Cf2 and connected to the positive input terminal Vin1n of the operational amplifier.

[0078] The timing of switches S14, S15, S17, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31, S32, S33, S34, S35 and S36 depends on the digital code stream output by the incremental ADC. When the digital code stream is 1, S22, S23, S26, S27, S30, S31, S34 and S35 are turned on, and S21, S24, S25, S28, S29, S32, S33 and S36 are turned off. When the incremental ADC output is 0, S21, S24, S25, S28, S29, S32, S33 and S36 are turned on, and S22, S23, S26, S27, S30, S31, S34 and S35 are turned off. Wherein Cf1 and Cf2 are capacitors with adjustable capacitance, switches S14, S15, S17 and S20 are sampling switches, which are closed when in the sampling state and disconnected when in the integration state. Switches S18, S19, S13 and S16 are integration switches, which are closed when in the integration state and disconnected when in the sampling state.

[0079] The specific adjustment process is:

[0080] If the incremental ADC output is 1, in the sampling state, the voltage VBE1 is sampled on Cf1 (the voltage VBE2 is sampled on Cf2), and the charge Q1 on the adjustable capacitor Cf1 in the sampling state is (VBE1-VCM)·Cf1, (the charge Q1' on the adjustable capacitor Cf2 in the sampling state is (VBE2-VCM)·Cf2). On the other side, the voltage VBE1 is sampled on Cf3 (the voltage VSS is sampled on Cf4), and the charge Q2 on the capacitor Cf3 in the sampling state is (VBE1-VCM)·Cf3 (the charge Q2' on the capacitor Cf4 in the sampling state is (VSS-VCM)·Cf4).

[0081] In the integration state, the charge on Cf will be transferred. Specifically, for Cf1, the left plate changes from VBE1 to VBE2 (for Cf2, the left plate changes from VBE2 to VBE1). At this time, the charge Q3 on the adjustable capacitor Cf1 in the integration state = (VBE1-VBE2-VCM)·Cf1 is transferred from Cf1 (the charge Q3' on the adjustable capacitor Cf2 in the integration state = (VBE2-VBE1)·Cf2 is transferred from Cf2). On the other side, for Cf4, the right plate changes from VSS to VBE1 (for Cf3, the right plate changes from VBE1 to VSS). At this time, the charge Q4 on the adjustable capacitor Cf3 in the integration state = (VSS-VBE1)·Cf4 is transferred from Cf4 (the charge Q4' on the adjustable capacitor Cf4 in the integration state = (VBE1-VSS)·Cf3 is transferred from Cf3).

[0082] Therefore, the charge transferred in the DAC feedback circuit at one end of the fully differential signal is:

[0083] (VBE1-VBE2)·Cf1+(VBE1-VSS)·Cf3.

[0084] The charge transferred in the DAC feedback circuit at the other end of the fully differential signal is:

[0085] (VBE2-VBE1)·Cf2+(VSS-VBE1)·Cf4.

[0086] Similarly, when the output code stream of the ADC is 0, the charge transferred in the DAC feedback circuit at one end of the fully differential signal is: (VBE2-VBE1)·Cf1+(VSS-VBE1)·Cf3.

[0087] The charge transferred in the DAC feedback circuit at the other end of the fully differential signal is:

[0088] (VBE1-VBE2)·Cf2+(VBE1-VSS)·Cf4.

[0089] Therefore, the values ​​of the variable capacitors Cf1 and Cf2 can be adjusted so that the total amount of charge transferred is independent of temperature.

[0090] Figure 4 A schematic diagram of the structure of a VBE generating circuit provided in an embodiment of the present invention is shown in FIG. Figure 4 As shown, the VBE generating circuit includes: transistors Q1-Q16, PMOS tubes MP0-MP8, PMOS tubes MP11-MP12, PMOS tubes MP21-MP22, PMOS tubes MP31-MP32, PMOS tubes MP41-MP42, PMOS tubes MP51-MP52, PMOS tubes MP61-MP62, PMOS tubes MP71-MP72, PMOS tubes MP81-MP82, PMOS tubes MP13-MP16, PMOS tubes MP23-MP26, PMOS tubes MP33-MP36, PMOS tubes MP43-MP46, and PMOS tubes MP53-MP53 -MP56, PMOS tubes MP63-MP66, PMOS tubes MP73-MP76, PMOS tubes MP83-MP86, switches S11-S12, switches S21-S22, switches S31-S32, switches S41-S42, switches S51-S52, switches S61-S62, switches S71-S72, switches S81-S82, switches S91-S92, switches S101-S102, switches S111-S112, switches S121-S122, switches S131-S132, switches S141-S142, switches S151-S152 and switches S161-S162;

[0091] The areas of transistors Q1-Q16 are equal, and the collectors of transistors Q1-Q16 are connected to their own bases; the collector of transistor Q1 is connected to the drains of PMOS tubes MP15 and MP16; the collector of transistor Q2 is connected to the drains of PMOS tubes MP13 and MP14; the collector of transistor Q3 is connected to the drains of PMOS tubes MP25 and MP26; the collector of transistor Q4 is connected to the drains of PMOS tubes MP23 and MP24; the collector of transistor Q5 is connected to the drains of PMOS tubes MP35 and MP36; the collector of transistor Q6 is connected to the drains of PMOS tubes MP35 and MP36; the collector of transistor Q7 is connected to the drains of PMOS tubes MP37 and MP38; the collector of transistor Q8 is connected to the drains of PMOS tubes MP39 and MP40; the collector of transistor Q9 is connected to the drains of PMOS tubes MP41 and MP42; the collector of transistor Q10 is connected to the drains of PMOS tubes MP43 and MP44; the collector of transistor Q11 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q12 is connected to the drains of PMOS tubes MP47 and MP42; the collector of transistor Q13 is connected to the drains of PMOS tubes MP43 and MP44; the collector of transistor Q14 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q15 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q16 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q17 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q18 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q19 is connected to the drains of PMOS tube The collector of transistor Q7 is connected to the drain of PMOS tube MP45 and PMOS tube MP46; the collector of transistor Q8 is connected to the drain of PMOS tube MP43 and PMOS tube MP44; the collector of transistor Q9 is connected to the drain of PMOS tube MP55 and PMOS tube MP56; the collector of transistor Q10 is connected to the drain of PMOS tube MP53 and PMOS tube MP54; the collector of transistor Q11 is connected to the drain of PMOS tube MP65 and PMOS tube MP66; the collector of transistor Q12 is connected to the PM The drains of the OS transistor MP63 and the PMOS transistor MP64; the collector of the transistor Q13 is connected to the drains of the PMOS transistor MP75 and the PMOS transistor MP76; the collector of the transistor Q14 is connected to the drains of the PMOS transistor MP73 and the PMOS transistor MP74; the collector of the transistor Q15 is connected to the drains of the PMOS transistor MP85 and the PMOS transistor MP86, and the collector of the transistor Q16 is connected to the drains of the PMOS transistor MP83 and the PMOS transistor MP84; the first end of the switch S11 is connected to the emitter of the transistor Q1, and the first output end VBE1 of the VBE generating circuit is connected to the switches S11, S21, and S 31. the second ends of the switches S41, S51, S61, S71, S81, S91, S101, S111, S121, S131, S141, S151 and S161; the second output end VBE2 of the VBE generating circuit is connected to the second ends of the switches S12, S22, S32, S42, S52, S62, S72, S82, S92, S102, S112, S122, S132, S142, S152 and S162;

[0092] The first ends of switch S12, switch S22, switch S32, switch S42, switch S52, switch S62, switch S72, switch S82, switch S92, switch S102, switch S112, switch S122, switch S132, switch S142, switch S152, and switch S162 are connected to the emitters of transistors Q1-Q16 in sequence; the first ends of switch S11, switch S31, switch S41, switch S51, and switch S 61. The first ends of switches S71, S81, S91, S101, S111, S121, S131, S141, S151 and S161 are connected to the emitters of transistors Q1-Q16 in sequence; the gates of PMOS tubes MP0-MP8 are connected to each other; the sources of PMOS tubes MP0-MP8 are connected to the power supply voltage VDD; the drain and gate of PMOS tube MP0 are connected to each other;

[0093] The drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP11 and the PMOS tube MP12; the drain of the PMOS tube MP2 is connected to the source of the PMOS tube MP21 and the PMOS tube MP22; the drain of the PMOS tube MP3 is connected to the source of the PMOS tube MP31 and the PMOS tube MP32; the drain of the PMOS tube MP4 is connected to the source of the PMOS tube MP41 and the PMOS tube MP42; the drain of the PMOS tube MP5 is connected to the source of the PMOS tube MP51 and the PMOS tube MP52; the drain of the PMOS tube MP6 is connected to the source of the PMOS tube MP61 and the PMOS tube MP62; the drain of the PMOS tube MP7 is connected to the source of the PMOS tube MP71 and the PMOS tube MP72; the drain of the PMOS tube MP8 is connected to the source of the PMOS tube MP81 and the PMOS tube MP82;

[0094] The gate of the PMOS tube MP11 is connected to the first output terminal A0 of the first inverter INV1; the gate of the PMOS tube MP12 is connected to the first output port B0 of the 3-8 decoder; the gate of the PMOS tube MP21 is connected to the second output terminal A1 of the first inverter INV1; the gate of the PMOS tube MP22 is connected to the second output port B1 of the 3-8 decoder; the gate of the PMOS tube MP31 is connected to the third output terminal A2 of the first inverter INV1; the gate of MP32 is connected to the third output port B2 of the 3-8 decoder; the gate of MP41 is connected to the fourth output terminal A3 of the first inverter INV1; the gate of MP42 is connected to the 3-8 decoder The gate of MP51 is connected to the fifth output terminal A4 of the first inverter INV1; the gate of MP52 is connected to the fifth output port B4 of the 3-8 decoder; the gate of MP61 is connected to the sixth output terminal A5 of the first inverter INV1; the gate of MP62 is connected to the sixth output port B5 of the 3-8 decoder; the gate of MP71 is connected to the seventh output terminal A6 of the first inverter INV1; the gate of the PMOS tube MP72 is connected to the seventh output port B6 of the 3-8 decoder; the gate of MP81 is connected to the eighth output terminal A7 of the first inverter INV1; the gate of MP82 is connected to the eighth output port B7 of the 3-8 decoder;

[0095] The drains of the PMOS tube MP11, the PMOS tube MP21, the PMOS tube MP31, the PMOS tube MP41, the PMOS tube MP51, the PMOS tube MP61, the PMOS tube MP71 and the PMOS tube MP81 are connected to each other and are all connected to the source of the PMOS tube MP83; the sources of the PMOS tube MP13, the PMOS tube MP23, the PMOS tube MP33, the PMOS tube MP43, the PMOS tube MP53, the PMOS tube MP63, the PMOS tube MP73, the PMOS tube MP83, the PMOS tube MP15, the PMOS tube MP25, the PMOS tube MP35, the PMOS tube MP45, the PMOS tube MP55, the PMOS tube MP65, the PMOS tube MP75 and the PMOS tube MP85 are connected to each other;

[0096] The drains of the PMOS tube MP12, the PMOS tube MP22, the PMOS tube MP32, the PMOS tube MP42, the PMOS tube MP52, the PMOS tube MP62, the PMOS tube MP72 and the PMOS tube MP82 are connected to each other and to the source of the PMOS tube MP84; the sources of the PMOS tube MP14, the PMOS tube MP24, the PMOS tube MP34, the PMOS tube MP44, the PMOS tube MP54, the PMOS tube MP64, the PMOS tube MP74, the PMOS tube MP84, the PMOS tube MP16, the PMOS tube MP26, the PMOS tube MP36, the PMOS tube MP46, the PMOS tube MP56, the PMOS tube MP66, the PMOS tube MP76 and the PMOS tube MP86 are connected to each other;

[0097] The gate of the PMOS tube MP83 is connected to the first output port C0 of the 4-16 decoder; the gate of the PMOS tube MP85 is connected to the second output port C1 of the 4-16 decoder; the gate of the PMOS tube MP73 is connected to the third output port C2 of the 4-16 decoder; the gate of the PMOS tube MP75 is connected to the fourth output port C3 of the 4-16 decoder; the gate of the PMOS tube MP63 is connected to the fifth output port C4 of the 4-16 decoder; the gate of the PMOS tube MP65 is connected to the sixth output port C5 of the 4-16 decoder; the gate of the PMOS tube MP53 is connected to the seventh output port C6 of the 4-16 decoder; the gate of the PMOS tube MP55 is connected to the eighth output port C7 ... The gate of P43 is connected to the ninth output port C8 of the 4-16 decoder; the gate of the PMOS tube MP45 is connected to the tenth output port C9 of the 4-16 decoder; the gate of the PMOS tube MP33 is connected to the eleventh output port C10 of the 4-16 decoder; the gate of the PMOS tube MP35 is connected to the twelfth output port C11 of the 4-16 decoder; the gate of the PMOS tube MP23 is connected to the thirteenth output port C12 of the 4-16 decoder; the gate of the PMOS tube MP25 is connected to the fourteenth output port C13 of the 4-16 decoder; the gate of the PMOS tube MP13 is connected to the fifteenth output port C14 of the 4-16 decoder; the gate of the PMOS tube MP15 is connected to the sixteenth output port C15 of the 4-16 decoder;

[0098] The gate of the PMOS tube MP84 is connected to the first output terminal D0 of the second inverter INV2; the gate of the PMOS tube MP86 is connected to the second output terminal D1 of the second inverter INV2; the gate of the PMOS tube MP74 is connected to the third output terminal D2 of the second inverter INV2; the gate of the PMOS tube MP76 is connected to the fourth output terminal D3 of the second inverter INV2; the gate of the PMOS tube MP64 is connected to the fifth output terminal D4 of the second inverter INV2; the gate of the PMOS tube MP66 is connected to the sixth output terminal D5 of the second inverter INV2; the gate of the PMOS tube MP54 is connected to the seventh output terminal D6 of the second inverter INV2; the gate of the PMOS tube MP56 is connected to the eighth output terminal D7 ... The gate of P44 is connected to the ninth output terminal D8 of the second inverter INV2; the gate of the PMOS tube MP46 is connected to the tenth output terminal D9 of the second inverter INV2; the gate of the PMOS tube MP34 is connected to the eleventh output terminal D10 of the second inverter INV2; the gate of the PMOS tube MP36 is connected to the twelfth output terminal D11 of the second inverter INV2; the gate of the PMOS tube MP24 is connected to the thirteenth output terminal D12 of the second inverter INV2; the gate of the PMOS tube MP26 is connected to the fourteenth output terminal D13 of the second inverter INV2; the gate of the PMOS tube MP14 is connected to the fifteenth output terminal D14 of the second inverter INV2; the gate of the PMOS tube MP16 is connected to the sixteenth output terminal D15 of the second inverter INV2.

[0099] It should be noted that the input end of the 3-8 decoder is connected to the first clock signal interface Clk1, the second clock signal interface Clk2 and the third clock signal interface Clk3, and the input end of the 4-16 decoder is correspondingly connected to the fourth clock signal interface Clk4, the fifth clock signal interface Clk5, the sixth clock signal interface Clk6 and the seventh clock signal interface Clk7.

[0100] Clk2, Clk3, Clk4, Clk5, Clk6 and Clk7 are respectively 2 times, 4 times, 8 times, 16 times, 32 times and 64 times the frequency of clock Clk1.

[0101] The output signal of the single-bit quantizer is used to control the on and off of switches S21-S36 in the DAC circuit. The first clock signal interface Clk1 is a sampling clock.

[0102] The corresponding relationship between control signals and components is as follows: Figure 4Corresponding to interfaces A<7:0>, B<7:0>, C<15:0> and D<15:0>, for the sake of convenience, they are also represented as A0-A7, B0-B7, C0-C15 and D0-D15. Specifically, A0, A1, A2, A3, A4, A5, A6 and A7 control the gates of transistors MP11, MP21, MP31, MP41, MP51, MP61, MP71 and MP81 respectively, and the transistors are turned on when the control signal is low. B0, B1, B2, B3, B4, B5, B6 and B7 control the gates of transistors MP12, MP22, MP32, MP42, MP52, MP62, MP72 and MP82 respectively, and the transistors are turned on when the control signal is low. C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14 and C15 respectively control the gates of transistors MP83, MP85, MP73, MP75, MP63, MP65, MP53, MP55, MP43, MP45, MP33, MP35, MP23, MP25, MP13 and MP15, and the transistors are turned on when the control signal is low. D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14 and D15 control the gates of transistors MP84, MP86, MP74, MP76, MP64, MP66, MP54, MP56, MP44, MP46, MP34, MP36, MP24, MP26, MP14 and MP16, and the transistors are turned on when the control signal is low. The C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14 and C15 signals simultaneously control switches S11, S21, S31, S41, S51, S61, S71, S81, S91, S101, S111, S121, S131, S141, S151 and S161. At this time, the switches are turned on when the control signals are high. The D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14 and D15 signals simultaneously control switches S12, S22, S32, S42, S52, S62, S72, S82, S92, S102, S112, S122, S132, S142, S152 and S162. At this time, the switches are turned on when the control signals are high. Figure 4 The current mirror uses dynamic element matching technology, which makes 7 PMOS tubes controlled by B and C turn on at the same time, and only one PMOS tube controlled by A and D turns on at the same time, which greatly reduces the error caused by mismatch and offset. The switch array is turned on at a high level and turned off at a low level.

[0103] The specific switch on-off relationship is as follows: Take one cycle as an example to illustrate the situation, when the PMOS tube MP81 is turned on, the PMOS tubes MP71, MP61, MP51, MP41, MP31, MP21 and MP11 are turned off, and at this time, the PMOS tubes MP72, MP62, MP52, MP42, MP32, MP22 and MP12 are turned on, and the PMOS tube MP82 is turned off. The PMOS tube MP83 is turned off, and the PMOS tubes MP85, MP73, MP75, MP63, MP65, MP53, MP55, MP43, MP45, MP33, MP35, MP23, MP25, MP13 and MP15 are turned on. The PMOS tube MP84 is turned on, and the PMOS tubes MP86, MP74, MP76, MP64, MP66, MP54, MP56, MP44, MP46, MP34, MP36, MP24, MP26, MP14 and MP16 are turned off. The switch S11 is closed, and the switches S21, S31, S41, S51, S61, S71, S81, S91, S101, S111, S121, S131, S141, S151 and S161 are turned off. The switch S12 is turned off, and the switches S22, S32, S42, S52, S62, S72, S82, S92, S102, S112, S122, S132, S142, S152 and S162 are closed, and so on. In summary, the PMOS tubes MP84, MP86, MP74, MP76, MP64, MP66, MP54, MP56, MP44, MP46, MP34, MP36, MP24, MP26, MP14 and MP16 are turned on one by one in sequence according to the cycle of Clk7. The PMOS tubes MP83, MP85, MP73, MP75, MP63, MP65, MP53, MP55, MP43, MP45, MP33, MP35, MP23, MP25, MP13 and MP15 corresponding to the above-mentioned turn-on tubes are turned off one by one in sequence according to the cycle of Clk7. And the PMOS tubes MP11, MP21, MP31, MP41, MP51, MP61, MP71 and MP81 are turned on one by one in accordance with the cycle of Clk3. The PMOS transistors MP12, MP22, MP32, MP42, MP52, MP62, MP72 and MP82 corresponding to the above-mentioned conduction transistor are turned off one by one in sequence according to the cycle of Clk3. The switches S11, S21, S31, S41, S51, S61, S71, S81, S91, S101, S111, S121, S131, S141, S151 and S161 are closed one by one in sequence according to the cycle of Clk7.The switches S12, S22, S32, S42, S52, S62, S72, S82, S92, S102, S112, S122, S132, S142, S152 and S162 corresponding to the above-mentioned closed switches are opened one by one according to the cycle of Clk7.

[0104] At this time, assume that the current flowing through transistors MP1-MP8 is I0, and the saturation current of transistors Q1-Q16 is I S , the thermal voltage is V T , then:

[0105] VBE1 = V T ln(7I0 / I S );

[0106] VBE2 = V T ln(I0 / 15I S );

[0107] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0108] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0109] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other changes of the above disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0110] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A battery pack monitoring circuit with integrated switched capacitor temperature compensation, characterized in that: include: A battery pack, a low voltage multiplexer, a high voltage multiplexer, an incremental ADC and a digital filter; the battery pack is composed of a plurality of battery modules to be monitored which are connected in series; The low voltage multiplexer is used to select a plurality of control channels according to the parameters to be measured of the battery pack to obtain corresponding low voltage control channels; The high-voltage multiplexer is used to sequentially select the voltages of the battery modules to be monitored in the battery pack to obtain a voltage selection signal; The incremental ADC is used to convert the voltage selection signal from an analog signal to a digital signal under the low-voltage control channel to obtain a digital code stream signal; wherein the incremental ADC is an incremental Σ-Δ ADC, adopts a multi-channel input structure, and a discrete switched capacitor bandgap reference circuit is provided in the incremental ADC; the discrete switched capacitor bandgap reference circuit and the incremental ADC adopt the same operational amplifier; the discrete switched capacitor bandgap reference circuit is provided with a decoder for dynamically adjusting the on-off of an internal switch; The digital filter is used to perform downsampling processing according to the digital code stream signal to obtain a monitoring result under the low-voltage channel signal corresponding to the battery module to be monitored.

2. The battery pack monitoring circuit with integrated switched capacitor temperature compensation according to claim 1, characterized in that: The high-voltage multiplexer is provided with an input port matching the output end of the battery pack; the battery pack is connected to the input end of the high-voltage multiplexer; The low voltage multiplexer is provided with differential input ports equal in number to the control channels; The output ends of the high-voltage multiplexer and the low-voltage multiplexer are both connected to the input end of the incremental ADC; and the output end of the incremental ADC is connected to the digital filter.

3. The battery pack monitoring circuit with integrated switched capacitor temperature compensation according to claim 1, characterized in that: The incremental ADC comprises: a first-stage integrator, a second-stage integrator, a DAC circuit, a passive summing circuit and a single-bit quantizer; the DAC circuit is the discrete switched capacitor bandgap reference circuit; The first-stage integrator and the second-stage integrator have the same structure, and both include: a sampling and holding circuit and an operational amplifier; The input end of the sampling and holding circuit in the first-stage integrator is connected to the output ends of the high-voltage multiplexer and the low-voltage multiplexer; the output end of the sampling and holding circuit in the first-stage integrator is connected to the input end of the operational amplifier in the first-stage integrator; the output end of the operational amplifier in the first-stage integrator is connected to the input end of the second-stage integrator; The output end of the second-stage integrator is connected to the input end of the passive summing circuit; the output end of the operational amplifier in the second-stage integrator is connected to the input end of the passive summing circuit; The output end of the passive summing circuit is connected to the input end of the single-bit quantizer and the digital filter; the output end of the single-bit quantizer is connected to the input end of the DAC circuit; The output end of the DAC circuit is connected to the output end of the sample-and-hold circuit in the first-stage integrator.

4. The battery pack monitoring circuit with integrated switched capacitor temperature compensation according to claim 3, characterized in that: The first-stage integrator is used to perform a first sampling integration process on the low-voltage channel signal and the voltage of the battery module to be monitored to obtain a first integrated output signal; The second stage integrator is used to perform a second sampling integration process on the first integrated output signal to obtain a second integrated output signal; The passive summing circuit is used to perform a summing operation on the first integrated output signal and the second integrated output signal to obtain a signal summing result; The single-bit quantizer is used to compare the two outputs inside the signal summation result, and obtain the digital code stream signal according to the comparison result; The DAC circuit is used to feed back different DAC output signals according to different digital code stream signals to the output end of the sampling and holding circuit in the first-stage integrator to adjust the first integrated output signal to avoid oversaturation of the first integrated output signal.

5. The battery pack monitoring circuit with integrated switched capacitor temperature compensation according to claim 3, characterized in that: The DAC circuit includes: a DAC feedback circuit and a VBE generating circuit.

6. The battery pack monitoring circuit with integrated switched capacitor temperature compensation according to claim 5, characterized in that: The DAC feedback circuit includes: switches S13 to S36, an adjustable capacitor Cf1, an adjustable capacitor Cf2, a capacitor Cf3, and a capacitor Cf4; The first ends of switch S28, switch S26, switch S24, and switch S22 are connected to each other and to the first output terminal VBE1 of the VBE generating circuit; the first ends of switch S21, switch S23, switch S25, and switch S27 are connected to each other and to the second output terminal VBE2 of the VBE generating circuit; the second ends of switch S21 and switch S22 are connected to each other and to the first end of switch S13; the second ends of switch S23 and switch S24 are connected to each other and to the first end of switch S14; the second ends of switch S25 and switch S26 are connected to each other and to the first end of switch S15; the second ends of switch S27 and switch S28 are connected to each other and to the first end of switch S16; the second ends of switch S13 and switch S14 are connected to each other and to the first end of the adjustable capacitor Cf1; the second ends of switch S15 and switch S16 are connected to each other and to the first end of the adjustable capacitor Cf2; The first ends of the switch S35, the switch S33, the switch S31, and the switch S29 are connected to each other and to the first output terminal VBE1 of the VBE generating circuit; the first ends of the switch S36, the switch S34, the switch S32, and the switch S30 are connected to each other and to the ground VSS; the second ends of the switch S29 and the switch S30 are connected to each other and to the first end of the switch S17; the second ends of the switch S31 and the switch S32 are connected to each other and to the first end of the switch S18; the second ends of the switch S33 and the switch S34 are connected to each other and to the first end of the switch S19; the second ends of the switch S35 and the switch S36 are connected to each other and to the first end of the switch S20; the second ends of the switch S17 and the switch S18 are connected to each other and to the first end of the capacitor Cf3; the second ends of the switch S19 and the switch S20 are connected to each other and to the first end of the capacitor Cf4; The second end of capacitor Cf3 is connected to the second end of adjustable capacitor Cf1 and connected to the inverting input terminal Vin1p of the operational amplifier. The second end of capacitor Cf4 is connected to the first end of adjustable capacitor Cf2 and connected to the positive input terminal Vin1n of the operational amplifier.

7. The battery pack monitoring circuit with integrated switched capacitor temperature compensation according to claim 5, characterized in that: The VBE generating circuit includes: triodes Q1-Q16, PMOS tubes MP0-MP8, PMOS tubes MP11-MP12, PMOS tubes MP21-MP22, PMOS tubes MP31-MP32, PMOS tubes MP41-MP42, PMOS tubes MP51-MP52, PMOS tubes MP61-MP62, PMOS tubes MP71-MP72, PMOS tubes MP81-MP82, PMOS tubes MP13-MP16, PMOS tubes MP23-MP26, PMOS tubes MP33-MP36, PMOS tubes MP43-MP46, PMOS tubes MP53-MP53 MP56, PMOS tubes MP63-MP66, PMOS tubes MP73-MP76, PMOS tubes MP83-MP86, switches S11-S12, switches S21-S22, switches S31-S32, switches S41-S42, switches S51-S52, switches S61-S62, switches S71-S72, switches S81-S82, switches S91-S92, switches S101-S102, switches S111-S112, switches S121-S122, switches S131-S132, switches S141-S142, switches S151-S152, and switches S161-S162; The areas of transistors Q1-Q16 are equal, and the collectors of transistors Q1-Q16 are connected to their own bases; the collector of transistor Q1 is connected to the drains of PMOS tubes MP15 and MP16; the collector of transistor Q2 is connected to the drains of PMOS tubes MP13 and MP14; the collector of transistor Q3 is connected to the drains of PMOS tubes MP25 and MP26; the collector of transistor Q4 is connected to the drains of PMOS tubes MP23 and MP24; the collector of transistor Q5 is connected to the drains of PMOS tubes MP35 and MP36; the collector of transistor Q6 is connected to the drains of PMOS tubes MP35 and MP36; the collector of transistor Q7 is connected to the drains of PMOS tubes MP37 and MP38; the collector of transistor Q8 is connected to the drains of PMOS tubes MP39 and MP40; the collector of transistor Q9 is connected to the drains of PMOS tubes MP41 and MP42; the collector of transistor Q10 is connected to the drains of PMOS tubes MP43 and MP44; the collector of transistor Q11 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q12 is connected to the drains of PMOS tubes MP47 and MP42; the collector of transistor Q13 is connected to the drains of PMOS tubes MP43 and MP44; the collector of transistor Q14 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q15 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q16 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q17 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q18 is connected to the drains of PMOS tubes MP45 and MP46; the collector of transistor Q19 is connected to the drains of PMOS tube The collector of transistor Q7 is connected to the drain of PMOS tube MP45 and PMOS tube MP46; the collector of transistor Q8 is connected to the drain of PMOS tube MP43 and PMOS tube MP44; the collector of transistor Q9 is connected to the drain of PMOS tube MP55 and PMOS tube MP56; the collector of transistor Q10 is connected to the drain of PMOS tube MP53 and PMOS tube MP54; the collector of transistor Q11 is connected to the drain of PMOS tube MP65 and PMOS tube MP66; the collector of transistor Q12 is connected to the PM The drains of the OS transistor MP63 and the PMOS transistor MP64; the collector of the transistor Q13 is connected to the drains of the PMOS transistor MP75 and the PMOS transistor MP76; the collector of the transistor Q14 is connected to the drains of the PMOS transistor MP73 and the PMOS transistor MP74; the collector of the transistor Q15 is connected to the drains of the PMOS transistor MP85 and the PMOS transistor MP86, and the collector of the transistor Q16 is connected to the drains of the PMOS transistor MP83 and the PMOS transistor MP84; the first end of the switch S11 is connected to the emitter of the transistor Q1, and the first output end VBE1 of the VBE generating circuit is connected to the switches S11, S21, and S 31. the second ends of the switches S41, S51, S61, S71, S81, S91, S101, S111, S121, S131, S141, S151 and S161; the second output end VBE2 of the VBE generating circuit is connected to the second ends of the switches S12, S22, S32, S42, S52, S62, S72, S82, S92, S102, S112, S122, S132, S142, S152 and S162; The first ends of switch S12, switch S22, switch S32, switch S42, switch S52, switch S62, switch S72, switch S82, switch S92, switch S102, switch S112, switch S122, switch S132, switch S142, switch S152, and switch S162 are connected to the emitters of transistors Q1-Q16 in sequence; the first ends of switch S11, switch S31, switch S41, switch S51, and switch S 61. The first ends of switches S71, S81, S91, S101, S111, S121, S131, S141, S151 and S161 are connected to the emitters of transistors Q1-Q16 in sequence; the gates of PMOS tubes MP0-MP8 are connected to each other; the sources of PMOS tubes MP0-MP8 are connected to the power supply voltage VDD; the drain and gate of PMOS tube MP0 are connected to each other; The drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP11 and the PMOS tube MP12; the drain of the PMOS tube MP2 is connected to the source of the PMOS tube MP21 and the PMOS tube MP22; the drain of the PMOS tube MP3 is connected to the source of the PMOS tube MP31 and the PMOS tube MP32; the drain of the PMOS tube MP4 is connected to the source of the PMOS tube MP41 and the PMOS tube MP42; the drain of the PMOS tube MP5 is connected to the source of the PMOS tube MP51 and the PMOS tube MP52; the drain of the PMOS tube MP6 is connected to the source of the PMOS tube MP61 and the PMOS tube MP62; the drain of the PMOS tube MP7 is connected to the source of the PMOS tube MP71 and the PMOS tube MP72; the drain of the PMOS tube MP8 is connected to the source of the PMOS tube MP81 and the PMOS tube MP82; The gate of the PMOS tube MP11 is connected to the first output terminal A0 of the first inverter INV1; the gate of the PMOS tube MP12 is connected to the first output port B0 of the 3-8 decoder; the gate of the PMOS tube MP21 is connected to the second output terminal A1 of the first inverter INV1; the gate of the PMOS tube MP22 is connected to the second output port B1 of the 3-8 decoder; the gate of the PMOS tube MP31 is connected to the third output terminal A2 of the first inverter INV1; the gate of MP32 is connected to the third output port B2 of the 3-8 decoder; the gate of MP41 is connected to the fourth output terminal A3 of the first inverter INV1; the gate of MP42 is connected to the 3-8 decoder The gate of MP51 is connected to the fifth output terminal A4 of the first inverter INV1; the gate of MP52 is connected to the fifth output port B4 of the 3-8 decoder; the gate of MP61 is connected to the sixth output terminal A5 of the first inverter INV1; the gate of MP62 is connected to the sixth output port B5 of the 3-8 decoder; the gate of MP71 is connected to the seventh output terminal A6 of the first inverter INV1; the gate of the PMOS tube MP72 is connected to the seventh output port B6 of the 3-8 decoder; the gate of MP81 is connected to the eighth output terminal A7 of the first inverter INV1; the gate of MP82 is connected to the eighth output port B7 of the 3-8 decoder; The drains of the PMOS tube MP11, the PMOS tube MP21, the PMOS tube MP31, the PMOS tube MP41, the PMOS tube MP51, the PMOS tube MP61, the PMOS tube MP71 and the PMOS tube MP81 are connected to each other and are all connected to the source of the PMOS tube MP83; the sources of the PMOS tube MP13, the PMOS tube MP23, the PMOS tube MP33, the PMOS tube MP43, the PMOS tube MP53, the PMOS tube MP63, the PMOS tube MP73, the PMOS tube MP83, the PMOS tube MP15, the PMOS tube MP25, the PMOS tube MP35, the PMOS tube MP45, the PMOS tube MP55, the PMOS tube MP65, the PMOS tube MP75 and the PMOS tube MP85 are connected to each other; The drains of the PMOS tube MP12, the PMOS tube MP22, the PMOS tube MP32, the PMOS tube MP42, the PMOS tube MP52, the PMOS tube MP62, the PMOS tube MP72 and the PMOS tube MP82 are connected to each other and to the source of the PMOS tube MP84; the sources of the PMOS tube MP14, the PMOS tube MP24, the PMOS tube MP34, the PMOS tube MP44, the PMOS tube MP54, the PMOS tube MP64, the PMOS tube MP74, the PMOS tube MP84, the PMOS tube MP16, the PMOS tube MP26, the PMOS tube MP36, the PMOS tube MP46, the PMOS tube MP56, the PMOS tube MP66, the PMOS tube MP76 and the PMOS tube MP86 are connected to each other; The gate of the PMOS tube MP83 is connected to the first output port C0 of the 4-16 decoder; the gate of the PMOS tube MP85 is connected to the second output port C1 of the 4-16 decoder; the gate of the PMOS tube MP73 is connected to the third output port C2 of the 4-16 decoder; the gate of the PMOS tube MP75 is connected to the fourth output port C3 of the 4-16 decoder; the gate of the PMOS tube MP63 is connected to the fifth output port C4 of the 4-16 decoder; the gate of the PMOS tube MP65 is connected to the sixth output port C5 of the 4-16 decoder; the gate of the PMOS tube MP53 is connected to the seventh output port C6 of the 4-16 decoder; the gate of the PMOS tube MP55 is connected to the eighth output port C7 ... The gate of P43 is connected to the ninth output port C8 of the 4-16 decoder; the gate of the PMOS tube MP45 is connected to the tenth output port C9 of the 4-16 decoder; the gate of the PMOS tube MP33 is connected to the eleventh output port C10 of the 4-16 decoder; the gate of the PMOS tube MP35 is connected to the twelfth output port C11 of the 4-16 decoder; the gate of the PMOS tube MP23 is connected to the thirteenth output port C12 of the 4-16 decoder; the gate of the PMOS tube MP25 is connected to the fourteenth output port C13 of the 4-16 decoder; the gate of the PMOS tube MP13 is connected to the fifteenth output port C14 of the 4-16 decoder; the gate of the PMOS tube MP15 is connected to the sixteenth output port C15 of the 4-16 decoder; The gate of the PMOS tube MP84 is connected to the first output terminal D0 of the second inverter INV2; the gate of the PMOS tube MP86 is connected to the second output terminal D1 of the second inverter INV2; the gate of the PMOS tube MP74 is connected to the third output terminal D2 of the second inverter INV2; the gate of the PMOS tube MP76 is connected to the fourth output terminal D3 of the second inverter INV2; the gate of the PMOS tube MP64 is connected to the fifth output terminal D4 of the second inverter INV2; the gate of the PMOS tube MP66 is connected to the sixth output terminal D5 of the second inverter INV2; the gate of the PMOS tube MP54 is connected to the seventh output terminal D6 of the second inverter INV2; the gate of the PMOS tube MP56 is connected to the eighth output terminal D7 ... The gate of P44 is connected to the ninth output terminal D8 of the second inverter INV2; the gate of the PMOS tube MP46 is connected to the tenth output terminal D9 of the second inverter INV2; the gate of the PMOS tube MP34 is connected to the eleventh output terminal D10 of the second inverter INV2; the gate of the PMOS tube MP36 is connected to the twelfth output terminal D11 of the second inverter INV2; the gate of the PMOS tube MP24 is connected to the thirteenth output terminal D12 of the second inverter INV2; the gate of the PMOS tube MP26 is connected to the fourteenth output terminal D13 of the second inverter INV2; the gate of the PMOS tube MP14 is connected to the fifteenth output terminal D14 of the second inverter INV2; the gate of the PMOS tube MP16 is connected to the sixteenth output terminal D15 of the second inverter INV2.

Images