A floating power supply voltage detection circuit and detection method thereof

Abstract

The present invention discloses a floating power supply voltage detection circuit and a detection method thereof, comprising a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3 and a Zener diode Z1. The detection voltage obtained by the present invention is independent of the gate-source voltage VGS of the MOS tube, and the noise coupling problem of the detection voltage caused by BST and SW is eliminated, thereby improving the accuracy of the floating power supply voltage detection.

Description

Technical Field

[0001] The present invention relates to a voltage detection circuit and a detection method thereof, in particular to a floating power supply voltage detection circuit and a detection method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] The DC-DC converter needs to drive the detection of the voltage difference between the bootstrap voltage domain, i.e., the high-side floating voltage BST and the floating ground SW, and then control the high-side drive circuit. Traditional technology converts the floating voltage difference, i.e., VBST-VSW, into a voltage related to the gate-source voltage VGS of the MOS tube for detection. However, the gate-source voltage VGS of the MOS tube is greatly affected by temperature and process deviation, causing the detection voltage to float. In addition, since the rising and falling slopes of the high-side floating voltage BST and the floating ground SW are very large, coupling interference will be caused to the detection voltage. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a floating power supply voltage detection circuit and a detection method thereof, so as to improve the detection accuracy of the detection voltage.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A floating power supply voltage detection circuit comprises a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3 and a Zener diode Z1, a source of the PMOS tube MP1 and a source of the PMOS tube MP3 are connected to a high-side floating voltage BST, and a PMOS tube MN1 is connected to a PMOS tube MP2, an NMOS tube MN3 is connected to a PMOS tube MP4, and a PMOS tube MN4 is connected to a PMOS tube MN5. The gate of the S transistor MP1 is connected to the gate of the PMOS transistor MP3, the drain of the PMOS transistor MP1 and the source of the PMOS transistor MP2, the drain of the PMOS transistor MP3 is connected to the source of the PMOS transistor MP4, the gate of the PMOS transistor MP2 is connected to the gate of the PMOS transistor MP4, the drain of the PMOS transistor MP2 and one end of the resistor R1, the other end of the resistor R1 is connected to the floating ground SW, the drain of the PMOS transistor MP4 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the cathode of the Zener diode Z1, the drain of the NMOS transistor MN1, the gate of the NMOS transistor MN1, the gate of the NMOS transistor MN2, and the capacitor C1. One end is connected to one end of the resistor R3, the source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN2, the other end of the resistor R3 is connected to one end of the capacitor C2, the gate of the NMOS tube NM4 and the gate of the NMOS tube MN3, the drain of the NMOS tube MN4 is connected to the source of the NMOS tube MN3, the drain of the NMOS tube MN3 is connected to the drain of the PMOS tube MP6, the gate of the PMOS tube MP6 and the gate of the PMOS tube MP8, the drain of the PMOS tube MP8 is connected to the source of the PMOS tube MP9 and outputs the detection voltage Vsns, the gate of the PMOS tube MP9 is connected to the drain of the PMOS tube MP9 and one end of the resistor R4, the source of the PMOS tube MP6 is connected to the drain of the PMOS tube MP5, the gate of the PMOS tube MP5 and one end of the resistor R5, the other end of the resistor R5 is connected to one end of the capacitor C3 and the gate of the PMOS tube MP7, the source of the PMOS tube MP8 is connected to the drain of the PMOS tube MP7, the source of the PMOS tube MP5, the other end of the capacitor C3 and the source of the PMOS tube MP7 are connected to the power supply VCC, and the anode of the Zener diode Z1, the source of the NMOS tube MN2, the other end of the capacitor C1, the other end of the capacitor C2, the source of the NMOS tube MN4 and the other end of the resistor R4 are grounded.

[0006] Furthermore, the PMOS tube MP1, the PMOS tube MP2 and the PMOS tube MP3 are low-voltage tubes, and the PMOS tube MP4 is a high-voltage tube.

[0007] Furthermore, the ratio of the width to length ratio of the PMOS tube MP3 to the PMOS tube MP1 is k1, and the width to length ratio of the PMOS tube MP1 is equal to that of the PMOS tube MP2.

[0008] Furthermore, the ratio of the width to length ratio of the NMOS transistor MN1 to the NMOS transistor MN3 is k2, and the ratio of the width to length ratio of the NMOS transistor MN2 to the NMOS transistor MN4 is k2.

[0009] Furthermore, the ratio of the width to length ratio of the PMOS tube MP5 and the PMOS tube MP7 is k3, and the ratio of the width to length ratio of the PMOS tube MP6 and the PMOS tube MP8 is k3.

[0010] Furthermore, the resistor R4 and the resistor R1 are resistors of the same type, and the ratio of the resistance value of the resistor R4 to the resistance value of the resistor R1 is k4.

[0011] Furthermore, the back gates of the PMOS transistor MP1 , the PMOS transistor MP2 , and the PMOS transistor MP9 are connected to the source.

[0012] Furthermore, the resistor R2 and the capacitor C1 form a first-stage filter, the resistor R3 and the capacitor C2 form a second-stage filter, and the resistor R5 and the capacitor C3 form a third-stage filter.

[0013] A detection method for a floating power supply voltage detection circuit comprises the following steps:

[0014] The current I1 flowing through the resistor R1 = (VBST-VSW-VGS1-VGS2) / R1, where VBST is the voltage of the high-side floating voltage BST, VSW is the voltage of the floating ground SW, VGS1 is the gate-source voltage of the PMOS tube MP1, and VGS2 is the gate-source voltage of the PMOS tube MP2;

[0015] The current flowing through the PMOS tube MP1 is equal to the current I1. The PMOS tube MP1 and the PMOS tube MP3 form a current mirror and the ratio of the width to length ratio of the PMOS tube MP3 to the PMOS tube MP1 is k1. Then, the current flowing through the PMOS tube MP3 is k1*I1. The current I2 flowing through the resistor R2 is equal to the current flowing through the PMOS tube MP3. Then, I2=k1*I1.

[0016] The current flowing through the NMOS tube MN1 and the NMOS tube MN2 is equal to the current I2, and since the ratio of the width-to-length ratio of the NMOS tube MN1 and the NMOS tube MN3 is k2, and the ratio of the width-to-length ratio of the NMOS tube MN2 and the NMOS tube MN4 is k2, the magnitude of the current flowing through the NMOS tube MN3 and the NMOS tube MN4 is k2*I2, the current flowing through the PMOS tube MP5 and the PMOS tube MP6 is equal to the current flowing through the NMOS tube MN3 and the NMOS tube MN4, and since the ratio of the width-to-length ratio of the PMOS tube MP5 and the PMOS tube MP7 is k3, and the ratio of the width-to-length ratio of the PMOS tube MP6 and the PMOS tube MP8 is k3, the magnitude of the current flowing through the PMOS tube MP7 and the PMOS tube MP8 is k3*k2*I2, and the current I4 flowing through the resistor R4 is equal to the current flowing through the PMOS tube MP7 and the PMOS tube MP8, that is, I4= k3*k2*I2;

[0017] Detection voltage Vsns=I4*R4+VGS9=k3*k2*I2*R4+VGS9

[0018] =k3*k2*k1*I1*R4+VGS9

[0019] =k3*k2*k1*(VBST-VSW-VGS1-VGS2)*R4 / R1+VGS9,

[0020] Where VGS9 is the gate-source voltage of PMOS tube MP9;

[0021] Since the width-to-length ratios of the PMOS tube MP1 and the PMOS tube MP2 are equal, VGS1=VGS2;

[0022] Then Vsns=k3*k2*k1*(VBST-VSW-2*VGS1)*R4 / R1+VGS9;

[0023] Let the width-to-length ratio of the PMOS tube MP9 be equal to the width-to-length ratio of the PMOS tube MP1, then VGS1=VGS9;

[0024] At the same time, take k1*k2*k3=1, k4=1 / 2,

[0025] So Vsns=(VBST-VSW-2*VGS1) / 2+VGS9

[0026] =(VBST-VSW) / 2-VGS1+VGS9=(VBST-VSW) / 2;

[0027] Then the detection voltage Vsns has nothing to do with the gate-source voltage VGS of the MOS tube;

[0028] By adjusting the resistance values ​​of the resistors R2 , R3 , and R4 and the capacitance values ​​of the capacitors C1 , C2 , and C3 , the coupling interference of the high-side floating voltage BST and the floating ground SW on the sampling voltage Vsns is eliminated.

[0029] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a floating power supply voltage detection circuit and a detection method thereof, the obtained detection voltage is independent of the gate-source voltage VGS of the MOS tube, and the noise coupling problem of BST and SW on the detection voltage is eliminated, thereby improving the accuracy of floating power supply voltage detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of a floating power supply voltage detection circuit of the present invention. DETAILED DESCRIPTION

[0031] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0032] like Figure 1As shown, a floating power supply voltage detection circuit of the present invention comprises a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3 and a Zener diode Z1, wherein the source of the PMOS tube MP1 and the source of the PMOS tube MP3 are connected to the high-side floating voltage B ST, the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP3, the drain of the PMOS tube MP1 and the source of the PMOS tube MP2, the drain of the PMOS tube MP3 is connected to the source of the PMOS tube MP4, the gate of the PMOS tube MP2 is connected to the gate of the PMOS tube MP4, the drain of the PMOS tube MP2 and one end of the resistor R1, the other end of the resistor R1 is connected to the floating ground SW, the drain of the PMOS tube MP4 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the cathode of the Zener diode Z1, the drain of the NMOS tube MN1, the gate of the NMOS tube MN1, the gate of the NMOS tube MN2, the One end of the capacitor C1 is connected to one end of the resistor R3, the source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN2, the other end of the resistor R3 is connected to one end of the capacitor C2, the gate of the NMOS tube NM4 and the gate of the NMOS tube MN3, the drain of the NMOS tube MN4 is connected to the source of the NMOS tube MN3, the drain of the NMOS tube MN3 is connected to the drain of the PMOS tube MP6, the gate of the PMOS tube MP6 and the gate of the PMOS tube MP8, the drain of the PMOS tube MP8 is connected to the source of the PMOS tube MP9 and outputs the detection voltage Vsns, the gate of the PMOS tube MP9 is connected to the gate of the PMOS tube MP9 The drain of the PMOS tube MP6 is connected to one end of the resistor R4, the source of the PMOS tube MP6 is connected to the drain of the PMOS tube MP5, the gate of the PMOS tube MP5 and one end of the resistor R5, the other end of the resistor R5 is connected to one end of the capacitor C3 and the gate of the PMOS tube MP7, the source of the PMOS tube MP8 is connected to the drain of the PMOS tube MP7, the source of the PMOS tube MP5, the other end of the capacitor C3 and the source of the PMOS tube MP7 are connected to the power supply VCC, and the anode of the Zener diode Z1, the source of the NMOS tube MN2, the other end of the capacitor C1, the other end of the capacitor C2, the source of the NMOS tube MN4 and the other end of the resistor R4 are grounded.

[0033] The PMOS tube MP1 , the PMOS tube MP2 , and the PMOS tube MP3 are low-voltage tubes, and the PMOS tube MP4 is a high-voltage tube.

[0034] The ratio of the width to length ratio of the PMOS tube MP3 to the PMOS tube MP1 is k1, and the width to length ratio of the PMOS tube MP1 to the PMOS tube MP2 is equal.

[0035] The ratio of the width to length ratio of the NMOS transistor MN1 to the NMOS transistor MN3 is k2, and the ratio of the width to length ratio of the NMOS transistor MN2 to the NMOS transistor MN4 is k2.

[0036] The ratio of the width to length ratio of the PMOS tube MP5 and the PMOS tube MP7 is k3, and the ratio of the width to length ratio of the PMOS tube MP6 and the PMOS tube MP8 is k3.

[0037] The resistor R4 and the resistor R1 are resistors of the same type, and the ratio of the resistance value of the resistor R4 to the resistance value of the resistor R1 is k4.

[0038] The back gates of the PMOS transistor MP1 , the PMOS transistor MP2 , and the PMOS transistor MP9 are connected to the source.

[0039] The resistor R2 and the capacitor C1 form a first-stage filter, the resistor R3 and the capacitor C2 form a second-stage filter, and the resistor R5 and the capacitor C3 form a third-stage filter.

[0040] A detection method for a floating power supply voltage detection circuit comprises the following steps:

[0041] The current I1 flowing through the resistor R1 = (VBST-VSW-VGS1-VGS2) / R1, where VBST is the voltage of the high-side floating voltage BST, VSW is the voltage of the floating ground SW, VGS1 is the gate-source voltage of the PMOS tube MP1, and VGS2 is the gate-source voltage of the PMOS tube MP2.

[0042] The current flowing through the PMOS tube MP1 is equal to the current I1. The PMOS tube MP1 and the PMOS tube MP3 form a current mirror and the ratio of the width to length ratio of the PMOS tube MP3 to the PMOS tube MP1 is k1. Then, the current flowing through the PMOS tube MP3 is k1*I1. The current I2 flowing through the resistor R2 is equal to the current flowing through the PMOS tube MP3, so I2=k1*I1.

[0043] The current flowing through the NMOS tube MN1 and the NMOS tube MN2 is equal to the current I2, and since the ratio of the width-to-length ratio of the NMOS tube MN1 and the NMOS tube MN3 is k2, and the ratio of the width-to-length ratio of the NMOS tube MN2 and the NMOS tube MN4 is k2, the magnitude of the current flowing through the NMOS tube MN3 and the NMOS tube MN4 is k2*I2, the current flowing through the PMOS tube MP5 and the PMOS tube MP6 is equal to the current flowing through the NMOS tube MN3 and the NMOS tube MN4, and since the ratio of the width-to-length ratio of the PMOS tube MP5 and the PMOS tube MP7 is k3, and the ratio of the width-to-length ratio of the PMOS tube MP6 and the PMOS tube MP8 is k3, the magnitude of the current flowing through the PMOS tube MP7 and the PMOS tube MP8 is k3*k2*I2, and the current I4 flowing through the resistor R4 is equal to the current flowing through the PMOS tube MP7 and the PMOS tube MP8, that is, I4= k3*k2*I2.

[0044] Detection voltage Vsns=I4*R4+VGS9=k3*k2*I2*R4+VGS9

[0045] =k3*k2*k1*I1*R4+VGS9

[0046] =k3*k2*k1*(VBST-VSW-VGS1-VGS2)*R4 / R1+VGS9,

[0047] Wherein VGS9 is the gate-source voltage of the PMOS tube MP9.

[0048] Since the width-to-length ratios of the PMOS tube MP1 and the PMOS tube MP2 are equal, VGS1=VGS2.

[0049] Then Vsns=k3*k2*k1*(VBST-VSW-2*VGS1)*R4 / R1+VGS9.

[0050] If the width-to-length ratio of the PMOS tube MP9 is equal to the width-to-length ratio of the PMOS tube MP1, then VGS1=VGS9.

[0051] At the same time, take k1*k2*k3=1, k4=1 / 2,

[0052] So Vsns=(VBST-VSW-2*VGS1) / 2+VGS9

[0053] =(VBST-VSW) / 2-VGS1+VGS9=(VBST-VSW) / 2.

[0054] The detection voltage Vsns has nothing to do with the gate-source voltage VGS of the MOS tube.

[0055] By adjusting the resistance values ​​of the resistors R2 , R3 , and R4 and the capacitance values ​​of the capacitors C1 , C2 , and C3 , the coupling interference of the high-side floating voltage BST and the floating ground SW on the sampling voltage Vsns is eliminated.

[0056] The present invention provides a floating power supply voltage detection circuit and a detection method thereof, wherein the obtained detection voltage is independent of the gate-source voltage VGS of a MOS tube, and the noise coupling problem of BST and SW on the detection voltage is eliminated, thereby improving the accuracy of floating power supply voltage detection.

[0057] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A floating power supply voltage detection circuit, characterized in that: The device comprises a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7, a PMOS tube MP8, a PMOS tube MP9, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3 and a Zener diode Z1. The source of the PMOS tube MP1 and the source of the PMOS tube MP3 are connected to the high-side floating voltage BST. The gate of the PMOS tube MP1 is connected to the high-side floating voltage BST. The gate of the PMOS tube MP3, the drain of the PMOS tube MP1 and the source of the PMOS tube MP2 are connected, the drain of the PMOS tube MP3 is connected to the source of the PMOS tube MP4, the gate of the PMOS tube MP2 is connected to the gate of the PMOS tube MP4, the drain of the PMOS tube MP2 and one end of the resistor R1, the other end of the resistor R1 is connected to the floating ground SW, the drain of the PMOS tube MP4 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the cathode of the Zener diode Z1, the drain of the NMOS tube MN1, the gate of the NMOS tube MN1, the gate of the NMOS tube MN2, one end of the capacitor C1 and the resistor R 3, the source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN2, the other end of the resistor R3 is connected to one end of the capacitor C2, the gate of the NMOS tube NM4 and the gate of the NMOS tube MN3, the drain of the NMOS tube MN4 is connected to the source of the NMOS tube MN3, the drain of the NMOS tube MN3 is connected to the drain of the PMOS tube MP6, the gate of the PMOS tube MP6 and the gate of the PMOS tube MP8, the drain of the PMOS tube MP8 is connected to the source of the PMOS tube MP9 and outputs the detection voltage Vsns, the gate of the PMOS tube MP9 is connected to the drain of the PMOS tube MP9 and the resistor One end of R4 is connected, the source of the PMOS tube MP6 is connected to the drain of the PMOS tube MP5, the gate of the PMOS tube MP5 and one end of the resistor R5, the other end of the resistor R5 is connected to one end of the capacitor C3 and the gate of the PMOS tube MP7, the source of the PMOS tube MP8 is connected to the drain of the PMOS tube MP7, the source of the PMOS tube MP5, the other end of the capacitor C3 and the source of the PMOS tube MP7 are connected to the power supply VCC, and the anode of the Zener diode Z1, the source of the NMOS tube MN2, the other end of the capacitor C1, the other end of the capacitor C2, the source of the NMOS tube MN4 and the other end of the resistor R4 are grounded.

2. The floating power supply voltage detection circuit according to claim 1, characterized in that: The PMOS tube MP1, the PMOS tube MP2 and the PMOS tube MP3 are low-voltage tubes, and the PMOS tube MP4 is a high-voltage tube.

3. The floating power supply voltage detection circuit according to claim 1, characterized in that: The ratio of the width to length ratio of the PMOS tube MP3 to the PMOS tube MP1 is k1, and the width to length ratio of the PMOS tube MP1 is equal to that of the PMOS tube MP2.

4. The floating power supply voltage detection circuit according to claim 1, characterized in that: The ratio of the width to length ratio of the NMOS transistor MN1 to the NMOS transistor MN3 is k2, and the ratio of the width to length ratio of the NMOS transistor MN2 to the NMOS transistor MN4 is k2.

5. The floating power supply voltage detection circuit according to claim 1, characterized in that: The ratio of the width to length ratio of the PMOS tube MP5 and the PMOS tube MP7 is k3, and the ratio of the width to length ratio of the PMOS tube MP6 and the PMOS tube MP8 is k3.

6. The floating power supply voltage detection circuit according to claim 1, characterized in that: The resistor R4 and the resistor R1 are resistors of the same type, and the ratio of the resistance value of the resistor R4 to the resistance value of the resistor R1 is k4.

7. The floating power supply voltage detection circuit according to claim 1, characterized in that: The back gates of the PMOS transistors MP1 , MP2 and MP9 are connected to the source electrodes.

8. The floating power supply voltage detection circuit according to claim 1, characterized in that: The resistor R2 and the capacitor C1 form a first-stage filter, the resistor R3 and the capacitor C2 form a second-stage filter, and the resistor R5 and the capacitor C3 form a third-stage filter.

9. A detection method for a floating power supply voltage detection circuit according to any one of claims 1 to 8, characterized in that The following steps are involved: The current I1 flowing through the resistor R1 = (VBST-VSW-VGS1-VGS2) / R1, where VBST is the voltage of the high-side floating voltage BST, VSW is the voltage of the floating ground SW, VGS1 is the gate-source voltage of the PMOS tube MP1, and VGS2 is the gate-source voltage of the PMOS tube MP2; The current flowing through the PMOS tube MP1 is equal to the current I1. The PMOS tube MP1 and the PMOS tube MP3 form a current mirror and the ratio of the width to length ratio of the PMOS tube MP3 to the PMOS tube MP1 is k1. Then, the current flowing through the PMOS tube MP3 is k1*I1. The current I2 flowing through the resistor R2 is equal to the current flowing through the PMOS tube MP3. Then, I2=k1*I1. The current flowing through the NMOS tube MN1 and the NMOS tube MN2 is equal to the current I2, and since the ratio of the width-to-length ratio of the NMOS tube MN1 and the NMOS tube MN3 is k2, and the ratio of the width-to-length ratio of the NMOS tube MN2 and the NMOS tube MN4 is k2, the magnitude of the current flowing through the NMOS tube MN3 and the NMOS tube MN4 is k2*I2, the current flowing through the PMOS tube MP5 and the PMOS tube MP6 is equal to the current flowing through the NMOS tube MN3 and the NMOS tube MN4, and since the ratio of the width-to-length ratio of the PMOS tube MP5 and the PMOS tube MP7 is k3, and the ratio of the width-to-length ratio of the PMOS tube MP6 and the PMOS tube MP8 is k3, the magnitude of the current flowing through the PMOS tube MP7 and the PMOS tube MP8 is k3*k2*I2, and the current I4 flowing through the resistor R4 is equal to the current flowing through the PMOS tube MP7 and the PMOS tube MP8, that is, I4= k3*k2*I2; Detection voltage Vsns=I4*R4+VGS9=k3*k2*I2*R4+VGS9 =k3*k2*k1*I1*R4+VGS9 =k3*k2*k1*(VBST-VSW-VGS1-VGS2)*R4 / R1+VGS9, Where VGS9 is the gate-source voltage of PMOS tube MP9; Since the width-to-length ratios of the PMOS tube MP1 and the PMOS tube MP2 are equal, VGS1=VGS2; Then Vsns=k3*k2*k1*(VBST-VSW-2*VGS1)*R4 / R1+VGS9; Let the width-to-length ratio of the PMOS tube MP9 be equal to the width-to-length ratio of the PMOS tube MP1, then VGS1=VGS9; At the same time, k1*k2*k3=1, k4=1 / 2, the ratio of the resistance value of resistor R4 to the resistance value of resistor R1 is k4; So Vsns=(VBST-VSW-2*VGS1) / 2+VGS9 =(VBST-VSW) / 2-VGS1+VGS9=(VBST-VSW) / 2; Then the detection voltage Vsns has nothing to do with the gate-source voltage VGS of the MOS tube; By adjusting the resistance values ​​of the resistors R2 , R3 , and R4 and the capacitance values ​​of the capacitors C1 , C2 , and C3 , the coupling interference of the high-side floating voltage BST and the floating ground SW on the sampling voltage Vsns is eliminated.

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