FPGA-based satellite-borne digital correlator use resource evaluation method

Abstract

The invention discloses an FPGA (Field Programmable Gate Array)-based satellite-borne digital correlator use resource evaluation method, which comprises the following steps of: 1, carrying out signal processing conversion on n paths of intermediate frequency input signals which are radio frequency signals received by a two-dimensional synthetic aperture antenna array, and then synchronously acquiring and outputting digital intermediate frequency signals by an AD (Analog to Digital) chip; 2, the control signal provides an integral period timestamp for the digital correlator; 3, outputting a correlation operation accumulated value between different channels in each integration period to a subsequent processing unit by an output signal, wherein C2n + 1 paths of correlation data are obtained; and step 4, the power supply module provides electric energy for the digital correlator single machine. According to the method, theoretical support and an instructive method are provided for evaluating the FPGA use resources of the digital correlator, the research and development period is effectively shortened, the efficiency is improved, and the development cost is reduced.

Description

Technical Field

[0001] The invention relates to the field of space microwave remote sensing, and in particular to a method for evaluating the use resources of a satellite-borne digital correlator based on FPGA. Background Art

[0002] With the development of science and technology, two-dimensional synthetic aperture microwave radiometer technology has been applied to satellite payloads to observe information such as land water resources. This technology uses multiple receiving antennas to receive microwave signals and obtains higher resolution by comprehensive processing of these signals. Compared with traditional single-antenna microwave radiometers, this technology can provide more accurate observation results and reduce the payload volume.

[0003] In order to obtain a larger observation field of view, the number of two-dimensional comprehensive aperture array units is often large, so the number of related operation units is also large. Considering the rapidity, convenience and flexibility of FPGA development, digital correlators in the satellite field are generally developed using FPGA. In order to further reduce the use of resources and reduce power consumption, digital correlators in the satellite field often use 1-bit quantization values ​​to calculate the correlation coefficient. Nevertheless, due to the huge number of FPGA operations, the power consumption generated is also huge. The increase in power consumption will cause the chip temperature to rise rapidly, which will not only cause temperature drift, but may even cause damage to the chip. Among them, temperature drift will cause the observed brightness temperature value measured by the microwave radiometer to have a large error.

[0004] The relevant calculation can be realized by multiplication and accumulation, which can be realized by using the DSP48E computing unit of FPGA, because DSP48E has great advantages in computing speed and power consumption. However, the number of DSP48E is relatively limited, and the cost increases exponentially with the increase of the number.

[0005] Assuming the correlator has 60 input channels, we need Each channel of correlation operation includes a complex multiplier, and each complex multiplier consumes 4 DSP48E operation units. For a 60-channel digital correlator, at least 7320 DSP48E operation units are required. This is unacceptable in terms of cost and resource utilization.

[0006] Invention patent CN106093884A proposes an improved FPGA-based multi-channel correlation processing implementation method, and invention patent CN112487354A proposes a comparator-based FPGA multi-channel high-speed real-time cross-correlation operation device. The core ideas of these patents are: (1) using a serial-to-parallel conversion accumulation circuit to solve the problem that the internal logic working clock frequency of the FPGA is lower than the sampling clock frequency; (2) using a multi-stage accumulator for data processing to reduce the use of logical resources for accumulation operations. However, the methods involved in the above patents do not perform theoretical calculations and effective evaluations on the use of resources. In addition, the heat dissipation method in the satellite field is generally conduction heat dissipation, and the heat dissipation conditions are limited. Therefore, in the satellite field, it is necessary to evaluate the resources of the FPGA to make full use of resources and reduce power consumption. Summary of the invention

[0007] In order to overcome the deficiencies in the prior art, the present invention provides a method for evaluating the use of resources of a satellite-borne digital correlator based on FPGA, which provides theoretical support and guidance for the early development and selection of a satellite-borne microwave radiometer digital correlator. The method does not require writing code in advance and putting it into an FPGA development environment for "synthesis" and "implementation", which can effectively shorten the R&D cycle, improve efficiency and reduce development costs.

[0008] In order to achieve the above-mentioned invention object, the technical solution adopted to solve the technical problem is as follows:

[0009] A method for evaluating the use resources of a spaceborne digital correlator based on FPGA comprises the following steps:

[0010] Step 1: The n-channel intermediate frequency input signals are radio frequency signals received by the two-dimensional synthetic aperture antenna array, which are processed and transformed, and then synchronously collected by the AD chip to output digital intermediate frequency signals;

[0011] Step 2: The control signal provides the digital correlator with an integration period timestamp;

[0012] Step 3: Output signal The accumulated value of correlation operation between different channels in each integration period is output to the subsequent processing unit. Road related data;

[0013] Step 4: The power module provides power to the digital correlator.

[0014] Furthermore, step 3 includes the following:

[0015] Step 31: The digital correlator receives n intermediate frequency input signals and performs correlation data processing and calculation between two channels;

[0016] Step 32: Use serial-to-parallel conversion to reduce the data processing speed, and process the 48-bit serial data continuously received by each channel in parallel at the same time;

[0017] Step 33: The digital correlator uses the control signal to accumulate the correlation values ​​output by all the correlation processing units within an integration period and outputs them to the subsequent units.

[0018] Furthermore, step 31 includes the following:

[0019] Step 311: In the digital correlator, the complex correlation operation between any two channels is mainly realized. The correlation operation between the two signals can be expressed as:

[0020]

[0021] In the field of satellite-borne, τ = 0 is generally taken, and x(n) and y(n) are complex discrete sequences;

[0022] In the FPGA implementation process, one complex correlation operation is equivalent to four multiplication operations and two addition operations. Each input complex signal consists of 1-bit I-channel and 1-bit Q-channel data respectively. The complex correlation processing unit is implemented using a 4-input 2-output lookup table LUT4-2.

[0023] Step 312: The four inputs of the 4-input 2-output lookup table correspond to I1, Q1, I2, and Q2, respectively. When the digital correlator uses a 1-bit quantization value to calculate the correlation coefficient, I1 and I2 have only two values, namely, 1 and -1; Q1 and Q2 also have only two values, namely, j and -j. When implemented in FPGA, the two values ​​of I1 and I2 and the two values ​​of Q1 and Q2 are represented by 1 and 0, respectively.

[0024] Step 313: The 2 outputs of the 4-input 2-output lookup table can be represented by 2 bits of data, that is, 00 represents 2, 01 represents -2, 10 represents 2j, and 11 represents -2j.

[0025] Further, step 32 includes the following contents:

[0026] Step 321: I1 and Q1 corresponding to CH1 and I2 and Q2 corresponding to CH2 are all composed of continuous 48 bits. The 48-bit data is divided into 8 groups, each with 6 bits, that is, data bits [5:0] are the first group, data bits [11:6] are the second group, and so on. Therefore, each of the 8 groups needs to use 6 LUT4-2 resources, and the total number of output bits of the 6 LUT4-2 is 6*2bit=12bit. At the same time, the real accumulated value of the output results of the 6 LUT4-2 can be represented by 8 bits, wherein the first 4 bits represent the real part and the last 4 bits represent the imaginary part. Then, the accumulated value of the output results of the 6 LUT4-2 can be represented by a 12-input 8-output LUT (LUT12-8), and 1 LUT12-8 is equivalent to a 2^12*8bit RAM, that is, a 4K*8bit RAM;

[0027] Step 322: The basic unit of BLOCK RAM is 36Kb, which can be configured as 4K*9bit. When used to instantiate the above 4K*8bit RAM, the efficiency can reach 88.9%;

[0028] Step 323: perform addition operations on the 4-bit real data and the 4-bit imaginary data output by the BLOCK RAM, respectively, in a step-by-step accumulation manner, firstly add the real and imaginary parts of group 1-2, group 3-4, group 5-6, and group 7-8, respectively, using 8 adders; secondly, add the real and imaginary parts of group 1-4 and group 5-8, respectively, and then use 4 adders; finally, add the real and imaginary parts of group 1-8 data, respectively, and then use 2 adders, using a total of 14 adders, and each DSP48E resource inside the FPGA can realize 4 independent 2-input adders, therefore, only 4 DSP48E resources are needed for the 14 adders;

[0029] Step 324: Each correlation processing unit needs to use 48 LUT4-2, 4 DSP48E and 8 36KBLOCK RAM, or 16 18K BLOCK RAM.

[0030] Further, step 33 includes the following contents:

[0031] Step 331: Assuming that one FPGA can process M complex correlation processing units, a BLOCK RAM with a depth of M is used as a memory for the correlation accumulation result. Each time a complex correlation accumulation operation of 48 sampling points is completed, the storage value of the correlation accumulation result of the corresponding address is read out, and then added to the complex correlation accumulation result of the current 48 sampling points. The summed result is then stored in the corresponding address, and the accumulation operation is completed. According to the design of 32 bits for the real part and the imaginary part, M*64 bits of memory are required, and this memory can be spliced ​​by T BLOCK RAMs;

[0032] Step 332: Input channel N, related processing unit M, storage space bit S, BLOCK RAM number T 18K (or T 36K ) is as follows:

[0033]

[0034] S=M×64

[0035]

[0036] In the formula, ceil means rounding up;

[0037] Step 333: The digital correlator uses the control signal to accumulate M-channel correlation values ​​within an integration period. Through time division multiplexing, the M-channel correlation values ​​share two adders. Each DSP48E contains two adders, so the entire digital correlator needs to use an additional DSP48E resource.

[0038] Step 334: The total resources used by the FPGA-based onboard digital correlator are at least: M*48 LUT4-2, M*4+1 DSP48E, M*8+T 36k 36K BLOCK RAM or M*16+T 18k 18K BLOCK RAM.

[0039] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0040] 1. The present invention designs related algorithms for the key resource modules of FPGA, such as LUT, DSP48E and BLOCK RAM, and can make full use of the core resources of FPGA;

[0041] 2. Compared with the traditional serial-to-parallel conversion accumulation circuit, the serial-to-parallel conversion method for the input channel proposed by the present invention does not accumulate the converted data, but uses LUT for processing, thereby reducing the internal working clock frequency of the FPGA;

[0042] 3. The present invention proposes a novel digital correlator implementation method, which optimizes FPGA operation logic, improves resource utilization, and optimally allocates resources;

[0043] 4. The present invention provides theoretical support and guiding methods for the evaluation of digital correlator FPGA usage resources, effectively shortening the R&D cycle, improving efficiency, and reducing development costs. In addition, reasonable resource utilization can effectively reduce FPGA power consumption and improve the reliability of satellite payloads. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0045] Figure 1 This is a single-machine input and output structure diagram of the satellite-borne digital correlator in the present invention;

[0046] Figure 2 It is an equivalent schematic diagram of the complex correlation operation unit in the present invention;

[0047] Figure 3 It is a diagram of a method for implementing a related processing operation unit in the present invention;

[0048] Figure 4 This is a diagram of a new digital correlator implementation method in the present invention. DETAILED DESCRIPTION

[0049] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] Due to the complexity of the satellite field, the satellite digital correlator generally only has the function of correlation processing and operation. Its input and output structure is as follows: Figure 1 As shown, including n intermediate frequency input signals, control signals, power supplies and output signals, this embodiment discloses a method for evaluating the use of resources of a satellite-borne digital correlator based on FPGA, comprising the following steps:

[0051] Step 1: The n-channel intermediate frequency input signals are radio frequency signals received by the two-dimensional synthetic aperture antenna array, which are processed and transformed, and then synchronously collected by the AD chip to output digital intermediate frequency signals;

[0052] Step 2: The control signal provides the digital correlator with an integration period timestamp;

[0053] Step 3: Output signal The accumulated value of correlation operation between different channels in each integration period is output to the subsequent processing unit. Road related data;

[0054] Specifically, step 3 includes the following contents:

[0055] Step 31: The digital correlator receives n intermediate frequency input signals and performs correlation data processing and calculation between two channels;

[0056] Furthermore, step 31 includes the following:

[0057] Step 311: In the digital correlator, the complex correlation operation between any two channels is mainly realized. The correlation operation between the two signals can be expressed as:

[0058]

[0059] In the field of satellite-borne, τ = 0 is generally taken, and x(n) and y(n) are complex discrete sequences;

[0060] In the FPGA implementation, a complex correlation operation is equivalent to 4 multiplication operations and 2 addition operations, such as Figure 2 As shown, each input complex signal consists of 1-bit I and 1-bit Q data. If the multiplication operation is directly performed using the DSP48E operation unit, it will consume too many operation resources. Therefore, the complex correlation processing unit is implemented using a 4-input 2-output lookup table LUT4-2, and the LUT resources in the FPGA are much larger than the DSP48E resources.

[0061] Step 312: The four inputs of the 4-input 2-output lookup table correspond to I1, Q1, I2, and Q2, respectively. When the digital correlator uses a 1-bit quantization value to calculate the correlation coefficient, I1 and I2 have only two values, namely, 1 and -1; Q1 and Q2 also have only two values, namely, j and -j. When implemented in FPGA, the two values ​​of I1 and I2 and the two values ​​of Q1 and Q2 are represented by 1 and 0, respectively.

[0062] Step 313: The 2 outputs of the 4-input 2-output lookup table can be represented by 2 bits of data, that is, 00 represents 2, 01 represents -2, 10 represents 2j, and 11 represents -2j.

[0063] The one LUT-4 described above can be completed by just one LUT in the FPGA resources, and the resource utilization rate of the LUT can reach 100%.

[0064] Step 32: Use serial-to-parallel conversion to reduce the data processing speed, and process the 48-bit serial data continuously received by each channel in parallel at the same time;

[0065] Furthermore, the sampling frequency corresponding to the n-channel input signals of the digital correlator is often greater than the working clock frequency inside the FPGA. Therefore, the serial-to-parallel method can be used to reduce the speed of data processing. Specifically, the 48-bit serial data continuously received by each channel is processed in parallel. Taking CH1 and CH2 as examples, the implementation method of the correlation processing operation unit is as follows: Figure 3 In this embodiment, step 32 includes the following contents:

[0066] Step 321: I1 and Q1 corresponding to CH1 and I2 and Q2 corresponding to CH2 are all composed of continuous 48 bits. The 48-bit data is divided into 8 groups, each with 6 bits, that is, data bits [5:0] are the first group, data bits [11:6] are the second group, and so on. Therefore, each of the 8 groups needs to use 6 LUT4-2 resources, and the total number of output bits of the 6 LUT4-2 is 6*2bit=12bit. At the same time, the real accumulated value of the output results of the 6 LUT4-2 can be represented by 8 bits, wherein the first 4 bits represent the real part and the last 4 bits represent the imaginary part. Then, the accumulated value of the output results of the 6 LUT4-2 can be represented by a 12-input 8-output LUT (LUT12-8), and 1 LUT12-8 is equivalent to a 2^12*8bit RAM, that is, a 4K*8bit RAM;

[0067] Step 322: The basic unit of BLOCK RAM is 36Kb, which can be configured as 4K*9bit. When used to instantiate the above 4K*8bit RAM, the efficiency can reach 88.9%;

[0068] Step 323: Figure 3 As shown, the 4-bit real data and 4-bit imaginary data output by the BLOCK RAM are added separately, and a step-by-step accumulation method is adopted. First, the real and imaginary parts of groups 1-2, groups 3-4, groups 5-6, and groups 7-8 are added separately, and 8 adders are used; secondly, the real and imaginary parts of groups 1-4 and groups 5-8 are added separately, and 4 adders are used again; finally, the real and imaginary parts of the data of groups 1-8 are added separately, and 2 adders are used again, and a total of 14 adders are used. Each DSP48E resource inside the FPGA can realize 4 independent 2-input adders. Therefore, only 4 DSP48E resources are needed for the 14 adders.

[0069] Step 324: Each correlation processing unit needs to use 48 LUT4-2, 4 DSP48E and 8 36KBLOCK RAM, or 16 18K BLOCK RAM.

[0070] Step 33: The digital correlator uses the control signal to accumulate the correlation values ​​output by all the correlation processing units within an integration period and outputs them to the subsequent units, such as Figure 4 shown.

[0071] Further, step 33 includes the following contents:

[0072] Step 331: Assuming that one FPGA can process M complex correlation processing units, a BLOCK RAM with a depth of M is used as a memory for the correlation accumulation result. Each time a complex correlation accumulation operation of 48 sampling points is completed, the storage value of the correlation accumulation result of the corresponding address is read out, and then added to the complex correlation accumulation result of the current 48 sampling points. The summed result is then stored in the corresponding address, and the accumulation operation is completed. According to the design of 32 bits for the real part and the imaginary part, M*64 bits of memory are required, and this memory can be spliced ​​by T BLOCK RAMs;

[0073] Step 332: Input channel N, related processing unit M, storage space bit S, BLOCK RAM number T 18K (or T 36K ) is as follows:

[0074]

[0075] S=M×64

[0076]

[0077] In the formula, ceil means rounding up;

[0078] Step 333: The digital correlator uses the control signal to accumulate M-channel correlation values ​​within an integration period. Through time division multiplexing, the M-channel correlation values ​​share two adders. Each DSP48E contains two adders, so the entire digital correlator needs to use an additional DSP48E resource.

[0079] Step 334: The total resources used by the FPGA-based onboard digital correlator are at least: M*48 LUT4-2, M*4+1 DSP48E, M*8+T 36k 36K BLOCK RAM or M*16+T 18k 18K BLOCK RAM.

[0080] Step 4: The power module provides power to the digital correlator.

[0081] In summary, compared with the traditional serial-to-parallel conversion accumulation circuit, the serial-to-parallel conversion method for the input channel proposed by the present invention no longer accumulates the converted data, but uses LUT processing, thereby reducing the internal working clock frequency of the FPGA; the present invention designs related processing algorithms for the key resource modules of FPGA, such as LUT, DSP48E and BLOCK RAM, and can make full use of the core resources of the FPGA; a new digital correlator implementation method proposed by the present invention optimizes the FPGA operation logic, improves the resource utilization rate, and optimally allocates the used resources; the present invention provides theoretical support and guiding methods for the resource evaluation of the digital correlator FPGA, effectively shortening the research and development cycle, improving efficiency, and reducing development costs. In addition, reasonable resource utilization can effectively reduce the power consumption of the FPGA and improve the reliability of the satellite payload.

[0082] The above describes the specific implementation of the present invention in conjunction with the accompanying drawings, mainly describing the design principle and design ideas of a resource evaluation method for a satellite-borne digital correlator based on FPGA, and is not intended to limit the present invention. In addition, the number of core resources corresponding to each FPGA manufacturer and each FPGA model may be slightly different. Any modification, data adjustment, equivalent replacement and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for evaluating the use of resources of a satellite-borne digital correlator based on FPGA, characterized in that: The following steps are involved: Step 1: The n-channel intermediate frequency input signals are radio frequency signals received by the two-dimensional synthetic aperture antenna array, which are processed and transformed, and then synchronously collected by the AD chip to output digital intermediate frequency signals; Step 2: The control signal provides the digital correlator with an integration period timestamp; Step 3: Output signal The accumulated value of correlation operation between different channels in each integration period is output to the subsequent processing unit. Road related data; Step 4: The power module provides power to the digital correlator.

2. The method for evaluating the use of resources of a satellite-borne digital correlator based on FPGA according to claim 1, characterized in that: Step 3 includes the following: Step 31: The digital correlator receives n intermediate frequency input signals and performs correlation data processing and calculation between two channels; Step 32: Use serial-to-parallel conversion to reduce the data processing speed, and process the 48-bit serial data continuously received by each channel in parallel at the same time; Step 33: The digital correlator uses the control signal to accumulate the correlation values ​​output by all the correlation processing units within an integration period and outputs them to the subsequent units.

3. The method for evaluating the use of resources of a satellite-borne digital correlator based on FPGA according to claim 2, characterized in that: Step 31 includes the following: Step 311: In the digital correlator, the complex correlation operation between any two channels is mainly realized. The correlation operation between the two signals can be expressed as: In the field of satellite-borne, τ = 0 is generally taken, and x(n) and y(n) are complex discrete sequences; In the FPGA implementation process, one complex correlation operation is equivalent to four multiplication operations and two addition operations. Each input complex signal consists of 1-bit I-channel and 1-bit Q-channel data respectively. The complex correlation processing unit is implemented using a 4-input 2-output lookup table LUT4-2. Step 312: The four inputs of the 4-input 2-output lookup table correspond to I1, Q1, I2, and Q2, respectively. When the digital correlator uses a 1-bit quantization value to calculate the correlation coefficient, I1 and I2 have only two values, namely, 1 and -1; Q1 and Q2 also have only two values, namely, j and -j. When implemented in FPGA, the two values ​​of I1 and I2 and the two values ​​of Q1 and Q2 are represented by 1 and 0, respectively. Step 313: The 2 outputs of the 4-input 2-output lookup table can be represented by 2 bits of data, that is, 00 represents 2, 01 represents -2, 10 represents 2j, and 11 represents -2j.

4. The method for evaluating the use of resources of a satellite-borne digital correlator based on FPGA according to claim 2, characterized in that: Step 32 includes the following: Step 321: I1 and Q1 corresponding to CH1 and I2 and Q2 corresponding to CH2 are all composed of continuous 48 bits. The 48-bit data is divided into 8 groups, each with 6 bits, that is, data bits [5:0] are the first group, data bits [11:6] are the second group, and so on. Therefore, each of the 8 groups needs to use 6 LUT4-2 resources, and the total number of output bits of the 6 LUT4-2 is 6*2bit=12bit. At the same time, the real accumulated value of the output results of the 6 LUT4-2 can be represented by 8 bits, wherein the first 4 bits represent the real part and the last 4 bits represent the imaginary part. Then, the accumulated value of the output results of the 6 LUT4-2 can be represented by a 12-input 8-output LUT (LUT12-8), and 1 LUT12-8 is equivalent to a 2^12*8bit RAM, that is, a 4K*8bit RAM; Step 322: The basic unit of BLOCK RAM is 36Kb, which can be configured as 4K*9bit. When used to instantiate the above 4K*8bit RAM, the efficiency can reach 88.9%; Step 323: perform addition operations on the 4-bit real data and the 4-bit imaginary data output by the BLOCK RAM, respectively, in a step-by-step accumulation manner, firstly add the real and imaginary parts of group 1-2, group 3-4, group 5-6, and group 7-8, respectively, using 8 adders; secondly, add the real and imaginary parts of group 1-4 and group 5-8, respectively, and then use 4 adders; finally, add the real and imaginary parts of group 1-8 data, respectively, and then use 2 adders, using a total of 14 adders, and each DSP48E resource inside the FPGA can realize 4 independent 2-input adders, therefore, only 4 DSP48E resources are needed for the 14 adders; Step 324: Each correlation processing unit needs to use 48 LUT4-2, 4 DSP48E and 8 36K BLOCKRAM, or 16 18K BLOCK RAM.

5. The method for evaluating the use of resources of a satellite-borne digital correlator based on FPGA according to claim 2, characterized in that: Step 33 includes the following: Step 331: Assuming that one FPGA can process M complex correlation processing units, a BLOCKRAM with a depth of M is used as a memory for the correlation accumulation result. Each time a complex correlation accumulation operation of 48 sampling points is completed, the storage value of the correlation accumulation result of the corresponding address is read out, and then added to the complex correlation accumulation result of the current 48 sampling points. The summed result is then stored in the corresponding address, and the accumulation operation is completed. According to the design of 32 bits for the real part and the imaginary part, M*64 bits of memory are required, and this memory can be spliced ​​by T BLOCK RAMs; Step 332: Input channel N, related processing unit M, storage space bit S, BLOCK RAM number T 18K (or T 36K ) is as follows: S=M×64 In the formula, ceil means rounding up; Step 333: The digital correlator uses the control signal to accumulate M-channel correlation values ​​within an integration period. Through time division multiplexing, the M-channel correlation values ​​share two adders. Each DSP48E contains two adders, so the entire digital correlator needs to use an additional DSP48E resource. Step 334: The total resources used by the FPGA-based onboard digital correlator are at least: M*48 LUT4-2, M*4+1 DSP48E, M*8+T 36k 36K BLOCK RAM or M*16+T 18k 18K BLOCK RAM.

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