Array substrate, display panel and display device

Abstract

Embodiments of the present application provide an array substrate, a display panel and a display device, wherein the array substrate comprises: a substrate; a plurality of shift register units arranged on one side of the substrate; a plurality of clock signal lines arranged on the same side of the substrate as the shift register units, the plurality of clock signal lines are arranged one by one corresponding to the plurality of shift register units, and each clock signal line is used for inputting a clock signal of a clock signal source into a corresponding shift register unit; and an overlapping conductive line arranged on a side of the clock signal line away from the substrate, the orthographic projection of the overlapping conductive line on the substrate and the orthographic projection of each clock signal line on the substrate both have overlapping regions to form overlapping capacitances between each clock signal line. The technical solution of the embodiments of the present application can make the clock signal waveforms output from the plurality of clock signal lines to the shift register units consistent, thereby avoiding causing charging differences and avoiding generating horizontal horizontal lines, and effectively improving the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Currently, gate driving circuits are typically formed on the array substrate of a liquid crystal display using an array process, known as Gate Driver on Array (GOA) technology. The gate driving circuit usually includes multiple shift register units, each receiving a clock signal via a corresponding clock signal line. These clock signal lines are coupled, with closer clock signal lines exhibiting stronger coupling and farther clock signal lines exhibiting weaker coupling. Therefore, the varying degrees of coupling between edge clock signal lines and central clock signal lines result in differences in the output clock signal waveform, leading to charging differences and the generation of horizontal stripes. Summary of the Invention

[0003] This application provides an array substrate, a display panel, and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As one aspect of the embodiments of this application, this application provides an array substrate, including: a substrate; a plurality of shift register units disposed on one side of the substrate; a plurality of clock signal lines disposed on the same side of the substrate as the shift register units, wherein the plurality of clock signal lines are configured in one-to-one correspondence with the plurality of shift register units, and each clock signal line is used to input a clock signal from a clock signal source into the corresponding shift register unit; and overlapping conductive lines disposed on the side of the clock signal lines away from the substrate, wherein the orthographic projection of the overlapping conductive lines on the substrate and the orthographic projection of each clock signal line on the substrate both have overlapping areas, so as to form overlapping capacitance with each clock signal line.

[0005] In one implementation, the overlapping conductive lines are located at the end of the clock signal line furthest from the clock signal source.

[0006] In one embodiment, the ratio of the width of the overlapping conductive lines to the width of each clock signal line is 0.5 to 2.

[0007] In one embodiment, the array substrate further includes: a gate metal layer disposed on one side of the substrate, the gate metal layer including a plurality of clock signal lines; a source / drain metal layer disposed on the side of the gate metal layer opposite to the substrate; and a transparent electrode layer disposed on the side of the gate metal layer opposite to the substrate; wherein the source / drain metal layer includes overlapping conductive lines; or, the transparent electrode layer includes overlapping conductive lines.

[0008] In one embodiment, when the source / drain metal layer includes overlapping conductive lines, the overlapping area of ​​the orthographic projection of the overlapping conductive lines on the substrate and the orthographic projection of the plurality of clock signal lines on the substrate is S1; when the transparent electrode layer includes overlapping conductive lines, the overlapping area of ​​the orthographic projection of the overlapping conductive lines on the substrate and the orthographic projection of the plurality of clock signal lines on the substrate is S2; wherein, S1 < S2.

[0009] In one embodiment, the array substrate further includes: a DC signal line, disposed on the same layer as multiple clock signal lines, for inputting the DC signal from the DC signal source into the shift register unit, wherein the orthographic projection of the DC signal line on the substrate and the orthographic projection of the overlapping conductive lines on the substrate have an overlapping area.

[0010] In one embodiment, the array substrate further includes: a DC signal line disposed on the same layer as multiple clock signal lines, wherein at least one insulating layer is disposed between the DC signal line and the overlapping conductive lines, and vias are formed on each insulating layer, and the DC signal line is electrically connected to the overlapping conductive lines through the vias.

[0011] In one embodiment, multiple clock signal lines are arranged at intervals along a first direction, and each clock signal line extends along a second direction perpendicular to the first direction; overlapping conductive lines extend along the first direction.

[0012] In one embodiment, multiple clock signal lines are arranged at intervals along a first direction, and each clock signal line extends along a second direction perpendicular to the first direction; the extension direction of the overlapping conductive lines is inclined relative to both the first and second directions.

[0013] In one embodiment, multiple clock signal lines are spaced apart along a first direction, and each clock signal line extends along a second direction perpendicular to the first direction; the overlapping conductive lines include a first connecting segment, a second connecting segment, and a third connecting segment, the extension directions of the first connecting segment and the third connecting segment are parallel to the first direction, the second connecting segment is connected between the first connecting segment and the third connecting segment, and the extension direction of the second connecting segment is parallel to the second direction.

[0014] In one embodiment, multiple clock signal lines are arranged at intervals along a first direction, and each clock signal line extends along a second direction perpendicular to the first direction; the overlapping conductive lines include a fourth connecting segment, a fifth connecting segment, a sixth connecting segment, a seventh connecting segment, and an eighth connecting segment, wherein the fifth connecting segment is connected between one end of the sixth connecting segment and the fourth connecting segment, and the seventh connecting segment is connected between the other end of the sixth connecting segment and the eighth connecting segment; wherein the fourth connecting segment, the sixth connecting segment, and the eighth connecting segment all extend along the first direction, and the fifth connecting segment and the seventh connecting segment all extend along the second direction.

[0015] As another aspect of the present application, the present application provides a display panel including the array substrate of any of the above embodiments.

[0016] As another aspect of the present application, the present application provides a display device including the display panel of any of the above embodiments.

[0017] The embodiments of this application employ the above-described technical solution to ensure that the clock signal waveforms output from multiple clock signal lines to the shift register unit are consistent, thereby avoiding charging differences, preventing the generation of horizontal stripes, and effectively improving the display effect.

[0018] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0019] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0020] Figure 1 This diagram illustrates clock signal lines and DC signal lines in related technologies.

[0021] Figure 2 This diagram shows the clock signal waveform of the input clock signal line in the relevant technology;

[0022] Figure 3 A schematic diagram showing a clock signal line, a shift register unit, and overlapping conductive lines according to an embodiment of this application;

[0023] Figure 4 A partial cross-sectional structural schematic diagram of an array substrate according to an embodiment of this application is shown;

[0024] Figure 5 A schematic diagram showing a clock signal line, a DC signal line, and overlapping conductive lines according to a first embodiment of this application is provided.

[0025] Figure 6 A schematic diagram showing a clock signal line, a DC signal line, and overlapping conductive lines according to a second embodiment of this application is provided.

[0026] Figure 7 A schematic diagram of a clock signal line, a DC signal line, and overlapping conductive lines according to a third embodiment of this application is shown.

[0027] Figure 8 A schematic diagram showing a clock signal line, a DC signal line, and overlapping conductive lines according to a fourth embodiment of this application is provided.

[0028] Figure 9 A schematic diagram of a clock signal line, a DC signal line, and overlapping conductive lines according to a fifth embodiment of this application is shown.

[0029] Explanation of reference numerals in the attached figures:

[0030] 100: Substrate; 300: Clock signal line; 400: Overlapping conductive line; 410: First connection segment; 420: Second connection segment; 430: Third connection segment; 440: Fourth connection segment; 450: Fifth connection segment; 460: Sixth connection segment; 470: Seventh connection segment; 480: Eighth connection segment; 500: Gate metal layer; 600: Source / drain metal layer; 700: Transparent electrode layer; 800: Gate insulating layer; 900: Source / drain insulating layer; 1000: DC signal line. Detailed Implementation

[0031] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0032] Figure 1 A schematic diagram of clock signal lines, DC signal lines, and shift register units in related technologies is shown; Figure 2 The diagram shows the clock signal waveform of the input clock signal line in the related art. In the related art, such as... Figure 1 and Figure 2 As shown, GOA (Go-of-Area) television equipment typically employs a design with multiple clock signal lines arranged side-by-side. A DC signal line, such as a low-level signal line, is located on one side of each clock signal line. Figure 1 and Figure 2 The diagram shows eight clock signal lines CLK1 to CLK8 and one DC signal line LVGL. When the clock signal on each clock signal line transitions (e.g., from high to low or low to high), it couples to the clock signals on nearby clock signal lines. The higher the refresh rate, the stronger the coupling between the clock signal lines. The coupling is stronger between clock signal lines that are close together and weaker between clock signal lines that are far apart. Therefore, the clock signal lines at the edges are coupled to different degrees than those in the middle, resulting in differences in the clock signal waveforms output by the edge and middle clock signal lines. This difference causes charging differences and produces horizontal stripes on the display panel.

[0033] To address the aforementioned problems, the first aspect of this application provides an array substrate. The following is in conjunction with... Figures 3-9An array substrate according to an embodiment of the first aspect of this application is described.

[0034] Figure 3 A schematic diagram showing a clock signal line 300, a shift register unit, and overlapping conductive lines 400 according to an embodiment of this application is provided. Figure 4 A partial cross-sectional structural diagram of an array substrate according to an embodiment of this application is shown. Figure 3 and Figure 4 As shown, the array substrate includes: a substrate 100, multiple shift register units, multiple clock signal lines 300, and overlapping conductive lines 400. The substrate 100 can be a glass substrate or a flexible substrate. In the description of this application, "multiple" means two or more.

[0035] Specifically, multiple shift register units are disposed on one side of the substrate 100. Multiple clock signal lines 300 are disposed on the same side of the substrate 100 as the shift register units, with each clock signal line 300 corresponding to one of the shift register units. Each clock signal line 300 is used to input the clock signal from the clock signal source into the corresponding shift register unit. Overlapping conductive lines 400 are disposed on the side of the clock signal lines 300 facing away from the substrate 100. The orthographic projection of the overlapping conductive lines 400 on the substrate 100 overlaps with the orthographic projection of each clock signal line 300 on the substrate 100, forming overlapping capacitance between them.

[0036] For example, substrate 100 may have a display area and a non-display area located outside the display area, such as the non-display area surrounding the display area. Multiple shift register units, multiple clock signal lines 300, and overlapping conductive lines 400 may all be located in the non-display area. Figure 3 The diagram shows eight clock signal lines 300 and eight shift register units GOA(n) to GOA(n+7). The eight clock signal lines 300 can be arranged at intervals along a first direction, and each clock signal line 300 can extend along a second direction perpendicular to the first direction. Figure 3The first direction is left-right, and the second direction is up-down. One end of each clock signal line 300 can be connected to a clock signal source to input the clock signal from the clock signal source into the corresponding shift register unit. The overlapping area of ​​the orthographic projection of the overlapping conductive line 400 on the substrate 100 and the orthographic projection of each clock signal line 300 on the substrate 100 can be equal or unequal. Since the orthographic projections of the overlapping conductive line 400 on the substrate 100 and the orthographic projections of each clock signal line 300 on the substrate 100 all have overlapping areas, overlapping capacitance can be formed between the overlapping conductive line 400 and each clock signal line 300. According to the principle of capacitive coupling, if the clock signal of any one of the eight clock signal lines 300 changes due to coupling, the overlapping capacitance will pull the clock signals of the other clock signal lines 300 to change together, thereby suppressing the waveform differences of the clock signals output by multiple clock signal lines 300 and keeping the waveforms of the clock signals output by multiple clock signal lines 300 consistent.

[0037] Optionally, the material of the overlapping conductive lines 400 can be metal or other conductive materials, such as metal oxide semiconductors, such as indium tin oxide (ITO).

[0038] Figure 3 The illustration shows eight clock signal lines 300 and eight shift register units for illustrative purposes. However, after reading the technical solution of this application, a person skilled in the art will obviously understand that the solution can be applied to other numbers of clock signal lines 300 and shift register units, which would also fall within the protection scope of this application.

[0039] According to the array substrate of this application embodiment, by providing overlapping conductive lines 400 on the side of the clock signal line 300 away from the substrate 100, and making the orthographic projection of the overlapping conductive lines 400 on the substrate 100 overlap with the orthographic projection of each clock signal line 300 on the substrate 100, an overlapping capacitance is formed between them, so that the clock signal waveforms output by multiple clock signal lines 300 to the shift register unit are consistent, thereby avoiding charging differences, avoiding the generation of horizontal stripes, and effectively improving the display effect.

[0040] In one embodiment, the overlapping conductive line 400 is located at the end of the clock signal line 300 furthest from the clock signal source. For example, the clock signal line 300 may have a first end and a second end, with the first end connected to the clock signal source and the second end located furthest from the clock signal source. The overlapping conductive line 400 is positioned close to the second end of the clock signal line 300, meaning the minimum distance between the overlapping conductive line 400 and the first end of the clock signal line 300 is greater than the minimum distance between the overlapping conductive line 400 and the second end of the clock signal line 300. Since the clock signal source can provide a stable clock signal, the coupling effect between the two clock signal lines 300 can be suppressed to some extent. Therefore, horizontal lines are less likely to appear near the first end of the clock signal line 300, while horizontal lines typically appear near the second end of the clock signal line 300.

[0041] In this embodiment, by placing the overlapping conductive line 400 at the end of the clock signal line 300 away from the clock signal source, the clock signal waveforms output by the multiple clock signal lines 300 to the shift register unit are further ensured to be consistent, thereby avoiding charging differences and preventing horizontal stripes from being generated at the end of the clock signal line 300 away from the clock signal source.

[0042] In one embodiment, the ratio of the width of the overlapping conductive line 400 to the width of each clock signal line 300 is 0.5 to 2 (including endpoint values). That is, the width of the overlapping conductive line 400 is 0.5 to 2 times the width of each clock signal line 300. The width direction can be parallel to the surface of the substrate 100. Specifically, for example, if the ratio of the width of the overlapping conductive line 400 to the width of each clock signal line 300 is less than 0.5, the width of the overlapping conductive line 400 may be too small, thereby reducing the structural strength of the overlapping conductive line 400 and affecting the reliability of the overlapping conductive line 400 in suppressing coupling differences between the clock signal lines 300; if the ratio of the width of the overlapping conductive line 400 to the width of each clock signal line 300 is greater than 2, the width of the overlapping conductive line 400 may be too large, resulting in excessive space occupied by the overlapping conductive line 400, which is detrimental to the arrangement of other interconnects in the array substrate.

[0043] In this embodiment, by making the ratio of the width of the overlapping conductive line 400 to the width of each clock signal line 300 between 0.5 and 2, the ratio of the width of the overlapping conductive line 400 to the width of each clock signal line 300 is reasonable. This ensures that the overlapping conductive line 400 can effectively suppress the coupling differences between the clock signal lines 300, while avoiding the overlapping conductive line 400 occupying too large an area, thereby facilitating the layout of other connecting lines.

[0044] In one implementation, reference Figure 3 and Figure 4The array substrate further includes a gate metal layer 500, a source / drain metal layer 600, and a transparent electrode layer 700. The gate metal layer 500 is disposed on one side of the substrate 100 and includes the aforementioned plurality of clock signal lines 300. The source / drain metal layer 600 is disposed on the side of the gate metal layer 500 facing away from the substrate 100. The transparent electrode layer 700 is disposed on the side of the gate metal layer 500 facing away from the substrate 100. The source / drain metal layer 600 includes the aforementioned overlapping conductive lines 400; or, the transparent electrode layer 700 includes the aforementioned overlapping conductive lines 400.

[0045] Exemplarily, the gate metal layer 500 may include a gate electrode. The source / drain metal layer 600 may include a first electrode and a second electrode, one of which is a source electrode and the other is a drain electrode. The substrate 100 may further include an active layer (not shown), which may include a channel region and non-channel regions located on both sides of the channel region, with the first electrode and the second electrode respectively contacting the corresponding non-channel regions. A gate insulating layer 800 is disposed between the source / drain metal layer 600 and the gate metal layer 500, and a source / drain insulating layer 900 is disposed between the source / drain metal layer 600 and the transparent electrode layer 700. The gate electrode, the first electrode, the second electrode, and the active layer constitute a thin-film transistor. The transparent electrode layer 700 may be a pixel electrode layer or a common electrode layer. When the source / drain metal layer 600 includes overlapping conductive lines 400, the vertical distance between the overlapping conductive lines 400 and the clock signal line 300 is the thickness of the gate insulating layer 800; when the transparent electrode layer 700 includes overlapping conductive lines 400, the vertical distance between the overlapping conductive lines 400 and the clock signal line 300 is the sum of the thicknesses of the gate insulating layer 800 and the source / drain insulating layer 900.

[0046] Optionally, the transparent electrode layer 700 can be made of ITO.

[0047] It should be noted that the array substrate in the embodiments of this application can be a bottom gate array substrate, a top gate array substrate, a dual gate array substrate (i.e., including a bottom gate and a top gate), or any combination of the above three structures.

[0048] In this embodiment, the overlapping conductive lines 400 can be fabricated using the original film structure of the array substrate (i.e., the source / drain metal layer 600 or the transparent electrode layer 700 mentioned above), thereby simplifying the fabrication process of the array substrate.

[0049] In one embodiment, when the source / drain metal layer 600 includes overlapping conductive lines 400, the overlap area of ​​the orthographic projection of the overlapping conductive lines 400 on the substrate 100 and the orthographic projection of the plurality of clock signal lines 300 on the substrate 100 is S1; when the transparent electrode layer 700 includes overlapping conductive lines 400, the overlap area of ​​the orthographic projection of the overlapping conductive lines 400 on the substrate 100 and the orthographic projection of the plurality of clock signal lines 300 on the substrate 100 is S2; wherein, S1 < S2.

[0050] For example, when the source / drain metal layer 600 includes overlapping conductive lines 400, the vertical distance D1 between the overlapping conductive lines 400 and the clock signal line 300 is the thickness of the gate insulating layer 800; when the transparent electrode layer 700 includes overlapping conductive lines 400, the vertical distance D2 between the overlapping conductive lines 400 and the clock signal line 300 is the sum of the thicknesses of the gate insulating layer 800 and the source / drain insulating layer 900, therefore D2 is greater than D1. The larger the vertical distance between the overlapping conductive lines 400 and the clock signal line 300, the smaller the overlapping capacitance formed between the overlapping conductive lines 400 and the clock signal line 300. When the source / drain metal layer 600 includes overlapping conductive lines 400, the overlapping capacitance formed between the overlapping conductive lines 400 and the clock signal line 300 is C1; when the transparent electrode layer 700 includes overlapping conductive lines 400, the overlapping capacitance formed between the overlapping conductive lines 400 and the clock signal line 300 is C2. If S1 = S2, then C1 > C2.

[0051] Therefore, by making S1 < S2, when the vertical distance between the overlapping conductive line 400 and the clock signal line 300 is large, the overlapping capacitance between the overlapping conductive line 400 and the clock signal line 300 can be increased, thereby improving the suppression effect of the overlapping capacitance on the coupling difference between the clock signal lines 300.

[0052] Figure 5 A schematic diagram of a clock signal line 300, a DC signal line 1000, and overlapping conductive lines 400 according to a first embodiment of this application is shown. In one embodiment, as Figure 4 and Figure 5 As shown, the array substrate also includes a DC signal line 1000, which is disposed on the same layer as multiple clock signal lines 300. It is used to input the DC signal from the DC signal source into the shift register unit. The orthographic projection of the DC signal line 1000 on the substrate 100 overlaps with the orthographic projection of the overlapping conductive lines 400 on the substrate 100. For example, the DC signal line 1000 can be a low-level signal line. The DC signal line 1000 can be disposed on one side of the multiple clock signal lines 300, and the extension direction of the DC signal line 1000 can be the same as the extension direction of each clock signal line 300.

[0053] In this embodiment, since the DC signal line 1000 can stably input a DC signal through a DC signal source, and by making the orthographic projection of the DC signal line 1000 on the substrate 100 and the orthographic projection of the overlapping conductive line 400 on the substrate 100 have an overlapping area, an overlapping capacitance can also be generated between the DC signal line 1000 and the overlapping conductive line 400. Thus, the coupling difference between the clock signal lines 300 can be suppressed more effectively by using the DC signal, thereby improving the display effect.

[0054] Figure 6 A schematic diagram of a clock signal line 300, a DC signal line 1000, and overlapping conductive lines 400 according to a second embodiment of this application is shown. In one embodiment, refer to... Figure 4 and Figure 6 The array substrate also includes a DC signal line 1000, which is disposed on the same layer as multiple clock signal lines 300. At least one insulating layer is disposed between the DC signal line 1000 and the overlapping conductive lines 400. Each insulating layer has a via formed thereon, and the DC signal line 1000 is electrically connected to the overlapping conductive lines 400 through the via.

[0055] For example, the DC signal line 1000 can be used to input a DC signal from a DC signal source into a shift register unit; or, the DC signal line 1000 can be used to output a DC signal from the shift register unit. When the source / drain metal layer 600 includes overlapping conductive lines 400, the insulating layer between the DC signal line 1000 and the overlapping conductive lines 400 is a gate insulating layer 800, and the DC signal line 1000 is electrically connected to the overlapping conductive lines 400 through vias on the gate insulating layer 800. When the transparent electrode layer 700 includes overlapping conductive lines 400, the insulating layer between the DC signal line 1000 and the overlapping conductive lines 400 is a gate insulating layer 800 and a source / drain insulating layer 900, and the DC signal line 1000 is electrically connected to the overlapping conductive lines 400 through vias on the gate insulating layer 800 and vias on the source / drain insulating layer 900.

[0056] In this embodiment, the overlapping conductive line 400 can be electrically connected to the DC signal line 1000, so that the overlapping conductive line 400 can stably input a DC signal through a DC signal source. In this way, the stable DC signal can more effectively suppress the coupling difference between the clock signal lines 300 and improve the display effect.

[0057] In one implementation, such as Figure 5 As shown, multiple clock signal lines 300 are arranged at intervals along a first direction, and each clock signal line 300 extends along a second direction perpendicular to the first direction; overlapping conductive lines 400 extend along the first direction. For example, in... Figure 5In the diagram, the first direction is left-right, and the second direction is up-down. The array substrate also includes DC signal lines 1000 extending along the second direction, and overlapping conductive lines 400 are perpendicular to both the DC signal lines 1000 and each clock signal line 300. The orthographic projection of the overlapping conductive lines 400 on the substrate 100 may or may not overlap with the orthographic projection of the DC signal lines 1000 on the substrate 100.

[0058] In this embodiment, the overlapping conductive lines 400 are perpendicular to each clock signal line 300. While ensuring that the orthographic projection of the overlapping conductive lines 400 on the substrate 100 overlaps with the orthographic projection of each clock signal line 300 on the substrate 100, the length of the overlapping conductive lines 400 is relatively short and the structure is simple, which is beneficial to reducing the cost of the array substrate.

[0059] Figure 7 A schematic diagram of a clock signal line 300, a DC signal line 1000, and overlapping conductive lines 400 according to a third embodiment of this application is shown. In one embodiment, as Figure 7 As shown, multiple clock signal lines 300 are arranged at intervals along a first direction, and each clock signal line 300 extends along a second direction perpendicular to the first direction; the extension direction of the overlapping conductive lines 400 is inclined relative to both the first and second directions, that is, the extension direction of the overlapping conductive lines 400 is neither parallel to the first direction nor parallel to the second direction. For example, in Figure 7 In the example, the first direction is left-right, and the second direction is up-down. In the left-to-right direction, the overlapping conductive lines 400 gradually slope downwards. The array substrate also includes DC signal lines 1000 extending along the second direction. The orthographic projections of the overlapping conductive lines 400 onto the substrate 100 and the orthographic projections of the DC signal lines 1000 onto the substrate 100 may or may not overlap.

[0060] In this embodiment, the overlapping conductive lines 400 are inclined relative to the clock signal lines 300. The structure of the overlapping conductive lines 400 is also simple, and the arrangement of the overlapping conductive lines 400 in this way is less difficult, thereby improving the overall fabrication efficiency of the array substrate.

[0061] Figure 8 A schematic diagram of a clock signal line 300, a DC signal line 1000, and overlapping conductive lines 400 according to a fourth embodiment of this application is shown. In one embodiment, combined with Figure 8Multiple clock signal lines 300 are arranged at intervals along a first direction, and each clock signal line 300 extends along a second direction perpendicular to the first direction; the overlapping conductive line 400 includes a first connecting segment 410, a second connecting segment 420 and a third connecting segment 430, the extension directions of the first connecting segment 410 and the third connecting segment 430 are parallel to the first direction, the second connecting segment 420 is connected between the first connecting segment 410 and the third connecting segment 430, and the extension direction of the second connecting segment 420 is parallel to the second direction.

[0062] For example, Figure 8 In the middle, the first direction is left and right, and the second direction is up and down. Figure 8 The diagram shows eight clock signal lines 300, and the array substrate also includes DC signal lines 1000 extending along the second direction. For ease of description, the eight clock signal lines 300 will be referred to from left to right as "first clock signal line 300", "second clock signal line 300"... "eighth clock signal line 300". The overlapping conductive lines 400 are formed in a "Z" shape. The orthographic projection of the first connecting segment 410 on the substrate 100 overlaps with the orthographic projections of the first clock signal lines 300 to the fourth clock signal lines 300 on the substrate 100. The orthographic projection of the second connecting segment 420 on the substrate 100 overlaps with the orthographic projections of the fourth clock signal line 300 and the fifth clock signal line 300 on the substrate 100. The orthographic projection of the third connection segment 430 on the substrate 100 overlaps with the orthographic projections of the fifth clock signal line 300 to the eighth clock signal line 300 on the substrate 100, and the orthographic projection of the third connection segment 430 on the substrate 100 overlaps with the orthographic projection of the DC signal line 1000 on the substrate 100.

[0063] In this embodiment, the overlapping conductive line 400 forms overlapping capacitance with each clock signal line 300 to avoid horizontal stripes, while effectively avoiding the connection line between the clock signal line 300 and the shift register unit, which facilitates routing.

[0064] Figure 9 A schematic diagram of a clock signal line 300, a DC signal line 1000, and overlapping conductive lines 400 according to a fifth embodiment of this application is shown. In one embodiment, as Figure 9As shown, multiple clock signal lines 300 are arranged at intervals along a first direction, and each clock signal line 300 extends along a second direction perpendicular to the first direction; the overlapping conductive lines 400 include a fourth connecting segment 440, a fifth connecting segment 450, a sixth connecting segment 460, a seventh connecting segment 470, and an eighth connecting segment 480. The fifth connecting segment 450 is connected between one end of the sixth connecting segment 460 and the fourth connecting segment 440, and the seventh connecting segment 470 is connected between the other end of the sixth connecting segment 460 and the eighth connecting segment 480; wherein, the fourth connecting segment 440, the sixth connecting segment 460, and the eighth connecting segment 480 all extend along the first direction, and the fifth connecting segment 450 and the seventh connecting segment 470 all extend along the second direction.

[0065] For example, Figure 9 In the diagram, the first direction is left-right, and the second direction is up-down. The overlapping conductive lines 400 are formed in a "U" shape. The orthographic projection of the fourth connecting segment 440 on the substrate 100 overlaps with the orthographic projections of the first clock signal line 300 and the second clock signal line 300 on the substrate 100. The orthographic projection of the fifth connecting segment 450 on the substrate 100 overlaps with the orthographic projections of the second clock signal line 300 and the third clock signal line 300 on the substrate 100. The orthographic projection of the sixth connecting segment 460 on the substrate 100 overlaps with the orthographic projections of the third to sixth clock signal lines 300 on the substrate 100. The orthographic projection of the seventh connecting segment 470 on the substrate 100 overlaps with the orthographic projections of the sixth and seventh clock signal lines 300 on the substrate 100. The orthographic projection of the eighth connection segment 480 on the substrate 100 overlaps with the orthographic projections of the seventh clock signal line 300, the eighth clock signal line 300, and the DC signal line 1000 on the substrate 100.

[0066] In this embodiment, the overlapping conductive lines 400 can also form overlapping capacitances with each clock signal line 300, thereby avoiding the generation of horizontal stripes. At the same time, the overlapping conductive lines 400 configured in this way can also avoid the connection lines between the clock signal lines 300 and the shift register unit, thereby facilitating the routing.

[0067] The display panel according to the second aspect of this application includes an array substrate according to any embodiment of the first aspect of this application.

[0068] According to the display panel of the present application embodiment, by adopting the above-mentioned array substrate, the clock signal waveforms output by multiple clock signal lines 300 to the shift register unit are consistent, thereby avoiding charging differences, avoiding the generation of horizontal stripes, and effectively improving the display effect.

[0069] The display device according to a third aspect of this application includes the aforementioned display panel. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0070] The display device according to the embodiments of this application, by employing the above-described display panel, can avoid the generation of horizontal stripes, thereby improving display quality and yield.

[0071] Other configurations of the array substrate, display panel, and display device in the above embodiments can be derived from various technical solutions now and in the future known to those skilled in the art, and will not be described in detail here.

[0072] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0073] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.

[0074] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0075] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0076] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0077] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: Substrate; Multiple shift register units are disposed on one side of the substrate; Multiple clock signal lines are disposed on the same side of the substrate as the shift register units. The multiple clock signal lines are configured in one-to-one correspondence with the multiple shift register units. Each clock signal line is used to input the clock signal from the clock signal source into the corresponding shift register unit. Overlapping conductive lines are disposed on the side of the clock signal lines away from the substrate. The orthographic projection of the overlapping conductive lines on the substrate and the orthographic projection of each clock signal line on the substrate both have overlapping areas, so as to form overlapping capacitance with each clock signal line. The clock signal line has a first end and a second end, the first end being connected to the clock signal source and the second end being located away from the clock signal source; the minimum distance between the overlapping conductive line and the first end of the clock signal line is greater than the minimum distance between the overlapping conductive line and the second end of the clock signal line.

2. The array substrate according to claim 1, characterized in that, The ratio of the width of the overlapping conductive lines to the width of each clock signal line is 0.5 to 2.

3. The array substrate according to claim 1, characterized in that, Also includes: A gate metal layer is disposed on one side of the substrate, and the gate metal layer includes the plurality of clock signal lines; A source / drain metal layer is disposed on the side of the gate metal layer opposite to the substrate; A transparent electrode layer is disposed on the side of the gate metal layer opposite to the substrate; Wherein, the source / drain metal layer includes the overlapping conductive lines; or, the transparent electrode layer includes the overlapping conductive lines.

4. The array substrate according to claim 3, characterized in that, When the source / drain metal layer includes the overlapping conductive lines, the overlapping area of ​​the orthographic projection of the overlapping conductive lines on the substrate and the orthographic projection of the plurality of clock signal lines on the substrate is S1; when the transparent electrode layer includes the overlapping conductive lines, the overlapping area of ​​the orthographic projection of the overlapping conductive lines on the substrate and the orthographic projection of the plurality of clock signal lines on the substrate is S2; wherein, S1 < S2.

5. The array substrate according to claim 1, characterized in that, Also includes: A DC signal line, disposed on the same layer as the multiple clock signal lines, is used to input the DC signal from the DC signal source into the shift register unit. The orthographic projection of the DC signal line on the substrate and the orthographic projection of the overlapping conductive line on the substrate have an overlapping area.

6. The array substrate according to claim 1, characterized in that, Also includes: A DC signal line is disposed on the same layer as the plurality of clock signal lines. At least one insulating layer is disposed between the DC signal line and the overlapping conductive lines. A via is formed on each of the insulating layers. The DC signal line is electrically connected to the overlapping conductive lines through the via.

7. The array substrate according to any one of claims 1-6, characterized in that, The plurality of clock signal lines are arranged at intervals along a first direction, and each of the clock signal lines extends along a second direction perpendicular to the first direction; the overlapping conductive lines extend along the first direction.

8. The array substrate according to any one of claims 1-6, characterized in that, The plurality of clock signal lines are arranged at intervals along a first direction, and each clock signal line extends along a second direction perpendicular to the first direction; the extension direction of the overlapping conductive lines is inclined relative to both the first direction and the second direction.

9. The array substrate according to any one of claims 1-6, characterized in that, The plurality of clock signal lines are arranged at intervals along a first direction, and each clock signal line extends along a second direction perpendicular to the first direction; the overlapping conductive line includes a first connecting segment, a second connecting segment and a third connecting segment, the extension directions of the first connecting segment and the third connecting segment are parallel to the first direction, the second connecting segment is connected between the first connecting segment and the third connecting segment, and the extension direction of the second connecting segment is parallel to the second direction.

10. The array substrate according to any one of claims 1-6, characterized in that, The plurality of clock signal lines are arranged at intervals along a first direction, and each clock signal line extends along a second direction perpendicular to the first direction; the overlapping conductive lines include a fourth connecting segment, a fifth connecting segment, a sixth connecting segment, a seventh connecting segment, and an eighth connecting segment, wherein the fifth connecting segment is connected between one end of the sixth connecting segment and the fourth connecting segment, and the seventh connecting segment is connected between the other end of the sixth connecting segment and the eighth connecting segment; wherein the fourth connecting segment, the sixth connecting segment, and the eighth connecting segment all extend along the first direction, and the fifth connecting segment and the seventh connecting segment all extend along the second direction.

11. A display panel, characterized in that, Includes the array substrate according to any one of claims 1-10.

12. A display device, characterized in that, Includes the display panel as described in claim 11.

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