Novel embedded signal processing system and method

Abstract

The invention relates to a novel embedded signal processing system and method. The system comprises a debugging unit, a communication interface unit, a DSP (Digital Signal Processor) array calculation unit, a control unit, a data storage unit and a data interface unit which are integrated on a PCB (Printed Circuit Board) hardware board card, the debugging unit is used for realizing serial port debugging of the system and accessing and inputting related function instructions; the data interface unit is used for acquiring external signal data of the system and converting the external signal data into an internal digital signal; the DSP array calculation unit is used for realizing deployment of a signal processing algorithm, scheduling of calculation tasks and summarization and transmission of data results; the control unit is used for realizing system computing resource scheduling; the communication interface unit is used for acquiring signal processing data from the control unit and then converting the signal processing data into data frames for external transmission; and the data storage unit is used for writing, reading and maintaining the signal processing data of the control unit. The system can improve the calculation precision and reduce the calculation time consumption.

Description

Technical Field

[0001] The present application relates to the field of embedded technology, and in particular to a novel embedded signal processing system and method. Background Art

[0002] With the rapid development of information technology, the demand for digital signal processing capabilities in application scenarios such as satellite navigation, aerospace, radar communications, and underwater acoustic detection has increased exponentially. Improving the accelerated computing capabilities of embedded signal processing systems for large-scale signal data has become an important research direction in the field of signal processing technology.

[0003] At present, common embedded signal processing systems use scalar operations to convert vector data in complex signal processing algorithms into scalar data before centralized processing. The software algorithm uses a circular polling method to access data sets. This method calls the calculation instructions of the DSP processor multiple times, resulting in performance bottlenecks such as excessive time complexity and space complexity indicators, long calculation time, and low calculation accuracy when running signal processing software algorithms in embedded systems. The current embedded signal processing systems have been unable to adapt to the adaptation and iteration of signal processing algorithms in complex application scenarios. Summary of the invention

[0004] Based on this, it is necessary to provide a new embedded signal processing system and method that can improve calculation accuracy and reduce calculation time to address the above technical problems.

[0005] A novel embedded signal processing system, the system includes a debugging unit, a communication interface unit, a DSP array calculation unit, a control unit, a data storage unit, a power supply unit and a data interface unit concentrated on a PCB hardware board;

[0006] The debugging unit is used to implement serial port debugging of the system and access input related function instructions;

[0007] The data interface unit is used to realize the data acquisition of external signals of the system and convert the external signal data into internal digital signals;

[0008] The DSP array computing unit is used for the software / hardware interface connection of the debugging unit, data interface unit, control unit, and communication interface unit, the implementation of the underlying driver function and the deployment of the signal processing algorithm, the scheduling of computing tasks, and the aggregation and transmission of data results;

[0009] The control unit is responsible for responding to external control commands and implementing system computing resource scheduling;

[0010] The communication interface unit is used to obtain signal processing data from the control unit and convert it into data frames for external transmission;

[0011] The data storage unit is used to write, read and maintain the signal processing data and system log of the control unit;

[0012] The power supply unit is used to realize the power supply of the embedded signal processing system.

[0013] In one embodiment, the back end of the debugging unit is connected to the front end of the DSP array computing unit; the data interface unit is connected to the side end of the DSP array computing unit; the front end of the control unit is connected to the tail end of the DSP array computing unit; the side end of the control unit is connected to the communication interface unit; and the tail end of the control unit is connected to the data storage unit.

[0014] In one embodiment, the communication interface unit is a board-level or system-level communication interface, including: an RS422 interface, an ARINC429 interface, a CAN interface, and a Gigabit / 100M Ethernet interface.

[0015] In one embodiment, the DSP array computing unit is composed of four FT-M7004V multi-core processors based on the Matrix architecture, each of which contains four DSP computing cores CORE0 to CORE4; the DSP array computing unit includes 16 DSP cores for completing accelerated calculations of signal data; the 16 DSP cores include CORE0 to CORE15.

[0016] In one of the embodiments, the DSP array computing unit is also used to perform data load balancing processing, data vector processing, data parallel computing processing and data result transmission processing on the internal digital signal to obtain the signal processing result; the process of data load balancing processing includes the main core CORE0 of DSP0 in the DSP array computing unit distributing the internal digital signal to the main core CORE4 of DSP1, the main core CORE8 of DSP2 and the main core CORE12 of DSP3 through SRIO, the control unit scheduling the main core of each DSP according to the load balancing processing method to distribute the large capacity data to the DSP computing core evenly, and each DSP in the DSP array computing unit realizes data load balancing scheduling and management through independent data receiving tasks, data sending tasks and inter-core communication tasks; the process of data vector processing includes each computing core in the DSP array computing unit caching the received vector data into its private VPE vector processing storage unit, Scalar data is cached in the public SPE scalar storage unit on the chip for classification processing of signal data. The VPE vector storage unit is responsible for the calculation and management of VECTOR vector data in the signal processing algorithm, and the SPE scalar storage unit is responsible for the calculation and management of scalar data in the software control process. The process of data parallel computing processing includes that after the DSP array computing unit completes data allocation, it calls the SIMD instruction set according to the deployed signal processing software algorithm to implement parallel computing processing, and then caches the calculation results of each DSP in the signal processing cycle into the DDR specified memory space. The data result transmission processing includes that each DSP core in the DSP array computing unit summarizes the processing results to the DDR space of the DSP0 main core CORE0 for temporary storage, and then the control unit collects the signal processing results from CORE0. CORE0 in the DSP array computing unit realizes signal processing data transmission through independent data aggregation receiving tasks and data communication tasks.

[0017] In one embodiment, the DSP array unit is further used to receive query instructions, signal data to be processed and control commands from the debugging unit, the data interface unit and the control unit.

[0018] In one of the embodiments, the DSP array unit is further used to transmit the status query result, the signal processing result and the signal data to be stored to the debugging unit, the data interface unit and the control unit respectively.

[0019] In one embodiment, the data storage unit is a storage carrier including an SD card and an mSATA electronic disk.

[0020] A novel embedded signal processing method, characterized in that the method comprises:

[0021] After the power supply unit is powered on, it is started through the control unit and the system startup parameters are read from the data storage unit. The system startup parameters are respectively passed to the main core CORE0 of DSP0, the main core CORE4 of DSP1, the main core CORE8 of DSP2, and the main core CORE12 of DSP3 in the DSP array computing unit for parameter parsing. After the parsing is completed, the system initializes the debugging unit, the data interface unit, and the communication interface unit and performs a system self-check, obtains the BIT information reported by each unit, and ensures that the debugging unit, the communication interface unit, the DSP array computing unit, the control unit, the data storage unit, the power supply unit, and the data interface unit are all in normal working state;

[0022] The data interface unit is used to collect external signal data of the system and convert the external signal data into internal digital signals. The internal digital signals are processed by data load balancing, data vector processing, data parallel computing processing and data result transmission processing according to the DSP array computing unit to obtain the signal processing results and summarize the signal processing results to CORE0. At the same time, the GPIO external interrupt connected to the control unit is triggered. After the control unit responds to the interrupt, the signal processing results are directly read from the DDR temporary space of the DSP array computing unit CORE0, and the data file storage operation is executed to the data storage unit. The communication interface unit obtains the signal processing data from the control unit and converts it into a data frame for external transmission.

[0023] The above-mentioned novel embedded signal processing system and method, the present application has a novel embedded signal processing system that integrates a debugging unit, a communication interface unit, a DSP array computing unit, a control unit, a data storage unit, a power supply unit and a data interface unit on a PCB hardware board, which has the advantages of high integration, strong signal processing capability, small size, low power consumption, etc., wherein the DSP array computing unit is mainly designed, and 4 FT-M7004V processors are used to realize array interconnection through the SRIO high-speed interface, and a data load balancing processing method is used to fully utilize the time slice resources of the two types of hardware units SPE and VPE in the DSP, and a data vector processing method is used to load the vector data to be processed into its VPE vector storage unit at one time, and the VECTOR vector calculation instruction is called to realize the accelerated calculation of the vector data, so that the system's scalar data processing and vector data processing maintain roughly the same calculation load, avoiding the phenomenon that some processing units of a certain DSP have too large calculation loads and some processing units are idle and waiting during calculation, thereby improving the calculation efficiency of the embedded signal processing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a framework diagram of a novel embedded signal processing system in one embodiment;

[0025] Figure 2is a flow chart of a novel embedded signal processing method in one embodiment;

[0026] Figure 3 A schematic diagram of data flow of a DSP array computing unit in one embodiment. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] In one embodiment, Figure 1 As shown, a novel embedded signal processing system is provided, including a debugging unit 1, a communication interface unit 2, a DSP array calculation unit 3, a control unit 4, a data storage unit 5, a power supply unit 6 and a data interface unit 7 which are concentrated on a PCB hardware board;

[0029] The debugging unit 1 is used to implement the serial port debugging of the system and access and input related function instructions;

[0030] The data interface unit 7 is used to collect external signal data of the system and convert the external signal data into internal digital signals;

[0031] The DSP array computing unit 3 is used for the connection of the software / hardware interfaces of the debugging unit 1, the data interface unit 7, the control unit 4, and the communication interface unit 2, the realization of the underlying driver functions and the deployment of the signal processing algorithm, the scheduling of the computing tasks, and the aggregation and transmission of the data results;

[0032] The control unit 4 is responsible for responding to external control commands and implementing system computing resource scheduling;

[0033] The communication interface unit 2 is used to obtain signal processing data from the control unit and convert it into data frames for external transmission;

[0034] The data storage unit 5 is used to write, read and maintain the signal processing data and system log of the control unit;

[0035] The power supply unit 6 is used to realize power supply of the embedded signal processing system.

[0036] In the above-mentioned novel embedded signal processing system, after the novel embedded signal processing system is powered on by the power supply unit 6, the control unit 4 starts and reads the system startup parameters from the data storage unit 5, and passes them to the main core CORE0 of DSP0, the main core CORE4 of DSP1, the main core CORE8 of DSP2, and the main core CORE12 of DSP3 in the DSP array computing unit 3 for parameter parsing. After the parsing is completed, the system initializes the debugging unit 1, the data interface unit 7, and the communication interface unit 2, and then starts the system self-check to obtain the BIT information reported by each unit to ensure that the debugging unit 1, the communication interface unit 2, the DSP array computing unit 3, the control unit 4, the data storage unit 5, the power supply unit 6, and the data interface unit 7 are all in normal working state; during the operation of the embedded signal processing system, the DSP array computing unit 3 can directly or indirectly receive the parameter setting instructions from the debugging unit 1 or the control unit 4, and write the new parameters into the data storage unit 5 through the control unit 4 to complete the erasure and overwriting of the old parameters. During the entire data processing process, the debugging unit 1 backend is interconnected with the DSP array computing unit 3 frontend. The debugging unit 1 has an RS232 serial port debugging function, which is a software debugging window. The operator inputs specific Shell instructions through the serial port to realize system human-computer interaction, startup parameter management, self-test result management, software version number management, operation status query, signal processing result query and other functions. The operator sends a signal processing instruction through the debugging unit 1, and then performs high-speed acquisition and conversion of external analog signals of the embedded signal processing system to internal digital signals through the data interface unit 7, and sends the converted signal data to the DSP array computing unit 3. The DSP array computing unit 3DSP0 The main core CORE0 distributes the converted signal data collected by the data interface unit 7 to the main core CORE4 of DSP1, the main core CORE8 of DSP2 and the main core CORE12 of DSP3 through SRIO. The control unit 4 schedules the main core of each DSP to distribute the large-capacity data evenly to the DSP computing core according to the load balancing processing method; each DSP in the DSP array computing unit 3 realizes data load balancing scheduling and management through independent data receiving tasks, data sending tasks, and inter-core communication tasks, so as to avoid the phenomenon that some processing units of a certain DSP are overloaded and some processing units are idle during calculation, thereby improving the computing efficiency of the embedded signal processing system.In the process of data vector processing, each computing core in the DSP array computing unit 3 caches the received vector data into its private VPE vector processing storage unit, and caches the scalar data into the public SPE scalar storage unit on the chip, and performs classification processing of signal data. The VPE vector storage unit is responsible for the calculation and management of VECTOR vector data in the signal processing algorithm, and the SPE scalar storage unit is responsible for the calculation and management of scalar data in the software control process, wherein the vector data to be processed can be loaded into its VPE vector storage unit at one time, and the VECTOR vector calculation instruction is called to realize the accelerated calculation of vector data. At the same time, after the DSP array computing unit 3 completes the data allocation, it calls the SIMD instruction set according to the deployed signal processing software algorithm to realize parallel computing processing. Using the SIMD method, a single DSP computing instruction can execute the calculation of multiple data sets in parallel, and one computing instruction can complete the processing of multiple groups of signal data. This method not only reduces the number of computing instructions of the embedded signal processing system, reduces the time consumption, but also reduces the number of cycles in the calculation process, and accelerates the signal processing calculation process.

[0037] Each DSP core in the DSP array computing unit 3 summarizes the processing results to the DDR space of the DSP0 main core CORE0 for temporary storage, and then the control unit 4 collects the signal processing results from CORE0; CORE0 in the DSP array computing unit 3 realizes signal processing data transmission through independent data summary receiving tasks and data communication tasks. The control unit 4 adopts the solution of mounting a large-capacity storage device on an embedded microprocessor, and realizes the storage, recording and playback of signal data through the file system, which is convenient for tracing and simulation research on the calculation data during the signal processing process, reduces the use cost, and improves the operability of the system. The communication interface unit 2 receives the signal processing data in the control unit 4 and converts it into a data frame for external transmission. If each core of the DSP array computing unit 3 completes the parallel calculation and summarizes the results to CORE0, and triggers the GPIO external interrupt connected to the control unit 4 at the same time, the control unit 4 responds to the interrupt and directly reads the signal processing results from the DDR temporary space of the DSP array computing unit 3 CORE0 to perform the data file storage operation; the control unit 4 and the storage module realize data storage management through the file system read and write tasks.

[0038] In one embodiment, the back end of the debugging unit is connected to the front end of the DSP array computing unit; the data interface unit is connected to the side end of the DSP array computing unit; the front end of the control unit is connected to the tail end of the DSP array computing unit; the side end of the control unit is connected to the communication interface unit; and the tail end of the control unit is connected to the data storage unit.

[0039] In one embodiment, the communication interface unit is a board-level or system-level communication interface, including: an RS422 interface, an ARINC429 interface, a CAN interface, and a Gigabit / 100M Ethernet interface.

[0040] In a specific embodiment, the communication interface unit is a medium for transmitting system signal processing results, status feedback, control instructions, and receiving and sending data to be stored. The communication interface unit realizes the two-way transmission function of internal and external data. Depending on the specific application scenario, the communication interface unit can be a board-level or system-level communication interface such as an RS422 interface, an ARINC429 interface, a CAN interface, a Gigabit / 100M Ethernet interface, etc.

[0041] In one embodiment, the DSP array computing unit is composed of four FT-M7004V multi-core processors based on the Matrix architecture, each of which contains four DSP computing cores CORE0 to CORE4; the DSP array computing unit includes 16 DSP cores for completing accelerated calculations of signal data; the 16 DSP cores include CORE0 to CORE15.

[0042] In one of the embodiments, the DSP array computing unit is also used to perform data load balancing processing, data vector processing, data parallel computing processing and data result transmission processing on the internal digital signal to obtain the signal processing result; the process of data load balancing processing includes the main core CORE0 of DSP0 in the DSP array computing unit distributing the internal digital signal to the main core CORE4 of DSP1, the main core CORE8 of DSP2 and the main core CORE12 of DSP3 through SRIO, the control unit scheduling the main core of each DSP according to the load balancing processing method to distribute the large capacity data to the DSP computing core evenly, and each DSP in the DSP array computing unit realizes data load balancing scheduling and management through independent data receiving tasks, data sending tasks and inter-core communication tasks; the process of data vector processing includes each computing core in the DSP array computing unit caching the received vector data into its private VPE vector processing storage unit, Scalar data is cached in the public SPE scalar storage unit on the chip for classification processing of signal data. The VPE vector storage unit is responsible for the calculation and management of VECTOR vector data in the signal processing algorithm, and the SPE scalar storage unit is responsible for the calculation and management of scalar data in the software control process. The process of data parallel computing includes that after the DSP array computing unit completes data allocation, it calls the SIMD instruction set according to the deployed signal processing software algorithm to realize parallel computing processing and caches the calculation results of each DSP in the signal processing cycle into the DDR specified memory space. The data result transmission processing includes that each DSP core in the DSP array computing unit summarizes the processing results to the DDR space of the DSP0 main core CORE0 for temporary storage, and then the control unit collects the signal processing results from CORE0. CORE0 in the DSP array computing unit realizes signal processing data transmission through independent data aggregation receiving tasks and data communication tasks.

[0043] In one embodiment, the DSP array unit is also used to receive query instructions, signal data to be processed and control commands from the debugging unit 1, the data interface unit and the control unit.

[0044] In one of the embodiments, the DSP array unit is also used to transmit the status query result, the signal processing result and the signal data to be stored to the debugging unit 1, the data interface unit and the control unit respectively.

[0045] In a specific embodiment, the DSP array computing unit and the control unit can be connected through a board-level PCIe bus, SRIO bus or EMIF bus according to different application scenarios.

[0046] In one embodiment, the data storage unit is a storage carrier including an SD card and an mSATA electronic disk.

[0047] In a specific embodiment, the EMMC protocol bus or the mSATA protocol bus can be used between the front end of the data storage unit and the control unit according to different application scenarios; the data storage unit can be a storage carrier such as an SD card, an mSATA electronic disk, etc. according to different application environments.

[0048] In one of the embodiments, the control unit backend is interconnected with the data storage unit frontend, has a file system management function, is mainly responsible for the management of data files, and implements operations such as reading and writing, file access, etc. of the data storage unit.

[0049] In one of the embodiments, the control unit is connected to the communication interface unit and is mainly responsible for responding to external control commands and realizing system computing resource scheduling; wherein the microprocessor used by the control unit adopts a Zynq Soc embedded processor chip.

[0050] In one embodiment, a novel embedded signal processing method includes:

[0051] After the power supply unit is powered on, it is started through the control unit and the system startup parameters are read from the data storage unit. The system startup parameters are respectively passed to the main core CORE0 of DSP0, the main core CORE4 of DSP1, the main core CORE8 of DSP2, and the main core CORE12 of DSP3 in the DSP array computing unit for parameter parsing. After the parsing is completed, the system initializes the debugging unit 1, the data interface unit and the communication interface unit and performs a system self-check, obtains the BIT information reported by each unit, and ensures that the debugging unit 1, the communication interface unit, the DSP array computing unit, the control unit, the data storage unit, the power supply unit, and the data interface unit are all in normal working state;

[0052] The data interface unit is used to collect external signal data of the system and convert the external signal data into internal digital signals. The internal digital signals are processed by data load balancing, data vector processing, data parallel computing processing and data result transmission processing according to the DSP array computing unit to obtain the signal processing results and summarize the signal processing results to CORE0. At the same time, the GPIO external interrupt connected to the control unit is triggered. After the control unit responds to the interrupt, the signal processing results are directly read from the DDR temporary space of the DSP array computing unit CORE0, and the data file storage operation is executed to the data storage unit. The communication interface unit obtains the signal processing data from the control unit and converts it into a data frame for external transmission.

[0053] In a specific embodiment, Figure 2 As shown, the following steps are included:

[0054] P1: System configuration parameter processing

[0055] System configuration parameter processing includes two operations: reading and setting system startup parameters. The specific process is as follows:

[0056] After the embedded signal processing system power supply unit is powered on, the control unit starts and reads the system startup parameters from the data storage unit, and passes them to the main core CORE0 of DSP0, the main core CORE4 of DSP1, the main core CORE8 of DSP2, and the main core CORE12 of DSP3 in the DSP array computing unit for parameter parsing. After the parsing is completed, the system initializes the debugging unit 1, the data interface unit, and the communication interface unit, and then starts the system self-check to obtain the BIT information reported by each unit to ensure that the debugging unit 1, the communication interface unit, the DSP array computing unit, the control unit, the data storage unit, the power supply unit, and the data interface unit are all in normal working state;

[0057] During the operation of the embedded signal processing system, the DSP array computing unit can directly or indirectly receive parameter setting instructions from the debugging unit 1 or the control unit, and write new parameters into the data storage unit through the control unit to complete the erasure and overwriting of old parameters.

[0058] P2: Communication interface processing

[0059] The communication interface unit is the information interaction interface between the embedded signal processing system and external devices. The main processing flow is as follows:

[0060] The DSP array computing unit parses the communication frame through the communication interface unit to obtain the control command and the log information to be stored.

[0061] The communication interface unit provides an upgrade interface for the DSP array computing unit and the control unit software, realizing the online upgrade function of the software.

[0062] P3: Data interface processing

[0063] Stable data transmission is carried out between the data interface unit and the DSP array computing unit, realizing high-speed acquisition and conversion of external analog signals to internal digital signals of the embedded signal processing system.

[0064] P4: Data load balancing processing

[0065] like Figure 3 As shown, the main core CORE0 of the DSP array computing unit DSP0 distributes the signal data to be processed collected by the data interface unit to the main core CORE4 of DSP1, the main core CORE8 of DSP2 and the main core CORE12 of DSP3 through SRIO. The control unit schedules the main core of each DSP to distribute the large-capacity data evenly to the DSP computing core according to the load balancing processing method.

[0066] Each DSP in the DSP array computing unit implements data load balancing scheduling and management through independent data receiving tasks, data sending tasks, and inter-core communication tasks.

[0067] P5: Data vector processing

[0068] Each computing core in the DSP array computing unit caches the received vector data into its private VPE vector processing storage unit, and caches the scalar data into the public SPE scalar storage unit on the chip to perform classification processing of the signal data. The VPE vector storage unit is responsible for the calculation and management of VECTOR vector data in the signal processing algorithm, and the SPE scalar storage unit is responsible for the calculation and management of scalar data in the software control process.

[0069] P6: Data Parallel Computing Processing

[0070] After the DSP array computing unit completes data allocation, it calls the SIMD instruction set according to the deployed signal processing software algorithm to implement parallel computing processing.

[0071] After the DSP array computing unit completes signal processing, it caches the calculation results of each DSP within the signal processing cycle in a classified manner into the DDR specified memory space.

[0072] P7: Data result transmission and processing

[0073] Each DSP core in the DSP array computing unit aggregates the processing results to the DDR space of the DSP0 main core CORE0 for temporary storage, and then the control unit collects the signal processing results from CORE0;

[0074] CORE0 in the DSP array computing unit realizes signal processing data transmission through independent data aggregation receiving tasks and data communication tasks;

[0075] The communication interface unit receives the signal processing data from the control unit and converts it into data frames for external transmission.

[0076] P8: Data storage processing

[0077] After completing the parallel calculation, each core of the DSP array computing unit aggregates the results to CORE0 and triggers the GPIO external interrupt connected to the control unit. After the control unit responds to the interrupt, it directly reads the signal processing results from the DDR temporary space of the DSP array computing unit CORE0 and performs the data file storage operation.

[0078] The control unit and the storage module implement data storage management through file system read and write tasks.

[0079] In one embodiment, the process of data load balancing processing includes the main core CORE0 of DSP0 in the DSP array computing unit distributing the internal digital signal to the main core CORE4 of DSP1, the main core CORE8 of DSP2 and the main core CORE12 of DSP3 through SRIO, the control unit scheduling the main core of each DSP according to the load balancing processing method, and evenly distributing the large-capacity data to the DSP computing cores, and each DSP in the DSP array computing unit realizes data load balancing scheduling and management through independent data receiving tasks, data sending tasks, and inter-core communication tasks; the process of data vector processing includes each computing core in the DSP array computing unit caching the received vector data into its private VPE vector processing storage unit, and caching the scalar data into the public SPE scalar storage unit on the chip to perform classification processing of signal data. , the VPE vector storage unit is responsible for the calculation and management of VECTOR vector data in the signal processing algorithm, and the SPE scalar storage unit is responsible for the calculation and management of scalar data in the software control process; the process of data parallel computing includes that after the DSP array computing unit completes data allocation, it calls the SIMD instruction set according to the deployed signal processing software algorithm to implement parallel computing processing, and then caches the calculation results of each DSP in the signal processing cycle into the DDR specified memory space; the data result transmission processing includes that each DSP core in the DSP array computing unit summarizes the processing results to the DDR space of the DSP0 main core CORE0 for temporary storage, and then the control unit collects the signal processing results from CORE0; CORE0 in the DSP array computing unit realizes signal processing data transmission through independent data aggregation receiving tasks and data communication tasks.

[0080] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A novel embedded signal processing system, characterized in that: The system includes a debugging unit, a communication interface unit, a DSP array calculation unit, a control unit, a data storage unit, a power supply unit and a data interface unit which are concentrated on a PCB hardware board; The debugging unit is used to implement serial port debugging of the system and access input related function instructions; The data interface unit is used to collect system external signal data and convert the external signal data into internal digital signals; The DSP array computing unit is used for the software / hardware interface connection of the debugging unit, data interface unit, control unit, and communication interface unit, the implementation of the underlying driver function and the deployment of the signal processing algorithm, the scheduling of computing tasks, and the aggregation and transmission of data results; The control unit is responsible for responding to external control commands and implementing system computing resource scheduling; The communication interface unit is used to obtain signal processing data from the control unit and convert it into data frames for external transmission; The data storage unit is used to write, read and maintain the signal processing data and system log of the control unit; The power supply unit is used to realize power supply of the embedded signal processing system.

2. The system according to claim 1, characterized in that The back end of the debugging unit is connected to the front end of the DSP array computing unit; the data interface unit is connected to the side end of the DSP array computing unit; the front end of the control unit is connected to the tail end of the DSP array computing unit; the side end of the control unit is connected to the communication interface unit; and the tail end of the control unit is connected to the data storage unit.

3. The system according to claim 1, characterized in that The communication interface unit is a board-level or system-level communication interface, including: an RS422 interface, an ARINC429 interface, a CAN interface and a Gigabit / 100M Ethernet interface.

4. The system according to claim 1, characterized in that The DSP array computing unit is composed of 4 FT-M7004V multi-core processors based on the Matrix architecture, each FT-M7004V processor contains 4 DSP computing cores CORE0~CORE4; the DSP array computing unit includes 16 DSP cores for completing the accelerated calculation of signal data; the 16 DSP cores include CORE0~CORE15.

5. The system according to claim 4, characterized in that The DSP array computing unit is also used to perform data load balancing processing, data vector processing, data parallel computing processing and data result transmission processing on the internal digital signal to obtain a signal processing result; the process of the data load balancing processing includes the main core CORE0 of DSP0 in the DSP array computing unit distributing the internal digital signal to the main core CORE4 of DSP1, the main core CORE8 of DSP2 and the main core CORE12 of DSP3 through SRIO, the control unit scheduling the main core of each DSP according to the load balancing processing method to evenly distribute the large-capacity data to the DSP computing core, and each DSP in the DSP array computing unit realizes data load balancing scheduling and management through independent data receiving tasks, data sending tasks and inter-core communication tasks; the process of the data vector processing includes each computing core in the DSP array computing unit receiving the received data Vector data is cached in its private VPE vector processing storage unit, and scalar data is cached in the public SPE scalar storage unit on the chip for classification processing of signal data. The VPE vector storage unit is responsible for the calculation and management of VECTOR vector data in the signal processing algorithm, and the SPE scalar storage unit is responsible for the calculation and management of scalar data in the software control process; the process of data parallel computing processing includes that after the DSP array computing unit completes data allocation, the SIMD instruction set is called according to the deployed signal processing software algorithm to realize parallel computing processing and the calculation results of each DSP in the signal processing cycle are classified and cached in the DDR specified memory space; the data result transmission processing includes that each DSP core in the DSP array computing unit summarizes the processing results to the DDR space of the DSP0 main core CORE0 for temporary storage, and then the control unit collects the signal processing results from CORE0; CORE0 in the DSP array computing unit realizes signal processing data transmission through independent data aggregation receiving tasks and data communication tasks.

6. The system according to claim 1, characterized in that The DSP array unit is also used to receive query instructions, signal data to be processed and control commands from the debugging unit, the data interface unit and the control unit.

7. The system according to claim 1, characterized in that The DSP array unit is also used to return the status query result, signal processing result and signal data to be stored to the debugging unit, the data interface unit and the control unit respectively.

8. The system according to claim 1, characterized in that The data storage unit is a storage carrier, including an SD card and an mSATA electronic disk.

9. A novel embedded signal processing method, characterized in that: The method is applied to the novel embedded signal processing system according to any one of claims 1 to 8, and the method comprises: After the power supply unit is powered on, it is started through the control unit and the system startup parameters are read from the data storage unit. The system startup parameters are respectively passed to the main core CORE0 of DSP0, the main core CORE4 of DSP1, the main core CORE8 of DSP2, and the main core CORE12 of DSP3 in the DSP array computing unit for parameter parsing. After the parsing is completed, the system initializes the debugging unit, the data interface unit, and the communication interface unit and performs a system self-check, obtains the BIT information reported by each unit, and ensures that the debugging unit, the communication interface unit, the DSP array computing unit, the control unit, the data storage unit, the power supply unit, and the data interface unit are all in normal working state; The data interface unit is used to collect external signal data of the system and convert the external signal data into internal digital signals. The internal digital signals are subjected to data load balancing processing, data vector processing, data parallel computing processing and data result transmission processing according to the DSP array computing unit to obtain signal processing results and summarize the signal processing results to CORE0. Meanwhile, a GPIO external interrupt connected to the control unit is triggered. After the control unit responds to the interrupt, the signal processing results are directly read from the DDR temporary space of the DSP array computing unit CORE0, and a data file storage operation is performed to store the data in the data storage unit. The communication interface unit obtains the signal processing data from the control unit and converts it into a data frame for external transmission.

10. The method according to claim 9, characterized in that The process of data load balancing processing includes the main core CORE0 of DSP0 in the DSP array computing unit distributing the internal digital signal to the main core CORE4 of DSP1, the main core CORE8 of DSP2 and the main core CORE12 of DSP3 through SRIO, the control unit scheduling the main core of each DSP to distribute the large-capacity data to the DSP computing core evenly according to the load balancing processing method, and each DSP in the DSP array computing unit realizes data load balancing scheduling and management through independent data receiving tasks, data sending tasks, and inter-core communication tasks; the process of data vector processing includes each computing core in the DSP array computing unit caching the received vector data into its private VPE vector processing storage unit, and caching the scalar data into the on-chip public Some SPE scalar storage units perform classification processing of signal data, VPE vector storage units are responsible for the calculation and management of VECTOR vector data in signal processing algorithms, and SPE scalar storage units are responsible for the calculation and management of scalar data in software control processes; the process of data parallel computing processing includes that after the DSP array computing unit completes data allocation, the SIMD instruction set is called according to the deployed signal processing software algorithm to implement parallel computing processing and the calculation results of each DSP in the signal processing cycle are classified and cached in the DDR specified memory space; the data result transmission processing includes that each DSP core in the DSP array computing unit aggregates the processing results to the DDR space of the DSP0 main core CORE0 for temporary storage, and then the control unit collects the signal processing results from CORE0; CORE0 in the DSP array computing unit realizes signal processing data transmission through independent data aggregation receiving tasks and data communication tasks.

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