Low dropout regulator capable of switching output mode

Abstract

The invention belongs to the integrated circuit technology, and particularly relates to a low dropout regulator capable of switching output modes, which comprises an SET network, an EA network and a feedback network, and is characterized in that the EA network comprises a first error amplifier circuit, a second error amplifier circuit and a third error amplifier circuit; the feedback network comprises a fixed feedback resistance network and an adjustable resistance feedback network. When the SET network selects the first error amplifier circuit or the second error amplifier circuit, the third error amplifier circuit and the feedback circuit form a loop of the low dropout linear regulator. According to the dual-mode switchable output equipment provided by the invention, the fixed output working mode and the adjustable output working mode can be freely switched, and the switching between the fixed output and the adjustable output can be realized only by operating the change-over switch, namely, the one-to-many working mode is realized, so that great convenience is brought to use; and meanwhile, the cost for separately designing a fixed output power supply and an adjustable output power supply is also saved.

Description

Technical Field

[0001] The invention belongs to integrated circuit technology, relates to a power management chip, and in particular to a low voltage difference linear regulator with switchable output modes. Background Art

[0002] Linear regulators (Low Drop-out Regulators, LDO) are widely used in complete machines due to their good current capability and ripple suppression capabilities, and can be used as secondary power supplies for complete machines. In practical applications, based on the characteristics of the output end, it can be divided into fixed output and adjustable output. However, in some applications, since adjustable output and fixed output are different chips, the upgrade process of the complete machine may involve using the same chip but requiring power supplies with different output modes. Therefore, IC design companies are required to re-modify the output mode and re-tape out the chip, which will consume manpower and material resources, and waste time. Summary of the invention

[0003] In order to solve the problems existing in the prior art, the present invention proposes a low-voltage dropout linear regulator with switchable output modes, comprising a SET network, an EA network and a feedback network, wherein the EA network comprises a first error amplifier circuit, a second error amplifier circuit and a third error amplifier circuit, and the feedback network comprises a fixed feedback resistor network and an adjustable resistor feedback network. When the SET network selects the first error amplifier circuit or the second error amplifier circuit and the third error amplifier circuit and the feedback circuit to form a loop of the low-voltage dropout linear regulator, when the first error amplifier circuit, the third error amplifier circuit and the fixed feedback resistor network form a loop of the low-voltage dropout linear regulator, the output of the low-voltage dropout linear regulator is in an adjustable mode, and when the second error amplifier circuit, the third error amplifier circuit and the adjustable resistor feedback network form a loop of the low-voltage dropout linear regulator, the output of the low-voltage dropout linear regulator is in a fixed mode.

[0004] Furthermore, the SET network is implemented by a comparator circuit and an inverter, and a reference signal is used as the inverting input terminal of the comparator circuit. When the negative input of the comparator circuit is connected to different signals, the low-voltage difference linear regulator is in different working modes. The output signal of the comparator circuit is d6, and the signal d6 is obtained by an inverter to obtain the signal d5.

[0005] Furthermore, the SET network is implemented by a comparator circuit and an inverter, and a reference signal is used as the inverting input terminal of the comparator circuit. When the negative input of the comparator circuit is connected to different signals, the low-voltage difference linear regulator is in different working modes. The output signal of the comparator circuit is d6, and the signal d6 is obtained by an inverter to obtain the signal d5.

[0006] Furthermore, a first switch tube is set between the negative input terminal of the first error amplifier circuit and the positive input terminal of the third error amplifier circuit to control the on-off between the two, and the adjustable resistance feedback network controls whether to be connected between the negative input terminal of the first error amplifier circuit and the positive input terminal of the third error amplifier circuit through the third switch tube; a second switch tube is set between the negative input terminal of the second error amplifier circuit and the positive input terminal of the third error amplifier circuit to control the on-off between the two, and the fixed feedback resistance network controls whether to be connected between the negative input terminal of the second error amplifier circuit and the positive input terminal of the third error amplifier circuit through the fourth switch tube.

[0007] Furthermore, the on-off of the first switch tube and the third switch tube is controlled by the signal d6; the on-off of the second switch tube and the fourth switch tube is controlled by the signal d5.

[0008] Furthermore, the SET network is composed of first to fourth P-type MOS transistors, first to second N-type MOS transistors, first to second inverters and a first resistor, wherein:

[0009] The source power supply terminals of the first P-type MOS tube and the second P-type MOS tube are connected, the gates of the first P-type MOS tube and the second P-type MOS tube are connected to the bias voltage terminal, and the drain of the first P-type MOS tube is connected to one end of the first resistor and the source of the third P-type MOS tube;

[0010] The drain of the second P-type MOS tube, the drain of the second N-type MOS tube and the input end of the first inverter are connected together;

[0011] The gate of the third P-type MOS transistor serves as the inverting input terminal of the SET network, and the drain of the third P-type MOS transistor is connected with the drain and gate of the first N-type MOS transistor and the gate of the second N-type MOS transistor;

[0012] The other end of the first resistor is connected to the source of the fourth P-type MOS transistor, the gate of the fourth P-type MOS transistor serves as the non-inverting input end of the SET network, and the drain of the fourth P-type MOS transistor is grounded;

[0013] The source electrodes of the first N-type MOS tube and the second N-type MOS tube are grounded;

[0014] The first inverter and the second inverter are cascaded, and the first inverter outputs a signal d6 and the second inverter outputs a signal d5.

[0015] Furthermore, the size ratio between the first P-type MOS transistor and the second P-type MOS transistor is 1:1; the size ratio between the first N-type MOS transistor and the second N-type MOS transistor is 1:2.

[0016] Furthermore, the EA network is composed of the fifth to seventh P-type MOS transistors and the third to tenth N-type MOS transistors, wherein:

[0017] The source electrodes of the fifth to seventh P-type MOS tubes are connected to the power supply end, the source electrode and the gate electrode of the fifth P-type MOS tube, the gate electrode of the sixth P-type MOS tube, the drain electrodes of the third N-type MOS tube and the fourth N-type MOS tube are connected together;

[0018] The drain of the sixth P-type MOS tube is connected with the gate of the seventh P-type MOS tube, the fifth N-type MOS tube and the gate of the sixth N-type MOS tube;

[0019] The drain of the seventh P-type MOS tube is connected to the drain of the tenth N-type MOS tube and is connected to the feedback network as the output end of the EA network;

[0020] The gates of the third N-type MOS tube and the fourth N-type MOS tube are connected to the second reference power supply terminal, and the source of the third N-type MOS tube is connected to the drain of the seventh N-type MOS tube and the source of the fifth N-type MOS tube;

[0021] The source of the fourth N-type MOS tube is connected to the source of the sixth N-type MOS tube and the drain of the eighth N-type MOS tube;

[0022] The gate of the fifth N-type MOS transistor is connected to the first voltage signal fed back by the feedback network, and the gate of the sixth N-type MOS transistor is connected to the second voltage signal fed back by the feedback network;

[0023] The gate of the seventh N-type MOS transistor is connected to the signal d5, and the source of the seventh N-type MOS transistor is connected to the source of the eighth N-type MOS transistor and the drain of the ninth N-type MOS transistor;

[0024] The gate of the eighth N-type MOS transistor is connected to the signal d6;

[0025] The sources of the ninth N-type MOS transistor and the ninth N-type MOS transistor are grounded, and the gates of the ninth N-type MOS transistor and the tenth N-type MOS transistor are connected to the second bias voltage terminal.

[0026] Further, the feedback network includes an eleventh N-type MOS transistor, an eighth P-type MOS transistor, a first on-chip feedback resistor and a second on-chip feedback resistor connected in series, and a first off-chip feedback resistor and a second off-chip feedback resistor connected in series, wherein:

[0027] The gate of the eighth P-type MOS transistor is connected to the output end of the EA network as the input end of the feedback network, the source of the eighth P-type MOS transistor is connected to the power supply end, and the gate is connected to one end of the first on-chip feedback resistor and one end of the first off-chip feedback resistor respectively;

[0028] The voltage between the first on-chip feedback resistor and the second on-chip feedback resistor is used as the first voltage signal fed back by the feedback network, and the voltage between the first off-chip feedback resistor and the second off-chip feedback resistor is used as the second voltage signal fed back by the feedback network;

[0029] The drain of the eleventh N-type MOS tube is connected to one end of the second on-chip feedback resistor, the source of the eleventh N-type MOS tube is connected to one end of the second off-chip feedback resistor, and the gate of the eleventh N-type MOS tube is connected to the signal d5.

[0030] The present invention selects one of the modes through a SET port to obtain an adjustable output or a fixed output; in the present invention, when the SET voltage is at a high level, the output is in an adjustable output mode, and when the SET voltage is at a low level, different feedback resistor networks are selected through an internal switch circuit to achieve a fixed output mode, thereby ensuring that a low-voltage difference linear regulator with two output modes is implemented in the same chip, improving the integrated compatibility of a single chip, saving manpower and material resources from a circuit design end, and satisfying different application environments of the same chip from an application end, thereby achieving a win-win situation in terms of supply and demand. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The circuit topology diagram of the conventional fixed output and adjustable output in the prior art;

[0032] Figure 2 A topological diagram of a low voltage drop linear regulator with switchable output modes according to the present invention;

[0033] Figure 3 A circuit schematic diagram of a low voltage drop linear regulator with switchable output modes according to the present invention;

[0034] Figure 4 The present invention discloses a low voltage difference linear regulator with switchable output mode, and a Set signal and a V ADJ Simulation diagram when the terminals are short-circuited. OUT 1.2V;

[0035] Figure 5 A simulation diagram of a low voltage difference linear regulator with switchable output mode in the present invention when the Set signal is short-circuited with the ground terminal, when V OUT 5V;

[0036] Among them, MN1 is a first N-type MOS transistor; MN2 is a second N-type MOS transistor; MN3 is a third N-type MOS transistor; MN4 is a fourth N-type MOS transistor; MN5 is a fifth N-type MOS transistor; MN6 is a sixth N-type MOS transistor; MN7 is a seventh N-type MOS transistor; MN8 is an eighth N-type MOS transistor;

[0037] MN9, the ninth N-type MOS tube; MN10, the tenth N-type MOS tube; MN11, the eleventh N-type MOS tube;

[0038] MP1, the first P-type MOS tube; MP2, the second P-type MOS tube; MP3, the third P-type MOS tube; MP4, the fourth P-type MOS tube; MP5, the fifth P-type MOS tube; MP6, the sixth P-type MOS tube; MP7, the seventh P-type MOS tube; MP8, the eighth P-type MOS tube;

[0039] R1 represents the first resistor;

[0040] INV1, first inverter; INV2, second inverter;

[0041] R FIX1 , the first on-chip feedback resistor; R FIX2 , the second on-chip feedback resistor;

[0042] R ADJ1 , the first off-chip feedback resistor; R ADJ 2 , the second off-chip feedback resistor;

[0043] NMOS1, a first switch tube; NMOS2, a second switch tube; NMOS3, a third switch tube; NMOS4, a fourth switch tube; NMOS5, a fifth switch tube. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] The present invention provides a low-voltage difference linear regulator with switchable output modes, comprising a SET network, an EA network and a feedback network, wherein the EA network comprises a first error amplifier circuit, a second error amplifier circuit and a third error amplifier circuit, and the feedback network comprises a fixed feedback resistor network and an adjustable resistor feedback network. When the SET network selects the first error amplifier circuit or the second error amplifier circuit and the third error amplifier circuit and the feedback circuit to form a loop of the low-voltage difference linear regulator, when the first error amplifier circuit, the third error amplifier circuit and the fixed feedback resistor network form a loop of the low-voltage difference linear regulator, the output of the low-voltage difference linear regulator is in an adjustable mode, and when the second error amplifier circuit, the third error amplifier circuit and the adjustable resistor feedback network form a loop of the low-voltage difference linear regulator, the output of the low-voltage difference linear regulator is in a fixed mode.

[0046] Figure 1 This is a traditional fixed output and adjustable output circuit topology diagram, which mainly consists of an error amplifier EA, a P-type MOS tube MP, and the first on-chip feedback resistor R FIX1 and the second on-chip feedback resistor R FIX2 (fixed output), the first off-chip feedback resistor R ADJ1 And the external feedback resistor R ADJ2 (Adjustable output). When a fixed voltage is required, the internal circuit of the chip is modified to point A. When an adjustable output voltage is required, the feedback end of the internal circuit of the chip is separately designed as a port connected to point B, and the adjustable output voltage is achieved by connecting different resistors. The above circuit change solution can meet applications with different output requirements, but because it requires the design of different chips to meet the application, it limits the compatibility of the product after the application upgrade.

[0047] In view of the problems existing in the prior art, the present invention proposes a dual-mode switching low voltage drop linear voltage regulator circuit, the topology diagram of the circuit is as follows Figure 1 As shown, it includes a SET network, an EA network and a feedback network, the EA network includes a first error amplifier circuit, a second error amplifier circuit and a third error amplifier circuit, the feedback network includes a fixed feedback resistor network and an adjustable resistor feedback network, the SET network is implemented by a comparator circuit and an inverter, a reference signal is used as the inverting input terminal of the comparator circuit, when the negative input of the comparator circuit is connected to different signals, the low voltage difference linear regulator is in different working modes, the output signal of the comparison circuit is d6, and the signal d6 is obtained by an inverter to obtain the signal d5;

[0048] A first MOS tube is arranged between the negative input end of the first error amplifier circuit and the positive input end of the third error amplifier circuit to control the on-off between the two, and the adjustable resistance feedback network controls whether to be connected between the negative input end of the first error amplifier circuit and the positive input end of the third error amplifier circuit through the third MOS tube; a second MOS tube is arranged between the negative input end of the second error amplifier circuit and the positive input end of the third error amplifier circuit to control the on-off between the two, and the fixed feedback resistance network controls whether to be connected between the negative input end of the second error amplifier circuit and the positive input end of the third error amplifier circuit through the fourth MOS tube.

[0049] like Figure 2 In this embodiment, the reference signal at the positive input of the comparator input to the SET network is set to V ref 1. The mode of the low-dropout linear regulator is controlled by the Set signal at the inverting input terminal of the comparator input to the SET network, including:

[0050] When the Set signal is set higher than the reference signal Vref 1, the signal d6 output by the comparator of the SET network is high level, and the signal d5 obtained by the signal d6 passing through the inverter is low level. At this time, the first switch tube NMOS1 and the third switch tube NMOS3 are turned on, and the first error amplifier circuit EA1 is selected. At this time, the loop of the LDO is composed of the first error amplifier circuit EA1, the third error amplifier circuit EA3 and the adjustable resistor feedback network. At this time, the chip is in the output adjustable mode, and the output voltage can be obtained by connecting different feedback resistors on the periphery;

[0051] When the Set signal is set lower than the reference signal V ref 1, the signal d6 output by the comparator of the SET network is low level, and the signal d5 obtained after the signal d6 passes through the inverter is high level. At this time, the second switch tube NMOS2, the fourth switch tube NMOS4 and the fifth switch tube NMOS5 are turned on, and the second error amplifier circuit EA2 is selected. At this time, the loop of the LDO is composed of the second error amplifier circuit EA2, the third error amplifier circuit EA3, and a fixed feedback resistor network. At this time, the chip is in fixed output mode, and feedback resistors with different outputs can be pre-designed internally to obtain a fixed output voltage.

[0052] This embodiment also provides an implementation scheme of a low voltage difference linear regulator with switchable output modes, which is mainly realized by MOS tubes.

[0053] like Figure 3 , the SET network is composed of the first to fourth P-type MOS transistors, the first to second N-type MOS transistors, the first to second inverters and the first resistor, wherein:

[0054] The source power supply terminals of the first P-type MOS transistor MP1 and the second P-type MOS transistor MP2 are connected, the gates of the first P-type MOS transistor and the second P-type MOS transistor are connected to the bias voltage terminal, and the drain of the first P-type MOS transistor is connected to one end of the first resistor and the source of the third P-type MOS transistor MP3;

[0055] The drains of the second P-type MOS transistor MN1 and the second N-type MOS transistor MN2 and the input end of the first inverter INV1 are connected together;

[0056] The gate of the third P-type MOS transistor serves as the inverting input terminal of the SET network, and the drain of the third P-type MOS transistor is connected with the drain and gate of the first N-type MOS transistor and the gate of the second N-type MOS transistor;

[0057] The other end of the first resistor R1 is connected to the source of the fourth P-type MOS transistor, the gate of the fourth P-type MOS transistor MP4 serves as the positive phase input end of the SET network, and the drain of the fourth P-type MOS transistor is grounded;

[0058] The source electrodes of the first N-type MOS tube and the second N-type MOS tube are grounded;

[0059] The first inverter and the second inverter INV2 are cascaded, and the first inverter outputs a signal d6 and the second inverter outputs a signal d5.

[0060] As an optional implementation, the size ratio between the first P-type MOS transistor and the second P-type MOS transistor is 1:1; the size ratio between the first N-type MOS transistor and the second N-type MOS transistor is 1:2.

[0061] like Figure 3 , the EA network is composed of the fifth to seventh P-type MOS tubes and the third to tenth N-type MOS tubes, where:

[0062] The sources of the fifth to seventh P-type MOS transistors are connected to the power supply terminal, the source and gate of the fifth P-type MOS transistor MP5, the gate of the sixth P-type MOS transistor MP6, the drains of the third N-type MOS transistor MN3 and the fourth N-type MOS transistor MN4 are connected together;

[0063] The drain of the sixth P-type MOS transistor is connected with the gate of the seventh P-type MOS transistor MP7, the fifth N-type MOS transistor MN5 and the gate of the sixth N-type MOS transistor MN6;

[0064] The drain of the seventh P-type MOS transistor is connected to the drain of the tenth N-type MOS transistor MN10 and is connected to the feedback network as the output end of the EA network;

[0065] The gates of the third N-type MOS transistor and the fourth N-type MOS transistor are connected to the second reference power supply terminal, and the source of the third N-type MOS transistor is connected to the drain of the seventh N-type MOS transistor MN7 and the source of the fifth N-type MOS transistor;

[0066] The source of the fourth N-type MOS transistor is connected to the source of the sixth N-type MOS transistor and the drain of the eighth N-type MOS transistor MN8;

[0067] The gate of the fifth N-type MOS transistor is connected to the first voltage signal fed back by the feedback network, and the gate of the sixth N-type MOS transistor is connected to the second voltage signal fed back by the feedback network;

[0068] The gate of the seventh N-type MOS transistor is connected to the signal d5, and the source of the seventh N-type MOS transistor is connected to the source of the eighth N-type MOS transistor and the drain of the ninth N-type MOS transistor MN9;

[0069] The gate of the eighth N-type MOS transistor is connected to the signal d6;

[0070] The sources of the ninth N-type MOS transistor and the ninth N-type MOS transistor are grounded, and the gates of the ninth N-type MOS transistor and the tenth N-type MOS transistor are connected to the second bias voltage terminal.

[0071] like Figure 3 The feedback network includes an eleventh N-type MOS transistor MN11 and an eighth P-type MOS transistor MP8, a first on-chip feedback resistor and a second on-chip feedback resistor connected in series, and a first off-chip feedback resistor and a second off-chip feedback resistor connected in series, wherein:

[0072] The gate of the eighth P-type MOS transistor is connected to the output end of the EA network as the input end of the feedback network, the source of the eighth P-type MOS transistor is connected to the power supply end, and the gate is connected to one end of the first on-chip feedback resistor and one end of the first off-chip feedback resistor respectively;

[0073] The voltage between the first on-chip feedback resistor and the second on-chip feedback resistor is used as the first voltage signal fed back by the feedback network, and the voltage between the first off-chip feedback resistor and the second off-chip feedback resistor is used as the second voltage signal fed back by the feedback network;

[0074] The drain of the eleventh N-type MOS tube is connected to one end of the second on-chip feedback resistor, the source of the eleventh N-type MOS tube is connected to one end of the second off-chip feedback resistor, and the gate of the eleventh N-type MOS tube is connected to the signal d5.

[0075] This embodiment provides a setting embodiment of the Set signal. A person skilled in the art will understand that the working mode of the low voltage drop linear regulator with switchable output mode of the present invention specifically includes:

[0076] When the Set signal is ADJ When connected, the simulation diagram is as follows Figure 4 As shown, V ADJ Greater than V ref1 About 600mV, at this time, MP4 is cut off, at this time, the current of MP1 flows to MP3 and MN1 branches, at this time, the current of MN2 is greater than MP2, at this time, the output is low level, d6 is high level, MN8 is turned on, d5 is low level, MN7 and MN11 are cut off, at this time, the signal transmission is from MN6→MP7→MP→V ADJ , the error op amp composed of MN4 and MN6 is selected in the op amp pair Figure 2 The output of the first error amplifier circuit EA1, the eighth P-type MOS tube MP8, the first off-chip feedback resistor R ADJ1 and the second off-chip feedback resistor R ADJ2 Construct an adjustable resistance feedback network; implement specific functions;

[0077] When the Set signal is connected to GND, the simulation diagram is as follows Figure 5As shown, at this time, MP3 is cut off, the current of MP1 flows to MP4, the current of MP2 is greater than MN2, and the output is high level. D6 is low level, MN8 is cut off, D5 is high level, and MN7 is turned on. At this time, the signal transmission is from MN5→MP7→MP→V FIX , the error op amp composed of MN3 and MN5 is selected in the op amp pair Figure 2 The second error amplifier circuit EA2, the eighth P-type MOS tube MP8, the first on-chip feedback resistor R FIX1 and the second internal feedback resistor R FIX2 The fixed output mode is composed of

[0078] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A low voltage dropout linear regulator with switchable output mode, characterized in that: It includes a SET network, an EA network and a feedback network. The EA network includes a first error amplifier circuit, a second error amplifier circuit and a third error amplifier circuit. The feedback network includes a fixed feedback resistor network and an adjustable resistor feedback network. When the SET network selects the first error amplifier circuit or the second error amplifier circuit and the third error amplifier circuit and the feedback circuit to form a loop of a low-voltage difference linear regulator, when the first error amplifier circuit, the third error amplifier circuit and the fixed feedback resistor network form a loop of the low-voltage difference linear regulator, the output of the low-voltage difference linear regulator is in an adjustable mode, and when the second error amplifier circuit, the third error amplifier circuit and the adjustable resistor feedback network form a loop of the low-voltage difference linear regulator, the output of the low-voltage difference linear regulator is in a fixed mode.

2. A low voltage dropout linear regulator with switchable output mode according to claim 1, characterized in that: The SET network is implemented through a comparator circuit and an inverter. A reference signal is used as the inverting input of the comparator circuit. When the negative input of the comparator circuit is connected to different signals, the low-voltage difference linear regulator is in different working modes. The output signal of the comparator circuit is d6, and the signal d6 is converted into signal d5 through an inverter.

3. A low voltage dropout linear regulator with switchable output mode according to claim 2, characterized in that: A first switch tube is set between the negative input end of the first error amplifier circuit and the positive input end of the third error amplifier circuit to control the on-off between the two, and the adjustable resistance feedback network controls whether to be connected between the negative input end of the first error amplifier circuit and the positive input end of the third error amplifier circuit through the third switch tube; a second switch tube is set between the negative input end of the second error amplifier circuit and the positive input end of the third error amplifier circuit to control the on-off between the two, and the fixed feedback resistance network controls whether to be connected between the negative input end of the second error amplifier circuit and the positive input end of the third error amplifier circuit through the fourth switch tube.

4. A low voltage dropout linear regulator with switchable output mode according to claim 3, characterized in that: The on / off of the first switch tube and the third switch tube is controlled by the signal d6; the on / off of the second switch tube and the fourth switch tube is controlled by the signal d5.

5. A low voltage dropout linear regulator with switchable output modes according to any one of claims 1 to 4, characterized in that: The SET network is composed of first to fourth P-type MOS transistors, first to second N-type MOS transistors, first to second inverters and a first resistor, wherein: The source power supply terminals of the first P-type MOS tube and the second P-type MOS tube are connected, the gates of the first P-type MOS tube and the second P-type MOS tube are connected to the bias voltage terminal, and the drain of the first P-type MOS tube is connected to one end of the first resistor and the source of the third P-type MOS tube; The drain of the second P-type MOS tube, the drain of the second N-type MOS tube and the input end of the first inverter are connected together; The gate of the third P-type MOS transistor serves as the inverting input terminal of the SET network, and the drain of the third P-type MOS transistor is connected with the drain and gate of the first N-type MOS transistor and the gate of the second N-type MOS transistor; The other end of the first resistor is connected to the source of the fourth P-type MOS transistor, the gate of the fourth P-type MOS transistor serves as the non-inverting input end of the SET network, and the drain of the fourth P-type MOS transistor is grounded; The source electrodes of the first N-type MOS tube and the second N-type MOS tube are grounded; The first inverter and the second inverter are cascaded, and the first inverter outputs a signal d6 and the second inverter outputs a signal d5.

6. The low voltage dropout linear regulator with switchable output mode according to claim 5, characterized in that: The size ratio between the first P-type MOS transistor and the second P-type MOS transistor is 1:1; the size ratio between the first N-type MOS transistor and the second N-type MOS transistor is 1:

2.

7. The low voltage dropout linear regulator with switchable output mode according to claim 5, characterized in that: The EA network is composed of the fifth to seventh P-type MOS transistors and the third to tenth N-type MOS transistors, wherein: The source electrodes of the fifth to seventh P-type MOS tubes are connected to the power supply end, the source electrode and the gate electrode of the fifth P-type MOS tube, the gate electrode of the sixth P-type MOS tube, the drain electrodes of the third N-type MOS tube and the fourth N-type MOS tube are connected together; The drain of the sixth P-type MOS tube is connected with the gate of the seventh P-type MOS tube, the fifth N-type MOS tube and the gate of the sixth N-type MOS tube; The drain of the seventh P-type MOS tube is connected to the drain of the tenth N-type MOS tube and is connected to the feedback network as the output end of the EA network; The gates of the third N-type MOS tube and the fourth N-type MOS tube are connected to the second reference power supply terminal, and the source of the third N-type MOS tube is connected to the drain of the seventh N-type MOS tube and the source of the fifth N-type MOS tube; The source of the fourth N-type MOS tube is connected to the source of the sixth N-type MOS tube and the drain of the eighth N-type MOS tube; The gate of the fifth N-type MOS transistor is connected to the first voltage signal fed back by the feedback network, and the gate of the sixth N-type MOS transistor is connected to the second voltage signal fed back by the feedback network; The gate of the seventh N-type MOS transistor is connected to the signal d5, and the source of the seventh N-type MOS transistor is connected to the source of the eighth N-type MOS transistor and the drain of the ninth N-type MOS transistor; The gate of the eighth N-type MOS transistor is connected to the signal d6; The sources of the ninth N-type MOS transistor and the ninth N-type MOS transistor are grounded, and the gates of the ninth N-type MOS transistor and the tenth N-type MOS transistor are connected to the second bias voltage terminal.

8. The low voltage dropout linear regulator with switchable output mode according to claim 7, characterized in that: The feedback network includes an eleventh N-type MOS transistor, an eighth P-type MOS transistor, a first on-chip feedback resistor and a second on-chip feedback resistor connected in series, and a first off-chip feedback resistor and a second off-chip feedback resistor connected in series, wherein: The gate of the eighth P-type MOS transistor is connected to the output end of the EA network as the input end of the feedback network, the source of the eighth P-type MOS transistor is connected to the power supply end, and the gate is respectively connected to one end of the first on-chip feedback resistor and one end of the first off-chip feedback resistor; The voltage between the first on-chip feedback resistor and the second on-chip feedback resistor is used as the first voltage signal fed back by the feedback network, and the voltage between the first off-chip feedback resistor and the second off-chip feedback resistor is used as the second voltage signal fed back by the feedback network; The drain of the eleventh N-type MOS tube is connected to one end of the second on-chip feedback resistor, the source of the eleventh N-type MOS tube is connected to one end of the second off-chip feedback resistor, and the gate of the eleventh N-type MOS tube is connected to the signal d5.

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