High-precision band-gap reference circuit without operational amplifier

Abstract

The invention discloses a high-precision band-gap reference circuit without an operational amplifier, which belongs to the field of analog circuits, and can generate high-precision reference voltage, detect the starting of the reference voltage, output an enable signal to control the internal starting logic of the analog circuit, and complete the sequential control of the starting process of the circuit. The high-precision band-gap reference circuit without the operational amplifier comprises a starting circuit, a reference core circuit and a reference detection circuit. Wherein the starting circuit provides starting current for the band-gap reference, so that the reference core circuit starts to work; the reference core circuit generates high-precision reference output voltage; when normal starting of the band-gap reference is completed, the reference detection circuit outputs a high signal to enable a subsequent module. According to the invention, a lower initial working voltage can be achieved; no operational amplifier clamp exists, and offset introduced by the operational amplifier and high gain of the required operational amplifier do not exist; the circuit structure is simple, and the low-power-consumption design of the whole band-gap reference can be achieved.

Description

Technical Field

[0001] The invention relates to the technical field of analog circuits, and in particular to a high-precision bandgap reference circuit without an operational amplifier. Background Art

[0002] Bandgap voltage reference circuits are widely used in analog and hybrid circuits, such as DC-DC, PLL phase-locked loops, voltage tuners, voltmeters, ammeters and other test instruments, as well as bias circuits, etc. Bandgap reference voltage circuits usually provide high-precision, low-temperature-coefficient voltage or current for other modules, and their performance directly or indirectly determines the performance indicators of the entire integrated circuit system.

[0003] The basic principle of the bandgap reference voltage circuit is to add a voltage with a negative temperature coefficient and a voltage with a positive temperature coefficient with appropriate weights. Figure 1 It is an implementation of a bandgap reference voltage circuit in the prior art, including an operational amplifier A0, resistors R1 and R2, three PNP transistors and three PMOS transistors. The current mirror implemented by PMOS tubes M1 and M2 and the operational amplifier A0 form a negative feedback loop, so that the voltage of node A is equal to that of node B. The difference between the base and emitter voltage of transistor Q1 , the difference between the base and emitter voltage of transistor Q2 At the same current, due to the different numbers of transistors Q1 and Q2 connected in parallel, the current density of Q1 and Q2 is different, so the voltage drop on resistor R1 is and difference , It is proportional to the absolute temperature and its expression is as follows: (1) in is the current density ratio of transistor Q1 and single transistor Q2, and are the currents flowing through Q1 and a single transistor Q2 respectively, and N is the number of transistors Q2 connected in parallel; Therefore, the current flowing through resistor R1 It is a current that is proportional to the absolute temperature.

[0004] Current With current , There is a mirror relationship, and the three are equal. The final current A positive temperature voltage and a negative temperature voltage are generated through the resistor R2 Summing to generate reference voltage : (2) It can be seen from formula (2) that by reasonably selecting the ratio of R2 to R1 and the value of N, a reference voltage with a smaller temperature coefficient can be obtained. However, the existing bandgap reference voltage circuit has some shortcomings in generating reference voltage: a differential op amp is required in the circuit, which has input offset. , which will affect the temperature coefficient of the reference voltage and the reference accuracy under PVT; the gain requirement for the op amp is high, which increases the difficulty of circuit design and the power consumption of the circuit; the minimum operating voltage is high, making it difficult to operate at a lower starting voltage. Summary of the invention

[0005] The object of the present invention is to provide a high-precision bandgap reference circuit without an operational amplifier to solve the problems of conventional operational amplifier offset error, reference voltage accuracy and reference minimum operating voltage.

[0006] In order to solve the above technical problems, the present invention provides a high-precision bandgap reference circuit without an operational amplifier, which generates a high-precision reference voltage, detects the reference voltage and starts to output an enable signal to control the internal startup logic of the analog circuit, thereby completing the timing control of the circuit startup process; The high-precision bandgap reference circuit without operational amplifier includes a startup circuit, a reference core circuit, and a reference detection circuit; wherein, The startup circuit provides a startup current for the bandgap reference, so that the reference core circuit starts to work; The reference core circuit generates a high-precision reference output voltage; When the bandgap reference is started up normally, the reference detection circuit outputs a high signal to enable subsequent modules.

[0007] In one embodiment, the startup circuit includes a first current source, a first N-type MOS transistor and a first NPN-type transistor; the tail end of the first current source is connected to the drain of the first N-type MOS transistor, the gate of the first N-type MOS transistor is short-circuited with its own drain, the source of the first N-type MOS transistor is connected to the collector of the first NPN-type transistor, the base of the first NPN-type transistor is short-circuited with its own collector, and the emitter of the first NPN-type transistor is grounded.

[0008] In one embodiment, the reference core circuit includes a second N-type MOS transistor, a second NPN-type triode, a third N-type MOS transistor, a third NPN-type triode, a first P-type MOS transistor, a fourth NPN-type triode, a second P-type MOS transistor, a third P-type MOS transistor, a fourth N-type MOS transistor, a fifth N-type MOS transistor, a fifth NPN-type triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a capacitor; The drain of the second N-type MOS tube is simultaneously connected to the gate of the first P-type MOS tube, the gate of the second P-type MOS tube, the drain of the second P-type MOS tube and the drain of the fourth N-type MOS tube, the source of the second N-type MOS tube is simultaneously connected to the source of the third N-type MOS tube, the first end of the first resistor and the first end of the fourth resistor; the tail end of the first resistor is simultaneously connected to the first end of the second resistor and the base of the second NPN-type transistor; the tail end of the second resistor is simultaneously connected to the first end of the third resistor and the collector of the second NPN-type transistor, and the emitter of the second NPN-type transistor is grounded; The drain of the third N-type MOS transistor is connected to the power supply, the source of the third N-type MOS transistor is simultaneously connected to the head end of the fourth resistor, the head end of the first resistor and the source of the second N-type MOS transistor; the tail end of the fourth resistor is simultaneously connected to the head end of the fifth resistor, the tail end of the capacitor, the base of the fourth NPN transistor and the reference detection circuit; the tail end of the fifth resistor is connected to the collector of the third NPN transistor; the base of the third NPN transistor is connected to the tail end of the third resistor; the emitter of the third NPN transistor is connected to the head end of the sixth resistor; and the tail end of the sixth resistor is grounded; The source of the first P-type MOS tube is connected to the power supply, and the drain of the first P-type MOS tube is simultaneously connected to the gate of the third N-type MOS tube, the head end of the capacitor, the gate of the fourth N-type MOS tube, the collector of the fourth NPN-type transistor and the gate of the sixth N-type MOS tube; the emitter of the fourth NPN-type transistor is grounded; The source of the second P-type MOS tube is connected to the power supply, and the gate of the second P-type MOS tube is simultaneously connected to the drain of the second P-type MOS tube, the gate of the third P-type MOS tube, the gate of the first P-type MOS tube and the drain of the fourth N-type MOS tube; the source of the third P-type MOS tube is connected to the power supply, and the drain of the third P-type MOS tube is simultaneously connected to the drain of the fifth N-type MOS tube and the gate of the fifth N-type MOS tube; the source of the fourth N-type MOS tube is simultaneously connected to the source of the fifth N-type MOS tube and the collector of the fifth NPN-type transistor; the emitter of the fourth NPN-type transistor is grounded; and the emitter of the fifth NPN-type transistor is grounded.

[0009] In one implementation, the reference detection circuit includes a fourth P-type MOS transistor, a fifth P-type MOS transistor, a sixth P-type MOS transistor, a seventh P-type MOS transistor, a sixth N-type MOS transistor, a sixth NPN-type triode, a first inverter, a second inverter, and a seventh resistor; The source of the fourth P-type MOS tube is connected to the power supply, the gate of the fourth P-type MOS tube is connected to the drain of the fourth P-type MOS tube, the gate of the fifth P-type MOS tube, the gate of the sixth P-type MOS tube and the drain of the sixth N-type MOS tube; the source of the sixth N-type MOS tube is connected to the collector of the sixth NPN-type transistor; the emitter of the sixth NPN-type transistor is connected to the head end of the seventh resistor; and the tail end of the seventh resistor is grounded; The source of the fifth P-type MOS tube is connected to the power supply, the drain of the fifth P-type MOS tube is simultaneously connected to the drain of the seventh P-type MOS tube, the input end of the first inverter and the collector of the seventh NPN-type transistor; the source of the sixth P-type MOS tube is connected to the power supply, the drain of the sixth P-type MOS tube is connected to the source of the seventh P-type MOS tube; the gate of the seventh P-type MOS tube is simultaneously connected to the output end of the first inverter and the input end of the second inverter; the emitter of the seventh NPN-type transistor is grounded; The gate of the first N-type MOS transistor is connected to the gate of the second N-type MOS transistor; the base of the first NPN-type transistor is connected to the base of the seventh NPN-type transistor; The gate of the sixth N-type MOS transistor is simultaneously connected to the gate of the third N-type MOS transistor, the gate of the fourth N-type MOS transistor, the drain of the first P-type MOS transistor, the collector of the fourth NPN-type transistor and the head end of the capacitor; the base of the sixth NPN-type transistor is simultaneously connected to the base of the fourth NPN-type transistor, the tail end of the fourth resistor, the head end of the fifth resistor and the tail end of the capacitor.

[0010] In one implementation, the common end of the source of the third N-type MOS transistor, the first end of the fourth resistor, the first end of the first resistor and the source of the second N-type MOS transistor is the output reference voltage signal VBG_1.2V of the bandgap reference; the output end of the second inverter is the output enable signal VBG_OK_1 of the reference voltage detection circuit.

[0011] The present invention provides a high-precision bandgap reference circuit without an operational amplifier, which has the following gain effects: (1) The bandgap reference circuit of the present invention has a low minimum operating voltage of 1.5V, and has a wider voltage applicability in analog circuits; (2) The present invention has no op amp clamp, no op amp gain and bandwidth requirements, and a simple design structure; (3) The present invention avoids the input offset introduced by the differential input mismatch of the operational amplifier, and the output reference voltage has higher accuracy; (4) The branch currents of the entire bandgap reference are all operating currents at the nA level, which can achieve low power consumption design of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of a bandgap reference voltage circuit in the prior art; Figure 2 is a structural block diagram of a bandgap reference circuit provided by the present invention; Figure 3 The figure is a structural principle diagram of the bandgap reference circuit provided by the present invention. DETAILED DESCRIPTION

[0013] The following is a further detailed description of a high-precision bandgap reference circuit without an operational amplifier proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0014] The present invention provides a high-precision bandgap reference circuit without an operational amplifier, which can generate a high-precision 1.2V reference voltage, detect the reference voltage to start and complete the output enable signal to control the internal startup logic of the analog circuit, and complete the timing control of the circuit startup process. The bandgap reference of the present invention fully realizes the startup of the reference circuit, the generation of the reference voltage, and the power-on timing control of the subsequent modules.

[0015] like Figure 2 As shown, the op-amp-free high-precision bandgap reference circuit of the present invention comprises a startup circuit 101, a reference core circuit 102, and a reference detection circuit 103. The startup circuit 101 provides a startup current for the bandgap reference, so that the reference core circuit 102 starts to work; the reference core circuit 102 generates a high-precision reference output voltage of 1.2V; when the bandgap reference is started normally, the reference detection circuit 103 outputs a high signal to enable subsequent modules.

[0016] like Figure 3 As shown, the startup circuit 101 includes a first current source IDC1, a first N-type MOS transistor MN1 and a first NPN-type transistor Q1. The tail end of the first current source IDC1 is connected to the drain of the first N-type MOS transistor MN1, the gate of the first N-type MOS transistor MN1 is short-circuited with its own drain, the source of the first N-type MOS transistor MN1 is connected to the collector of the first NPN-type transistor Q1, the base of the first NPN-type transistor Q1 is short-circuited with its own collector, and the emitter of the first NPN-type transistor Q1 is grounded.

[0017] The reference core circuit 102 includes a second N-type MOS transistor MN2, a second NPN-type transistor Q2, a third N-type MOS transistor MN3, a third NPN-type transistor Q3, a first P-type MOS transistor MP1, a fourth NPN-type transistor Q4, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth N-type MOS transistor MN4, a fifth N-type MOS transistor MN5, a fifth NPN-type transistor Q5, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, and a capacitor C1.

[0018] The drain of the second N-type MOS transistor MN2 is simultaneously connected to the gate of the first P-type MOS transistor MP1, the gate of the second P-type MOS transistor MP2, the drain of the second P-type MOS transistor MP2 and the drain of the fourth N-type MOS transistor MN4; the source of the second N-type MOS transistor MN2 is simultaneously connected to the source of the third N-type MOS transistor MN3, the first end of the resistor R1 and the first end of the resistor R4; the tail end of the resistor R1 is simultaneously connected to the first end of the resistor R2 and the base of the second NPN-type transistor Q2; the tail end of the resistor R2 is simultaneously connected to the first end of the resistor R3 and the collector of the second NPN-type transistor Q2, and the emitter of the second NPN-type transistor Q2 is grounded.

[0019] The drain of the third N-type MOS transistor MN3 is connected to the power supply, the source of the third N-type MOS transistor MN3 is simultaneously connected to the head end of the resistor R4, the head end of the resistor R1 and the source of the second N-type MOS transistor MN2; the tail end of the resistor R4 is simultaneously connected to the head end of the resistor R5, the tail end of the capacitor C1, the base of the fourth NPN-type transistor Q4 and the base of the sixth NPN-type transistor Q6; the tail end of the resistor R5 is connected to the collector of the third NPN-type transistor Q3; the base of the third NPN-type transistor Q3 is connected to the tail end of the resistor R3; the emitter of the third NPN-type transistor Q3 is connected to the head end of the resistor R6; and the tail end of the resistor R6 is grounded.

[0020] The source of the first P-type MOS transistor MP1 is connected to the power supply, and the drain of the first P-type MOS transistor MP1 is simultaneously connected to the gate of the third N-type MOS transistor MN3, the head end of the capacitor C1, the gate of the fourth N-type MOS transistor MN4, the collector of the fourth NPN-type transistor Q4 and the gate of the sixth N-type MOS transistor MN6; the emitter of the fourth NPN-type transistor Q4 is grounded.

[0021] The source of the second P-type MOS transistor MP2 is connected to the power supply, and the gate of the second P-type MOS transistor MP2 is simultaneously connected to the drain of the second P-type MOS transistor MP2, the gate of the third P-type MOS transistor MP3, the gate of the first P-type MOS transistor MP1, and the drain of the fourth N-type MOS transistor MN4; the source of the third P-type MOS transistor MP3 is connected to the power supply, and the drain of the third P-type MOS transistor MP3 is simultaneously connected to the drain of the fifth N-type MOS transistor MN5 and the gate of the fifth N-type MOS transistor MN5; the source of the fourth N-type MOS transistor MN4 is simultaneously connected to the source of the fifth N-type MOS transistor MN5 and the collector of the fifth NPN-type transistor Q5; the emitter of the fourth NPN-type transistor Q4 is grounded; and the emitter of the fifth NPN-type transistor Q5 is grounded.

[0022] The reference detection circuit 103 includes a fourth P-type MOS transistor MP4, a fifth P-type MOS transistor MP5, a sixth P-type MOS transistor MP6, a seventh P-type MOS transistor MP7, a sixth N-type MOS transistor MN6, a sixth NPN-type transistor Q6, a first inverter INV1, a second inverter INV2 and a resistor R7.

[0023] The source of the fourth P-type MOS transistor MP4 is connected to the power supply, the gate of the fourth P-type MOS transistor MP4 is simultaneously connected to the drain of the fourth P-type MOS transistor MP4, the gate of the fifth P-type MOS transistor MP5, the gate of the sixth P-type MOS transistor MP6 and the drain of the sixth N-type MOS transistor MN6; the source of the sixth N-type MOS transistor MN6 is connected to the collector of the sixth NPN-type transistor Q6; the emitter of the sixth NPN-type transistor Q6 is connected to the head end of the resistor R7; and the tail end of the resistor R7 is grounded.

[0024] The source of the fifth P-type MOS transistor MP5 is connected to the power supply, and the drain of the fifth P-type MOS transistor MP5 is simultaneously connected to the drain of the seventh P-type MOS transistor MP7, the input end of the first inverter INV1 and the collector of the seventh NPN-type transistor Q7; the source of the sixth P-type MOS transistor MP6 is connected to the power supply, and the drain of the sixth P-type MOS transistor MP6 is connected to the source of the seventh P-type MOS transistor MP7; the gate of the seventh P-type MOS transistor MP7 is simultaneously connected to the output end of the first inverter INV1 and the input end of the second inverter INV2; the emitter of the seventh NPN-type transistor Q7 is grounded.

[0025] The gate of the first N-type MOS transistor MN1 is connected to the gate of the second N-type MOS transistor MN2; the base of the first NPN-type transistor Q1 is connected to the base of the seventh NPN-type transistor Q7.

[0026] The gate of the sixth N-type MOS transistor MN6 is simultaneously connected to the gate of the third N-type MOS transistor MN3, the gate of the fourth N-type MOS transistor MN4, the drain of the first P-type MOS transistor MP1, the collector of the fourth NPN-type transistor Q4 and the head end of the capacitor C1; the base of the sixth NPN-type transistor Q6 is simultaneously connected to the base of the fourth NPN-type transistor Q4, the tail end of the resistor R4, the head end of the resistor R5 and the tail end of the capacitor C1.

[0027] The common end of the source of the third N-type MOS transistor MN3, the first end of the resistor R4, the first end of the resistor R1 and the source of the second N-type MOS transistor MN2 is the output reference voltage signal VBG_1.2V of the bandgap reference; the output end of the second inverter INV2 is the output enable signal VBG_OK_1 of the reference voltage detection circuit.

[0028] The detailed working process of the present invention is as follows: When Figure 3 As shown, the startup current IDC1 in the startup circuit 101 generates a current that passes through the subsequent reference core circuit 102. The base voltage difference ΔV between the base of the second NPN transistor Q2 and the base of the third NPN transistor Q3 in the core reference circuit 102 is BEIt falls on resistors R2 and R6. Because the transistor amplification factor β exists, the current on resistor R3 is a small current of 1 / β, so the voltage on resistor R3 can be ignored in the calculation. Resistor R3 is used as the second-order compensation of the bandgap reference.

[0029] The number of the second NPN transistor Q2 is 1, the number of the fifth NPN transistor Q5 is 1, the number of the second P-type MOS transistor MP2 is 1, the number of the first P-type MOS transistor MP1 is 4, the number of the third P-type MOS transistor MP3 is 3, and the number of the fourth NPN transistor MP4 is 1. In normal operation, the IPTAT current generated by the second NPN transistor Q2 passes through the load of the operational amplifier and the mirror current of the current mirror, and the current to the fourth NPN transistor Q4 is the same. Because the number of the second NPN transistor Q2 and the fourth NPN transistor Q4 is also equal, the voltage of the clamped node A (located between the resistor R1 and the resistor R2) and the node B (located between the resistor R4 and the resistor R5) are equal, and the IPTAT currents generated by the two branches of the reference core circuit are equal. A 1.2V reference voltage output is generated at the common node of the first end of the resistor R4, the first end of the resistor R1 and the source of the third P-type MOS transistor MP3, and the voltage of each voltage domain can be obtained through resistor voltage division. The lowest working voltage of the reference voltage output generated by this structure is 1.5V.

[0030] The number of the first NPN transistor Q1 is 1, and the number of the seventh NPN transistor Q7 is 1. When the bandgap reference works normally, the voltage of the node B will increase, which will enable the sixth NPN transistor Q6 and the sixth N-type MOS transistor MN6 to generate current. The current mirror through the fourth P-type MOS transistor MP4 and the fifth P-type MOS transistor MP5 will increase the voltage at the input node of the first inverter INV1, that is, when the bandgap reference is started, the reference detection circuit 103 will output the start-up completion second inverter INV2 enable signal VBG_OK_1, start the subsequent working module in the analog circuit power supply system, and ensure the power-on start-up timing in the analog circuit. The hysteresis control of the enable signal VBG_OK_1 of the seventh P-type MOS transistor MP7 ensures the stable output of the signal and is not affected by the fluctuation of the power supply voltage.

[0031] The high-precision bandgap reference circuit without an op amp of the present invention can have a lower starting operating voltage; there is no op amp clamping, and there is no offset introduced by the op amp and high gain required of the op amp; the circuit structure is simple, and the low-power design of the entire bandgap reference can be achieved; it can have good adaptability with the power system module of the analog circuit, and the timing control eliminates the power-on problem. The present invention has the characteristics of high precision, low power consumption, strong practicality, and simple structure, and has a very wide range of application scenarios in analog circuits.

[0032] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high-precision bandgap reference circuit without an operational amplifier, characterized in that: Generate high-precision reference voltage, detect the reference voltage startup and complete the output enable signal to control the internal startup logic of the analog circuit, and complete the timing control of the circuit startup process; The high-precision bandgap reference circuit without operational amplifier includes a startup circuit, a reference core circuit, and a reference detection circuit; wherein, The startup circuit provides a startup current for the bandgap reference, so that the reference core circuit starts to work; The reference core circuit generates a high-precision reference output voltage; When the bandgap reference is started up normally, the reference detection circuit outputs a high signal to enable subsequent modules.

2. The high-precision bandgap reference circuit without an operational amplifier as claimed in claim 1, characterized in that: The startup circuit comprises a first current source, a first N-type MOS transistor and a first NPN-type triode; the tail end of the first current source is connected to the drain of the first N-type MOS transistor, the gate of the first N-type MOS transistor is short-circuited with its own drain, the source of the first N-type MOS transistor is connected to the collector of the first NPN-type triode, the base of the first NPN-type triode is short-circuited with its own collector, and the emitter of the first NPN-type triode is grounded.

3. The high-precision bandgap reference circuit without operational amplifier as claimed in claim 2, characterized in that: The reference core circuit includes a second N-type MOS transistor, a second NPN-type triode, a third N-type MOS transistor, a third NPN-type triode, a first P-type MOS transistor, a fourth NPN-type triode, a second P-type MOS transistor, a third P-type MOS transistor, a fourth N-type MOS transistor, a fifth N-type MOS transistor, a fifth NPN-type triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a capacitor; The drain of the second N-type MOS tube is simultaneously connected to the gate of the first P-type MOS tube, the gate of the second P-type MOS tube, the drain of the second P-type MOS tube and the drain of the fourth N-type MOS tube, the source of the second N-type MOS tube is simultaneously connected to the source of the third N-type MOS tube, the first end of the first resistor and the first end of the fourth resistor; the tail end of the first resistor is simultaneously connected to the first end of the second resistor and the base of the second NPN-type transistor; the tail end of the second resistor is simultaneously connected to the first end of the third resistor and the collector of the second NPN-type transistor, and the emitter of the second NPN-type transistor is grounded; The drain of the third N-type MOS transistor is connected to the power supply, the source of the third N-type MOS transistor is simultaneously connected to the head end of the fourth resistor, the head end of the first resistor and the source of the second N-type MOS transistor; the tail end of the fourth resistor is simultaneously connected to the head end of the fifth resistor, the tail end of the capacitor, the base of the fourth NPN transistor and the reference detection circuit; the tail end of the fifth resistor is connected to the collector of the third NPN transistor; the base of the third NPN transistor is connected to the tail end of the third resistor; the emitter of the third NPN transistor is connected to the head end of the sixth resistor; and the tail end of the sixth resistor is grounded; The source of the first P-type MOS tube is connected to the power supply, and the drain of the first P-type MOS tube is simultaneously connected to the gate of the third N-type MOS tube, the head end of the capacitor, the gate of the fourth N-type MOS tube, the collector of the fourth NPN-type transistor and the gate of the sixth N-type MOS tube; the emitter of the fourth NPN-type transistor is grounded; The source of the second P-type MOS tube is connected to the power supply, and the gate of the second P-type MOS tube is simultaneously connected to the drain of the second P-type MOS tube, the gate of the third P-type MOS tube, the gate of the first P-type MOS tube and the drain of the fourth N-type MOS tube; the source of the third P-type MOS tube is connected to the power supply, and the drain of the third P-type MOS tube is simultaneously connected to the drain of the fifth N-type MOS tube and the gate of the fifth N-type MOS tube; the source of the fourth N-type MOS tube is simultaneously connected to the source of the fifth N-type MOS tube and the collector of the fifth NPN-type transistor; the emitter of the fourth NPN-type transistor is grounded; and the emitter of the fifth NPN-type transistor is grounded.

4. The high-precision bandgap reference circuit without operational amplifier as claimed in claim 3, characterized in that: The reference detection circuit includes a fourth P-type MOS transistor, a fifth P-type MOS transistor, a sixth P-type MOS transistor, a seventh P-type MOS transistor, a sixth N-type MOS transistor, a sixth NPN-type triode, a first inverter, a second inverter and a seventh resistor; The source of the fourth P-type MOS tube is connected to the power supply, the gate of the fourth P-type MOS tube is connected to the drain of the fourth P-type MOS tube, the gate of the fifth P-type MOS tube, the gate of the sixth P-type MOS tube and the drain of the sixth N-type MOS tube; the source of the sixth N-type MOS tube is connected to the collector of the sixth NPN-type transistor; the emitter of the sixth NPN-type transistor is connected to the head end of the seventh resistor; and the tail end of the seventh resistor is grounded; The source of the fifth P-type MOS tube is connected to the power supply, and the drain of the fifth P-type MOS tube is simultaneously connected to the drain of the seventh P-type MOS tube, the input end of the first inverter and the collector of the seventh NPN-type transistor; the source of the sixth P-type MOS tube is connected to the power supply, and the drain of the sixth P-type MOS tube is connected to the source of the seventh P-type MOS tube; The gate of the seventh P-type MOS tube is connected to the output end of the first inverter and the input end of the second inverter at the same time; the emitter of the seventh NPN-type transistor is grounded; The gate of the first N-type MOS transistor is connected to the gate of the second N-type MOS transistor; the base of the first NPN-type transistor is connected to the base of the seventh NPN-type transistor; The gate of the sixth N-type MOS transistor is simultaneously connected to the gate of the third N-type MOS transistor, the gate of the fourth N-type MOS transistor, the drain of the first P-type MOS transistor, the collector of the fourth NPN-type transistor and the head end of the capacitor; the base of the sixth NPN-type transistor is simultaneously connected to the base of the fourth NPN-type transistor, the tail end of the fourth resistor, the head end of the fifth resistor and the tail end of the capacitor.

5. The high-precision bandgap reference circuit without operational amplifier as claimed in claim 4, characterized in that: The common end of the source of the third N-type MOS transistor, the first end of the fourth resistor, the first end of the first resistor and the source of the second N-type MOS transistor is the output reference voltage signal VBG_1.2V of the bandgap reference; The output terminal of the second inverter is an output enable signal VBG_OK_1 of the reference voltage detection circuit.

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