Logical to physical data structure

Abstract

The invention relates to a logical-to-physical data structure. An example apparatus is provided that includes a controller coupled to a non-volatile memory (NVM) device. The controller may be configured to cause a logical block address (LBA) to be stored in a first logical-to-physical (L2P) data structure in the NVM device and a physical block address (PBA) to be stored in a second L2P data structure in the NVM device. The first L2P data structure and the second L2P data structure may have the same size associated therewith.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the invention name “Logical to Physical Data Structure”, application number 201980036672.9 and application date March 27, 2019. Technical Field

[0003] The present invention relates generally to semiconductor memory and methods, and more particularly to apparatus and methods related to logical to physical data structures. Background Art

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computing systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory and NOR flash memory, among others.

[0005] Data may be stored according to logical block addresses (LBAs) and physical block addresses (PBAs). The mapping between LBAs and PBAs may be referred to as logical to physical (L2P) mappings. The mapping between LBAs and PBAs may be stored in a tree structure. The tree structure for storing L2P data may include a P-level L2P table, where P is a non-zero integer. A simple example according to some methods may include a 2-level L2P table. The first level table may contain the address of the second level table, which may be referred to as a "segment". In some methods, each segment may include an L2P table for a small range of contiguous LBAs (e.g., 1024 LBAs). Summary of the invention

[0006] One embodiment of the present invention provides an apparatus comprising: a controller coupled to a non-volatile memory (NVM) device, wherein the controller is configured to cause: a logical block address (LBA) to be stored in a first logical-to-physical (L2P) data structure in the NVM device; and a physical block address (PBA) to be stored in a second L2P data structure in the NVM device, wherein the first L2P data structure and the second L2P data structure have the same size associated therewith.

[0007] Another embodiment of the present invention provides an apparatus comprising: a non-volatile memory (NVM) device comprising a first memory portion and a second memory portion; and a controller coupled to the NVM device, wherein the controller is configured to cause: a first hash function to be executed to determine a first location in a first logical-to-physical (L2P) address data structure in the first memory portion where a logical block address (LBA) is to be stored; a determination is made that the first location contains a second LBA; and a second hash function to be executed to determine a second location in the first L2P address data structure in the first memory portion where the LBA is to be stored.

[0008] Yet another embodiment of the present invention provides an apparatus comprising: a non-volatile memory (NVM) device; a flash memory device; and a controller coupled to the NVM device and the flash memory device, wherein the controller is configured to cause: a first hash function to be executed to determine a first location in a first data structure in the NVM device where a logical block address (LBA) is to be stored; a physical block address to be set to a corresponding first location in a second data structure in the NVM device in response to the determination that the LBA is to be stored in the first location in the first data structure; a second hash function to be executed to determine a second location in the first data structure where the LBA is to be stored; and the physical block address to be set to a corresponding second location in the second data structure in the NVM device in response to the determination that the LBA is to be stored in the second location in the first data structure.

[0009] Yet another embodiment of the present invention provides a method comprising: determining a first location in a first logical-to-physical (L2P) data structure stored in a non-volatile memory (NVM) device for writing a first logical block address (LBA); determining that the first location includes a second LBA; writing the first LBA to a second location in the first L2P data structure in response to the determination that the first location includes the second LBA; and writing a physical block address (PBA) corresponding to the first LBA to a location in a second L2P data structure stored in the NVM device, wherein the second location in the first L2P data structure corresponds to the location in the second L2P data structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a functional block diagram of a device in the form of a computing system including a memory system according to several embodiments of the present invention.

[0011] Figure 2 is a block diagram of an apparatus in the form of a memory system according to several embodiments of the invention.

[0012] Figure 3A is a block diagram of a flash memory data structure according to several embodiments of the present invention.

[0013] Figure 3B is a block diagram of an example logical to physical data structure according to several embodiments of the invention.

[0014] Figure 3C is another block diagram of an example logical to physical data structure according to several embodiments of the present invention.

[0015] Figure 4 An example flow diagram illustrating a logical to physical data structure according to several embodiments of the invention. DETAILED DESCRIPTION

[0016] The present invention includes apparatus and methods related to logical-to-physical data structures. An example apparatus includes a controller coupled to a non-volatile memory (NVM) device. The controller may be configured to cause a logical block address (LBA) to be stored in a first logical-to-physical (L2P) data structure in the NVM device and a physical block address (PBA) to be stored in a second L2P data structure in the NVM device. The first L2P data structure and the second L2P data structure may have the same size associated therewith.

[0017] A computing system, such as a personal computer, laptop computer, tablet computer, phablet, smart phone, Internet of Things (IoT) enabled device, etc., may include one or more memory devices (e.g., memory resources) to store data and / or instructions associated with the computing system. As used herein, "IoT enabled devices" include physical devices, vehicles, household appliances, and other devices embedded with electronics, software, sensors, actuators, and / or network connectivity that enables such objects to connect and exchange data. Examples of IoT enabled devices include wearable technology, smart home devices, smart shopping systems, and surveillance devices, as well as other cyber-physical systems. In addition, a computing system may include one or more processing resources to execute system software, such as an operating system, to provide common services to applications running on the computing system. Examples of operating systems include wait.

[0018] During operation, a computing system may store data (e.g., commands, firmware, software, computer code, metacode, framework files, etc.) in one or more memory devices. Such memory devices may be volatile or non-volatile (e.g., persistent). Examples of non-volatile memory (NVM) devices may include persistent flash memory resources such as NAND flash memory, NOR flash memory, etc., and emerging memory devices. Emerging memory (EM) technologies may include phase change memory (PCM), magnetoresistive random access memory (MRAM), resistive random access memory (ReRAM), ferroelectric RAM (FeRAM), and / or 3D XPoint memory, which may improve memory-related latency compared to other memory technologies. Volatile memory devices may include memory devices that require power to maintain stored information. Examples of volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM), among others.

[0019] The data stored by the memory device(s) may reside in physical locations of the memory device(s). The physical location (e.g., physical block address) where the data is stored may be mapped to a logical block address (LBA). The logical block address may be stored in a data structure and may be called to access a physical block address (PBA) where the data is stored. For example, to access (e.g., read, write, erase, etc.) data, the LBA may be called, which in turn directs the computing system to the PBA. As used herein, a "data structure" refers to a specialized format for organizing and / or storing data, which may or may not be organized in rows and columns. Examples of data structures include arrays, files, records, tables, trees, linked lists, hash tables, etc.

[0020] Logical block addressing is a scheme that can be used by a host to identify logical sectors of data. For example, each logical sector can correspond to a unique logical block address (LBA). In addition, an LBA can also correspond to a physical address. A logical sector of data can be a number of bytes of data (e.g., 256 bytes, 512 bytes, or 1,024 bytes). However, embodiments are not limited to these examples.

[0021] The mapping between LBAs and PBAs may be stored in a logical-to-physical (L2P) data structure (e.g., an L2P address data structure). In some methods, the L2P data structure is arranged in a tree structure. An example tree structure for storing an L2P data structure according to some methods may include a P-level L2P table, where P is a non-zero integer. A simple example according to some methods may include a 2-level L2P table. A first-level table may contain the address of a second-level table, which may be referred to as a "segment". In some methods, each segment may include an L2P table for a small range of contiguous LBAs (e.g., 1024 LBAs).

[0022] In some approaches, a tree-structured L2P data structure as described above is utilized to simplify searching for a given LBA during operation of a computing device. Further, in some approaches, a tree-structured L2P data structure as described above is utilized to minimize the size associated with the first-level table. For example, if the size associated with the first-level table remains within a certain size threshold, the first-level table may be stored in an SRAM and / or DRAM portion of a storage controller of a computing system.

[0023] However, methods in which a tree-structured L2P data structure is used may suffer from various disadvantages. For example, as the storage density of a memory device increases, methods using a tree-structured L2P data structure utilize additional levels in the tree. For example, as the storage density of a memory device increases, the number of levels in the tree-structured L2P data structure may increase accordingly. In some methods, this may result in longer delays for L2P lookups and / or translations. In addition, as the number of levels of the tree increases, the complexity of management (e.g., the complexity of the memory management scheme) also increases. The increase in latency and / or the increase in management complexity may correspond to changes in the L2P table that are propagated across each level of the tree.

[0024] In contrast, embodiments herein describe L2P table structures that may be used in applications where non-volatile memory devices (e.g., emerging NVM devices) and flash memory devices (e.g., NAND memory devices) are provided as part of a memory device. In some embodiments, the L2P data structures described herein may include L2P mapping tables. A first L2P mapping table may include logical block addresses and a second L2P mapping table may include physical block addresses. In some embodiments, the first L2P mapping table (e.g., an L2P mapping table that includes logical block addresses) and the second L2P mapping table (e.g., an L2P mapping table that includes physical block addresses) may be the same size (e.g., they may include the same number of rows and the same number of columns).

[0025] In some embodiments, a plurality of hash functions (e.g., two hash functions) may be used to access the first L2P mapping table. Then, an index located in the first L2P mapping table using the hash function may be used to locate the physical location of the corresponding physical block address in the second L2P mapping table. In some embodiments, after locating the physical location of the corresponding physical block address in the second L2P mapping table, the physical block address may be written to or read from the physical location in the second L2P mapping table.

[0026] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part of the invention and in which one or more embodiments of the invention may be practiced are shown by way of illustration. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the invention, and it is understood that other embodiments may be utilized and process changes, electrical changes, and / or structural changes may be made without departing from the scope of the invention. As used herein, designators such as "N" and the like, especially relative to reference numerals in the drawings, indicate that a number of specific features so designated may be included. As used herein, "several" specific things refer to one or more such things (e.g., a number of memory arrays may refer to one or more memory arrays). "Multiple" is intended to refer to more than one such thing.

[0027] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the drawing and the remaining digits identify the element or component in the drawing. Similar elements or components between different figures may be identified by using similar numerals. For example, 110 may be Figure 1 The component "10" is referred to in the figure, and similar components are Figure 2 210. It will be appreciated that the elements shown in the various embodiments herein may be added, exchanged and / or eliminated in order to provide several additional embodiments of the present invention. In addition, it will be appreciated that the proportions and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the present invention and should not be considered limiting.

[0028] Figure 1 is a functional block diagram of an apparatus in the form of a computing system 100 including a memory system 104 according to several embodiments of the invention. As used herein, an "apparatus" may refer to, but is not limited to, any one or combination of various structures such as, for example, a circuit or circuitry, a die or dies, a module or modules, a device or devices, or a system or systems.

[0029] The memory system 104 may be, for example, a solid state drive (SSD). Figure 1 In the embodiment described in, the memory system 104 includes a host interface 106, a memory (e.g., a plurality of memory devices 110-1, 110-2, ..., 110-N) (e.g., a solid-state memory device), and a controller 108 (e.g., an SSD controller) coupled to the physical host interface 106 and the memory devices 110-1, 110-2, ..., 110-N.

[0030] The memory devices 110-1, 110-2, ..., 110-N may include, for example, a plurality of non-volatile memory arrays (e.g., arrays of non-volatile memory cells). For example, the memory devices 110-1, 110-2, ..., 110-N may include a plurality of non-volatile memory arrays, such as emerging memory arrays and / or flash memory arrays, as described herein in conjunction with Figure 2 Describe in more detail.

[0031] In some embodiments, the memory devices 110-1, ..., 110-N may include an array of several memory cells (e.g., non-volatile memory cells). For example, the array may be a flash memory array having a NAND architecture. However, embodiments are not limited to a particular type of memory array or array architecture. The memory cells may be grouped, for example, into several blocks that include several physical pages of memory cells. In several embodiments, a block refers to a group of memory cells that are erased together as a unit. Several blocks may be included in a plane of memory cells and the array may include several planes. As an example, a memory device may be configured to store 8KB (kilobytes) of user data per page, 128 pages of user data per block, 2048 blocks per plane, and 16 planes per device.

[0032] In operation, for example, data may be written to and / or read from memory devices of a memory system (e.g., memory devices 110-1, ..., 110-N of memory system 104) as pages of data. Thus, pages of data may be referred to as the data transfer size of a memory system. Data may be transferred to or from a host 102 in segments of data referred to as sectors (e.g., host sectors). Thus, sectors of data may be referred to as the data transfer size of a host. In some embodiments, a NAND block may be referred to as an erase block, where a block is a unit of erase and a page is a measure of read and / or write.

[0033] The host interface 106 may be used to communicate information between the memory system 104 and another device such as the host 102. The host 102 may include a memory access device (e.g., a processor). As used herein, a "processor" may mean a plurality of processors, such as a parallel processing system, a number of coprocessors, etc. Example hosts may include personal laptop computers, desktop computers, digital cameras, digital recording and playback devices, mobile (e.g., smart) phones, PDAs, memory card readers, interface hubs, IoT-enabled devices, etc. The host 102 may include a system motherboard and / or backplane and may include a number of processing resources (e.g., one or more processors, microprocessors, etc.). The system 100 may include separate integrated circuits or both the host 102 and the memory system 104 may be on the same integrated circuit. The system 100 may be, for example, a server system and / or a high performance computing (HPC) system and / or portions thereof.

[0034] For clarity, system 100 has been simplified to focus on features that are particularly relevant to the present invention. Memory system 104 may include one or more memory resources, such as a DRAM array (e.g., a 2T2C DRAM array, a 3T DRAM array, etc.), a FeRAM, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash memory array, a 3D Xpoint memory, a NOR flash memory array, and / or a storage subsystem including, for example, a controller, a 3D Xpoint memory portion, and a NAND flash memory portion.

[0035] The host interface 106 may be in the form of a standardized physical interface. For example, when the memory system 104 is used for information storage in the computing system 100, the host interface 106 may be a Serial Advanced Technology Attachment (SATA) physical interface, a Peripheral Component Interconnect Express (PCIe) physical interface, or a Universal Serial Bus (USB) physical interface, as well as other physical connectors and / or interfaces. However, in general, the host interface 106 may provide an interface for transferring control, address, information (e.g., data), and other signals between the memory system 104 and a host (e.g., the host 102) having a receiver compatible with the host interface 106.

[0036] Controller 108 may include, for example, control circuitry and / or logic (e.g., hardware and firmware). Controller 108 may be included on the same physical device (e.g., the same die) as memories 110-1, 110-2, ..., 110-N. For example, controller 108 may be an application specific integrated circuit (ASIC) coupled to a printed circuit board including physical host interface 106 and memories 110-1, 110-2, ..., 110-N. Alternatively, controller 108 may be included on a separate physical device communicatively coupled to a physical device including memories 110-1, 110-2, ..., 110-N. In several embodiments, components of controller 108 may be distributed across multiple physical devices (e.g., some components on the same die as memories, and some components on different dies, modules, or boards) as a distributed controller.

[0037] Controller 108 may communicate with memory devices 110-1, 110-2, ..., 110-N to sense (e.g., read), program (e.g., write), and / or erase information, among other operations. Controller 108 may have circuitry that may be a number of integrated circuits and / or discrete components. In several embodiments, the circuitry in controller 108 may include control circuitry for controlling access across memory devices 110-1, 110-2, ..., 110-N and / or circuitry for providing a translation layer (e.g., a flash memory translation layer) between host 102 and memory system 104.

[0038] The controller 108 may control the operation of each respective memory device 110-1, 110-2, ..., 110-N as a dedicated area (e.g., a block-addressed portion) of an L2P data structure (e.g., configuring a portion of each respective memory device 110-1, ..., 110-N to store one or more L2P data structures, as described herein in conjunction with Figure 2 For example, a first portion of each respective memory device 110-1, 110-2, ..., 110-N may be configured to store a first L2P data structure, and a second portion of each respective memory device 110-1, 110-2, ..., 110-N may be configured to store a second L2P data structure.

[0039] The first portion of each respective memory device 110-1, 110-2, ..., 110-N may be, for example, a first plurality of blocks (eg, physical blocks) of memory cells in each respective memory, as will be further described herein (eg, in conjunction with Figure 1 ), and may be referred to herein as a first portion of memory. Additionally, the portion of each respective memory device 110-1, 110-2, ..., 110-N includes a second plurality of blocks, a third plurality of blocks, and so on.

[0040] The second portion of each respective memory 110-1, 110-2, ..., 110-N may be, for example, a second plurality of blocks (eg, physical blocks) of memory cells in each respective memory, as will be described herein (eg, in conjunction with Figure 2 ) is further described. The controller 108 may cause one or more L2P data structures (e.g., Figure 2 The L2P data structures 216-1, ..., 216-N) illustrated in FIG. 1 are stored in respective memory devices 110-1, ..., 110-N.

[0041] Figure 1The embodiments described in the drawings may include additional circuitry, logic, and / or components that are not described in order to avoid obscuring the embodiments of the invention. For example, the memory system 104 may include address circuitry to latch address signals provided on the I / O connector by the I / O circuitry. The address signals may be received and decoded by the row decoder and the column decoder to access the memories 110-1, 110-2, ..., 110-N.

[0042] Figure 2 is a block diagram of an apparatus in the form of a memory system according to several embodiments of the present invention. Figure 2 As illustrated in FIG. 2 , controller 208 may be coupled to memory device 210. Controller 208 may be similar to Figure 1 , and the memory device 210 may be similar to Figure 1 , 110-N as described in the accompanying drawings. Memory device 210 may include NVM device 212 and flash memory device 214. Controller 208, memory device 210, NVM device 212 and / or flash memory device 214 may be individually considered to be "apparatus".

[0043] NVM device 212 may include a plurality of L2P data structures 216-1, ..., 216-N. Figure 2 216-N, but in at least one embodiment, NVM device 212 may include two distinct L2P data structures 216-1, ..., 216-N; however, embodiments are not limited to two distinct L2P data structures 216-1, ..., 216-N. For example, in at least one embodiment, NVM device 212 may include a first L2P data structure (e.g., L2P data structure 216-1) and a second L2P data structure (e.g., L2P data structure 216-N). However, embodiments are not limited in this regard, and NVM device 212 may include more than two distinct L2P data structures 216-1, ..., 216-N (e.g., three or more distinct L2P data structures).

[0044] The L2P data structures 216-1, ..., 216-N may be configurable to store data corresponding to the L2P addressing scheme. For example, the L2P data structures 216-1, ..., 216-N may be configurable to store an L2P addressing table. In some embodiments, the L2P data structure 216-1 may be an axb table (e.g., an axb tensor or a multi-dimensional array) and the L2P data structure 216-N may be an axb table, where a and b are non-zero integers. In other words, in some embodiments, the L2P data structure 216-1 and the L2P data structure 216-N may include the same number of columns and the same number of rows (e.g., the L2P data structure 216-1 and the L2P data structure 216-N may be the same size). In some embodiments, the controller 208 may be configured to control the storage in the L2P data structures 216-1, ..., 216-N.

[0045] The L2P data structure 216-1 may be similar to the Figure 3B The data structure Λ is described and illustrated in more detail, and the L2P data structure 216-N may be similar to the data structure Λ described and illustrated in detail herein. Figure 3C The data structures II are illustrated and described in more detail. For example, L2P data structure 216-1 may include logical block addresses (LBAs), while L2P data structure 216-N may include physical block addresses (PBAs). Figure 2 The two L2P data structures 216-1 and 216-N illustrated in FIG. 216-1 and 216-N may be related in the following manner: if an LBA is stored at the i-th position (e.g., location) in the L2P data structure 216-1, then the corresponding PBA may be stored in the i-th position of the L2P data structure 216-N. In some embodiments, the LBAs stored in the L2P table 216-1 may be located, written, and / or read by executing multiple hash functions. In a non-limiting example, the LBAs stored in the L2P table 216-1 may be located, written, and / or read by executing two hash functions referred to herein as h and s.

[0046] The hash functions h and s may be functions of an LBA. For simplicity, an LBA may be referred to herein as l. In other words, the first hash function h may be referred to as h(l), and the second hash function may be referred to as s(l). In some embodiments, the first hash function h(l) may correspond to a hash address of LBA l, and the second hash function s(l) may correspond to a hash increment of LBA l, as described in more detail herein in conjunction with Equations 1-7 and Tables 1 and 2.

[0047] In some embodiments, hash functions h and s may be selected so that they are efficiently computable. As used herein, the term "efficiently computable" refers to a function that can be easily implemented in hardware. In addition, hash functions h and s may be selected to have a low probability of collision. The term "low probability of collision" herein refers to a function that may output different hash values ​​after receiving different input values. For example, when h and s have a "low probability of collision", when different LBAs (e.g., different values ​​of l) are used as inputs to the hash functions, each hash function h(l) and s(l) will output different hash values ​​after execution, as described in more detail herein in conjunction with Table 1.

[0048] By using two L2P address tables (e.g., L2P data structure 216-1 and L2P data structure 216-N), the number of data structures (e.g., the levels of trees used in some previous approaches) may be minimized even as the storage density of the memory device 210 increases, compared to some approaches in which L2P data is stored in a multi-level tree structure. For example, embodiments described herein in which two discrete L2P address tables (e.g., first L2P data structure 216-1 and second L2P data structure 216-N) are utilized may reduce the number of data structures (e.g., trees) used in some approaches as the storage density of the memory device 210 increases. However, as described above, embodiments are not limited to two discrete L2P address tables, and the present invention is intended to cover instances in which more than two discrete L2P address tables may be used in conjunction with storing and retrieving logical and physical block addresses.

[0049] By using two discrete L2P address tables (e.g., L2P data structure 216-1 and L2P data structure 216-N), LBAs may be written and / or read using only two operations. For example, in some embodiments, by utilizing hash functions h(l) and s(l), LBAs may be written using only two write operations. As an example, when flash memory device 214 contains less than a threshold number of entries (e.g., when flash memory device 214 is partially filled), embodiments herein allow LBAs to be written to L2P data structure 216-1 using only two write operations. In embodiments where flash memory device 214 contains more than a threshold number of entries, embodiments herein may allow LBAs to be written to L2P data structure 216-1 using only three write operations. Embodiments are not limited in this regard; however, and in some embodiments, based on the number of entries contained in flash memory device 214, more than three write operations may be used to write LBAs to L2P data structure 216-1.

[0050] In some embodiments, the L2P data structure 216-1 may be configured so that it is partially sorted, as described herein in conjunction with Figures 3A to 3CDescribed in more detail. As used herein, "partially ordered" refers to a condition in which the L2P data structure 216-1 reflects a binary relationship between certain elements in the L2P data structure 216-1. For example, certain elements in the L2P data structure 216-1 may include an element that precedes another element in the L2P data structure in terms of ordering 216-1. However, not every element in the L2P data structure 216-1 needs to exhibit the property that one element precedes another element in terms of ordering, and the L2P data structure 216-1 may include several pairs of elements in which neither element in the pair precedes the other elements in the pair in terms of ordering. In some embodiments, the controller 208 may be configured to maintain the L2P data structure 216-1 so that the L2P data structure 216-1 is partially ordered. In conjunction with Figures 3A to 3C The situation where the L2P data structure 216-1 is partially ordered is discussed in more detail.

[0051] The flash memory device 214 may include a flash memory data structure 218. The flash memory data structure 218 may be configurable to store data corresponding to the locations of the PBAs and / or LBAs stored in the L2P data structures 216-1, . . . , 216-N, as described herein in conjunction with Figure 3A In some embodiments, the controller 208 can be configured to control the storage of data corresponding to the location of the PBA and / or LBA in the flash memory data structure 218.

[0052] As discussed above, the flash memory device 214 may include one or more portions of an electronic (e.g., solid-state) non-volatile memory storage device. For example, the flash memory device 214 may include one or more portions of NAND flash memory, NOR flash memory, NVRAM flash memory, etc. The flash memory device 214 may be configured to be written to (or read from) in blocks (or pages), which may be smaller than the amount of storage space available for the entire flash memory device 214. However, in some embodiments, the flash memory device 214 may be written to or read from byte by byte (e.g., locations of the flash memory device 214 may be independently written to or read from).

[0053] In some embodiments, as shown in Equation 1, hash functions h(l) and s(l) may be defined as for n LBASs (where 0≤n≤n-1) and for m PBAs (where m>n)

[0054]

[0055] In Equation 1, the hash function s(l) may be selected such that s(l) is relatively prime to m. As used herein, the term "relatively prime" (or "coprime") describes two integers such that there is no integer greater than 1 that divides the two integers. For example, the integers 12 and 13 are relatively prime because there is no integer greater than 1 that divides both 12 and 13. In contrast, the integers 12 and 14 are not relatively prime because there is an integer greater than 1 that divides both 12 and 14 (e.g., 2).

[0056] In some embodiments, by selecting s(l) so that it is relatively prime to m, each distinct position in the LBA structure Λ (e.g., Figure 3B LBA data table Λ316-1) described in.

[0057] As shown in Equation 2, the L2P data structure 216-1 (eg, Figure 3B 216-1) and L2P data structure 216-N (e.g., Figure 3B The PBA data table 216-1 illustrated in FIG. 216-2 may include m elements. For example, the L2P data structure 216-1 and the L2P data structure 216-N may be configured such that there is one element m for each PBA.

[0058]

[0059] In some embodiments, L2P data structure 216-1 and L2P data structure 216-N may be empty. For example, at a certain time period, L2P data structure 216-1 and L2P data structure 216-N may not contain data (e.g., L2P data structure 216-1 may not contain LBAs and L2P data structure 216-N may not contain PBAs), as shown by Equation 3:

[0060] Λ i =Π i = -1 for all i (Equation 3)

[0061] Host (for example, this article in Figure 1 The host 102 described in FIG. 2 may write LBA(l) to a location in the L2P data structure 216-1. In some embodiments, there may be a corresponding empty location in the L2P data structure 216-N where PBA(p) may be written. The location in the L2P data structure 216-1 for writing the LBA may be determined using Equation 4:

[0062] i=h(l) (Equation 4)

[0063] In some embodiments, if Λ i= -1, then the i-th position in the L2P data structure 216-1 is empty and the values ​​of the L2P data structure 216-1 and the L2P data structure 216-N may be set as shown in the equation

[0064] As shown in Formula 5:

[0065]

[0066] In contrast, if the i-th position in the L2P is occupied, as shown in Equation 6, then a conflict may occur. As used herein, a "conflict" is a scenario in which the position in the L2P data structure 216-1 determined by the hash function h(l) already contains a different LBA than l. When a conflict is detected, the new LBA cannot be written above the existing LBA in the L2P data structure 216-1. Instead, if a conflict is detected, a second hash function s(l) may be used to determine a different position in the L2P data structure 216-1 for writing the LBA.

[0067] Λ i =l′≠l (Equation 6)

[0068] Combined with the following Figures 3A to 3C Writing LBAs to L2P data structure 216-1 and writing PBAs to L2P data structure 216-N are further described.

[0069] Figure 3A is a block diagram of a flash memory data structure 218 according to several embodiments of the present invention. A flash memory device may be similar to Figure 2 The flash memory device 214 described in FIG. Figure 3A As shown in FIG. 1 , the flash memory data structure 318 may include multiple locations (e.g., Figure 2 214 as described in the description of the flash memory device storage location of the flash memory device 214). In addition, as Figure 3A As shown in FIG. 3 , the flash memory data structure 318 shows a plurality of steps (eg, step 0, ..., step 4), which will be described below by way of example. For example, Figure 3A Shows the status of the flash memory device at multiple steps.

[0070] exist Figure 3A In the example, some locations may be free, valid, or invalid. These states may change as time increases and data is written to the flash memory device (e.g., as data is written to the flash memory data structure 318). Figure 3AAs illustrated in , empty locations (e.g., locations having no corresponding data stored therein) are indicated as white boxes. Locations containing valid data (e.g., the latest version of the content associated with a given LBA) are indicated with a single hash pattern, and invalid locations (e.g., locations containing data that is no longer valid to the host) are indicated by cross-hatching. For example, at step 0, the location corresponding to index 0 is valid because it contains the latest version of the data associated with LBA 2. In contrast, at step 3, the location corresponding to index 0 is invalid because LBA 2 has been updated by the host and the latest content is now located in location 3.

[0071] Figure 3B is a block diagram of an example L2P data structure according to several embodiments of the present invention. Figure 3B The L2P data structure 316-1 described in Figure 2 The L2P data structure 216-1 described in FIG. Figure 3B As shown in FIG. 1 , the L2P data structure 316-1 may include multiple locations (e.g., Figure 2 216-1). In addition, as Figure 3B As shown in FIG. 3 , L2P data structure 316-1 shows a plurality of steps (eg, step 0, ..., step 4), which will be described below by way of example. For example, Figure 3B The evolution of the L2P data structure 316-N for multiple steps is shown.

[0072] Figure 3C is another block diagram of an example L2P data structure according to several embodiments of the present invention. Figure 3C The L2P data structure 316-N described in Figure 2 The L2P data structure 216-N described in FIG. Figure 3C As shown in FIG. 1 , L2P data structure 316-N may include multiple locations (e.g., Figure 2 216-N as described in the L2P data structure 216-N). In addition, Figure 3C As shown in FIG. 3 , L2P data structure 316-N shows a plurality of steps (eg, step 0, ..., step 4), which will be described below by way of example. For example, Figure 3C The evolution of the L2P data structure 316-N for multiple steps is shown.

[0073] In the following non-limiting example, we assume that there are 8 PBAs (eg, m=8) and 6 LBAs (eg, n=6). An example of two hash functions h(l) and s(l) for this example is shown in Equation 7:

[0074]

[0075] Although the modulo operation shown in Equation 7 shows a divisor of 8, embodiments are not limited thereto, and h(l) and s(l) shown in Equation 7 may have a divisor different from 8. For example, a divisor x, where x is an integer, may be used in place of 8 in Equation 7. The values ​​generated by the two hash functions h(l) and s(l) for an example where m=8 and n=6 are shown in Table 1:

[0076] LBA h(l) s(l) 0 0 3 1 6 5 2 4 7 3 2 1 4 0 3 5 6 5

[0077] Table 1

[0078] Continuing with this example, the host (for example, Figure 1 The host 102 described in ) may write the LBA sequence to a memory device (e.g., Figure 2 In some embodiments, the sequence of steps (e.g., Figures 3A to 3C The LBA sequence is written as shown in step 0, ..., step 4). An example sequence of LBAs may be the following LBA sequence shown in Table 2:

[0079] Step 0 Step 1 Step 2 Step 3 Step 4 2 4 5 2 0

[0080] Table 2

[0081] exist Figures 3A to 3C At step 0 shown in , the host may attempt to write an LBA having a corresponding value of 2 (as shown in Table 2). Since this is the first time the host has attempted to write an LBA to the memory device, there is an empty block in L2P data structure 316-N corresponding to the empty PBA block at 0. Using Equation 4, i=h(2)=4. Since Λ4 is empty (e.g., there is no previously stored LBA in the location corresponding to Λ4), the controller may cause Λ4=2 and Π4=0 to be set, as shown in Table 2. Figure 3B and 3C In addition, since the flash memory data structure 318 does not contain an entry at step 0, the LBA value 2 is written to the location of the flash memory data structure 318 corresponding to the index 0 at step 0, as shown in FIG. Figure 3A As shown in .

[0082] exist Figures 3A to 3C At step 1 shown in FIG. 2 , the host may attempt to write an LBA having a corresponding value of 4 (as shown in Table 2). Figure 3C As shown in FIG. 4 , there is an empty block in L2P data structure 316-N corresponding to the empty PBA block at 1. Using Equation 4, i=h(4)=0. Since Λ0 is empty (e.g., there is no previously stored LBA in the position corresponding to Λ0), the controller may cause Λ0=4 and Π0=1 to be set, as shown in FIG. Figure 3B and 3C In addition, since the flash memory data structure 318 does not contain an entry at step 1, the LBA value 4 is written to the location in the flash memory data structure 318 corresponding to the index 1 at step 1, as shown in FIG. Figure 3A As shown in .

[0083] exist Figures 3A to 3C At step 2 shown in FIG. 2 , the host may attempt to write an LBA having a corresponding value of 5 (as shown in Table 2). Figure 3C As shown in FIG. 4 , there is an empty block in L2P data structure 316-N corresponding to the empty PBA block at 2. Using Equation 4, i=h(5)=6. Since Λ6 is empty (e.g., there is no previously stored LBA in the position corresponding to Λ6), the controller may cause Λ6=6 and Π6=2 to be set, as shown in FIG. Figure 3B and 3C In addition, since the flash memory data structure 318 does not contain an entry at step 2, the LBA value 5 is written to the location of the flash memory data structure 318 corresponding to the index 2 at step 2, as shown in FIG. Figure 3A As shown in .

[0084] exist Figures 3A to 3C At step 3 shown in FIG. 2 , the host may attempt to update the content of the LBA having a corresponding value of 2 (as shown in Table 2). Figure 3C As shown in FIG. 3 , there is an empty block in L2P data structure 316-N corresponding to the empty PBA block at 3. Using Equation 4, i=h(2)=4. Since Λ4=2, the correct LBA value (e.g., value 2) is stored in the location corresponding to Λ4=2. In this case, the PBA can be updated to correspond to Figure 3C For example, in some embodiments, the controller may cause Λ4=2 and Π4=3 to be set, such as Figure 3B and 3C In this example, the contents of the PBA corresponding to PBA block 3 are now valid. In addition, since the flash memory data structure 318 does not contain an entry at step 3, the LBA value 2 is written to the location in the flash memory data structure 318 corresponding to index 3 at step 3, as shown in FIG. Figure 3A As shown in .

[0085] exist Figures 3A to 3C At step 4 shown in FIG. 2 , the host may attempt to write the contents of an LBA having a corresponding value of 0 (as shown in Table 2). Figure 3C, there is a free block in L2P data structure 316-N corresponding to the free PBA block at 4. Using Equation 4, i=h(0)=0. Since Λ0=4, a conflict may occur. In some embodiments, when a conflict occurs, the controller may be configured to maintain the conflicting LBAs in a particular order (e.g., the controller may be configured to maintain L2P data structure 316-1 so that it is partially sorted). For example, when a conflict occurs, the controller may be configured to maintain the conflicting LBAs in L2P data structure 316-1 in ascending order.

[0086] Following the example, the LBA stored in Λ0=4, which is a value greater than the new LBA 0 (from step 4 of Table 2). Therefore, the controller may cause Λ0 to be set to 0 and PBA to be set to 1. Therefore, the controller may cause Λ0=0 and Π0=0 to be set, and cause the new positions of LBA 4 and PBA 1 to be located. In some embodiments, a second hash function s(l) may be used to determine the new position. Using s(l) from Equation 7, s(4)=3, so i+s(4)=0+3=0. Therefore, the controller may be configured to cause Λ3=4 and Π3=1, as Figure 3B and 3C As shown in .

[0087] Combination of the above Figures 3A to 3C The described example is further more fully summarized below in the following example of pseudo code. In the following pseudo code example, initially, L2P data structures 316-1 and 316-N are empty and by setting Λ i =Π i = -1 is initialized for all i∈{0, ..., m-1}, as shown in Equation 3. A first example pseudo-code illustrates an example of writing and / or updating LBA 1 according to several embodiments of the present invention:

[0088]

[0089] In a first operation of the first example pseudo-code, a procedure may be initiated to write (e.g., insert) LBA l with corresponding PBA p. In some embodiments, a second operation may include setting the first hash function h(l) to i, as described in conjunction with Equation 4. A third operation may include setting an indication that the setting is not yet complete to an error, thereby indicating that the procedure continues at a fourth operation.

[0090] The fourth operation may include executing a while loop when the setting has not yet been completed, as described in the fifth to twenty-first operations. In some embodiments, the fifth operation may include determining i is equal to -1, as shown in Equation 3. If Λ i= -1, then the procedure can proceed to the sixth operation, where Λ i Set to 1, as shown in Equation 5. In the seventh operation, Π i is set to p, as shown in Equation 5. If Λ i Set to l and Π i Set to p, then the if loop started at the fifth operation is completed, as shown in the eighth operation.

[0091] At the ninth operation, in response to Λ i The determination that Λ is equal to l initiates the else if then loop, as shown in Equation 5. i is equal to 1, then in the tenth operation, Π i Set to p, as shown in Equation 5. In some embodiments, once Λ i Equal to l and Π i If the setting is set to p, then at the eleventh operation, the setting can be completed. In some embodiments, the ninth to eleventh operations can correspond to the update of L2P data structures 316-1 and 316-N, as described above in conjunction with Figures 3A to 3C As described in step 3 of .

[0092] At the twelfth operation, in response to Λ i >1, and the second else if then loop is started. i >l, at the thirteenth operation, the controller may cause Λ i is set to l', as shown in Equation 6. In some embodiments, l' may correspond to the second position in the L2P data structure 316-1. i Set to p', which may correspond to the second position in the L2P data structure 316-N.

[0093] Since LBA 1 has a value greater than the LBA previously stored in the first position of the L2P data structure 316-1, at the fifteenth operation, Λ i Similarly, at the sixteenth operation, Π i At the seventeenth operation, l' may be set to l, and at the eighteenth operation, p' may be set to p. Finally, at the nineteenth operation, the if loop may end. In some embodiments, the eleventh to nineteenth operations may correspond to detecting conflicts occurring in the L2P data structures 316-1 and 316-N, as described above in conjunction with Figures 3A to 3C As described in step 4 of .

[0094] In response to the completion of the nineteenth operation, i may be set to i+s(l)(mod m) to increment the first hash function by using the second hash function, as described above in conjunction with Figures 3A to 3C Subsequently, the while loop may be terminated at the twentieth operation, and the program may end at the twenty-first operation.

[0095] The second example pseudo-code illustrates an example of reading PBA p corresponding to LBA 1 according to several embodiments of the present invention. In the second example pseudo-code, if the LBA is written (eg, stored) in the L2P data structure 316-1, a PBA value of -1 is returned:

[0096]

[0097]

[0098] In the first operation of the second example pseudo-code, a procedure may be initialized to read (e.g., retrieve) the PBA p associated with the corresponding LBA 1. In some embodiments, the second operation may include setting h(1) to i, as shown in Equation 4. If the setting has not been completed at the third operation, a while loop may be executed at the fourth operation.

[0099] The while loop may include an if then loop at the fifth operation. For example, at the fifth operation, if i = l, then at the sixth operation, Π i Set to p. This corresponds to the location in L2P data structure 316-1 that contains the corresponding entry in L2P data structure 316-N. At the seventh operation, the setting may be completed and the if then loop executed at the fifth operation may terminate.

[0100] If the if then loop executed at the fifth operation has not yet been completed, then at the eighth operation, in response to Λ i Is -1 or whether Λ i >1 and execute the else if then loop. In this case, at the ninth operation, p may be set to -1 and the if then loop executed at the eighth operation may be terminated at the tenth operation.

[0101] At the eleventh operation, the if loop executed at the fifth operation may terminate and at the twelfth operation, i may be set to i+s(l)(mod m) to increment the first hash function by using the second hash function, as described above in conjunction with Figures 3A to 3C At the thirteenth operation, the while loop executed at the fourth operation may terminate and the PBA p may be returned at the fourteenth operation. Finally, at the fifteenth operation, the program may end.

[0102] Figure 4 An example flow chart illustrating a logical-to-physical data structure according to several embodiments of the present invention. At block 422, method 420 may include determining a first logical-to-physical (L2P) data structure (e.g., as described herein in detail in the non-volatile memory device) stored in the non-volatile memory device. Figure 2 In some embodiments, the method 420 may include determining a first location in the first L2P data structure for writing the first LBA by executing a first hash function h(1), as described herein in conjunction with Figures 3A to 3C described.

[0103] At block 424, method 420 may include determining that the first location includes the second LBA. In some embodiments, determining that the first location includes the second LBA may include determining that a conflict has occurred at the first location. The second LBA may have been previously stored in the first location (e.g., the second LBA may have been stored in the first location prior to attempting to store the first LBA in the first location). In some embodiments, method 420 may include determining a first location in the first L2P data structure for writing the first LBA by performing a second hash function s(1), as described herein in conjunction with Figures 3A to 3C described.

[0104] At block 426, method 420 may include writing the first LBA to a second location in the first L2P data structure in response to a determination that the first location includes the second LBA. For example, method 420 may include writing the first LBA to a second location in the first L2P data structure in response to a determination that a conflict has occurred.

[0105] At block 428, method 420 may include writing a physical block address (PBA) corresponding to the first LBA to a second L2P data structure (eg, as described herein in Figure 2 In some embodiments, the second position in the first L2P data structure may correspond to the first position in the second L2P data structure.

[0106] As described above, the first L2P data structure and the second L2P data structure may contain the same number of rows and the same number of columns (e.g., the first L2P data structure may be an axb table and the second L2P data structure may be an axb table, where a and b are non-zero integers). For example, in some embodiments, the first L2P data structure and the second L2P data structure may have the same size.

[0107] In some embodiments, method 420 may further include reading the first LBA from the second location in the first L2P data structure. However, embodiments are not limited thereto, and in some embodiments, such as embodiments in which no conflict is detected and the first LBA is written to the first location in the L2P data structure, the method may further include reading the LBA from the first location in the first L2P data structure.

[0108] In some embodiments, method 420 may further include reading the PBA from a second location in the second L2P data structure. For example, if a conflict is detected and the PBA is written to a second location in the second L2P data structure, method 420 may include reading the PBA from a second location in the second L2P data structure. However, embodiments are not limited thereto, and in some embodiments, such as embodiments where no conflict is detected and the PBA is written to a first location in the second L2P data structure, the method may further include reading the PBA from a first location in the second L2P data structure.

[0109] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present invention is intended to cover adaptations or changes of one or more embodiments of the present invention. It should be understood that the above description has been made in an illustrative and non-restrictive manner. Upon reviewing the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of one or more embodiments of the present invention includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present invention should be determined with reference to the appended claims together with the full scope of equivalents enjoyed by such claims.

[0110] In the foregoing detailed description, some features are grouped together in a single embodiment for the purpose of simplifying the invention. The inventive method should not be interpreted as reflecting an intention that the disclosed embodiments of the invention must use more features than those explicitly recited in each claim. Rather, as reflected in the attached claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the attached claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment.

Claims

1. An apparatus for utilizing a logical to physical data structure, comprising: a controller coupled to a first non-volatile memory device of a first type and a second non-volatile memory device of a second type, wherein the controller is configured to cause: writing the LBAs to a first L2P data structure in the second nonvolatile memory device using a first number of write operations in response to determining that the first nonvolatile memory device contains less than a threshold number of entries; or writing the LBA to the first L2P data structure using a second number of write operations in response to determining that the first nonvolatile memory device contains more than the threshold number of entries; and A physical block address is written into a second L2P data structure in the second non-volatile memory device, wherein the first L2P data structure and the second L2P data structure have the same size associated therewith.

2. The apparatus of claim 1, wherein the first non-volatile memory device is a NAND flash memory device.

3. The apparatus of claim 2, wherein the second non-volatile memory device is a memory device selected from a group consisting of: Phase change memory device; Resistive random access memory devices; Magnetoresistive random access memory devices; and 3D XPoint memory devices.

4. The apparatus of claim 1, wherein the controller is further configured to cause: The LBA is written to a first location of the first L2P data structure based at least in part on execution of a first hash function; and The LBA is written to a second location of the first L2P data structure based at least in part on a determination that execution of the first hash function produced a conflict.

5. The apparatus of claim 4, wherein the controller is further configured to cause a determination that execution of the first hash function produces a conflict based at least in part on a determination that the first location of the first L2P data structure contains an LBA that is different from the LBA to be written into the first location.

6. The apparatus of claim 4, wherein the controller is further configured to cause the LBA to be written into the second location of the first L2P data structure based at least in part on execution of a second hash function.

7. A method for utilizing a logical to physical data structure, comprising: determining a first location in a first L2P data structure stored in a first non-volatile memory (NVM) device for writing a first LBA; Determining that the first location includes a second LBA; writing the first LBA to a second location in the first L2P data structure in response to determining that the first location contains the second LBA; and writing a physical block address corresponding to the first LBA to a location in a second L2P data structure stored in the first NVM device, wherein the second location in the first L2P data structure corresponds to the location in the second L2P data structure; and Wherein the physical block address corresponds to a second location in a second NVM device coupled to the first NVM device.

8. The method of claim 7, wherein the second NVM device is a flash memory device.

9. The method according to claim 7, wherein the method comprises: performing a first number of write operations to write the first LBA into the first L2P data structure in response to the second NVM device having a first number of entries; and A second number of write operations are performed to write the first LBA into the first L2P data structure in response to the second NVM device having a second number of entries.

10. The method of claim 7, wherein the first L2P data structure and the second L2P data structure have the same size.

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