Inter-board synchronous triggering method of microinstruction and microinstruction control test system

Abstract

The invention relates to a microinstruction inter-board synchronous triggering method and a microinstruction control test system, and the method comprises the steps: receiving a synchronous clock signal sent by a communication board card, and starting the cycle counting based on the synchronous clock signal, and obtaining a clock count value; sequentially expanding each test instruction into one or more microinstructions based on the sequence of the plurality of test instructions pre-loaded to the cache; receiving a starting instruction sent by the communication board card, wherein the starting instruction comprises a starting count value; the starting count value is compared with the clock count value, when the clock count value is equal to the starting count value for the first time, operation of the microinstruction is triggered, and the problems that communication time needs to be spent and the real-time performance is poor when the microinstruction is synchronously triggered are solved.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and in particular to a microinstruction inter-board synchronous triggering method and a microinstruction control test system. Background Art

[0002] Semiconductor chip ATE (Automatic Test Equipment) is used to detect the integrity of the functions and performance of integrated circuits. It is an important device to ensure the quality of integrated circuits in the integrated circuit manufacturing process. Its integrated circuit testing usually requires four steps: test program design, program compilation, vector loading, and test execution, and the PATTERN (test vector) file runs through each step of the integrated circuit test. The main content of the PATTERN file is the symbol combination of the input level and the expected output level, and also contains microinstructions to achieve certain complex functions. During the test process, multiple resource boards need to operate in coordination, and it is required that the microinstructions can be triggered synchronously between different boards. However, the existing triggering method is usually to parse the trigger (TRIGGER) microinstruction when running PATTERN on the digital board (DIO), and send the TRIGGER message to the communication bus. After receiving the instruction, other boards complete the corresponding operation. This method takes communication time and has poor real-time performance. Summary of the invention

[0003] In this embodiment, a microinstruction inter-board synchronous triggering method and a microinstruction control test system are provided to solve the problem in the related art that the multi-board microinstruction synchronous triggering requires communication time and has poor real-time performance.

[0004] In the first aspect, a method for inter-board synchronous triggering of a microinstruction is provided in the present embodiment, the method is applied to a resource board in a microinstruction control test system, the system comprising a host computer, a communication board connected to the host computer for communication, and a plurality of resource boards connected to the communication board, the method comprising: Receiving a synchronous clock signal sent by the communication board, and starting cyclic counting based on the synchronous clock signal to obtain a clock count value; Based on the order of the plurality of test instructions preloaded into the cache, sequentially expanding each test instruction into one or more microinstructions; Receiving a startup instruction sent by the communication board, wherein the startup instruction includes a startup count value; The startup count value is compared with the clock count value, and when the clock count value is equal to the startup count value for the first time, the execution of the microinstruction is triggered.

[0005] In some embodiments, the microinstruction includes an execution cycle number, and when the clock count value is equal to the start count value for the first time, triggering the execution of the microinstruction includes: When the clock count value is equal to the start count value for the first time, counting starts based on the synchronous clock signal and a preconfigured execution cycle factor to obtain an execution cycle count value; Obtaining the execution cycle sequence number of each of the microinstructions in sequence and comparing it with the execution cycle count value; When the execution cycle sequence number is equal to the execution cycle count value, the microinstruction is executed until all microinstructions in the cache are executed.

[0006] In some embodiments, the microinstruction further includes an event type and event parameters, and executing the microinstruction includes: Based on the event type and the event parameters, obtaining instruction information of the microinstruction; Based on the event parameters, determining a sending object of the microinstruction; The instruction information is sent to the sending object.

[0007] In some embodiments, sending the instruction information to the sending object includes: In the case where the sending object is a waveform generator or a waveform collector, performing clock domain conversion on the instruction information and distributing it to the waveform generator or the waveform collector; When the sending object is a controller, the instruction information is sent to the controller based on a communication protocol with the controller.

[0008] In some embodiments, obtaining the instruction information of the microinstruction based on the event type and the event parameter includes: In the case where the event type of the microinstruction is instruction loading, reading corresponding instruction information from a memory based on a loading address in the event parameter; When the event type of the microinstruction is not instruction loading, corresponding instruction information is generated based on the event parameters.

[0009] In some embodiments, the microinstruction further includes a valid channel, and when the execution cycle sequence number is equal to the execution cycle count value, executing the microinstruction includes: Determining whether the microinstruction is valid for the resource board based on the valid channel of the microinstruction; If valid, executing the microinstruction; In the invalid case, the microinstruction is ignored and the next microinstruction is fetched.

[0010] In some embodiments, the test instruction includes a valid channel, a row difference, an operation code and function information, and the sequence of the multiple test instructions preloaded into the cache is based on the order of each test instruction to be expanded into one or more microinstructions in sequence, including: Based on the operation code and the function information, obtaining the number of execution cycles corresponding to the test instruction; Based on the row difference and the number of execution cycles, obtaining the execution cycle sequence number of each microinstruction corresponding to the test instruction; Based on the valid channel, execution cycle number, operation code and function information, one or more microinstructions corresponding to the test instruction are generated.

[0011] In some embodiments, when the execution cycle sequence number is equal to the execution cycle count value, executing the microinstruction includes: Determining whether the microinstruction is a delay compensation microinstruction, wherein the delay compensation microinstruction includes a delay cycle number; If so, obtaining the difference between the execution cycle number corresponding to each microinstruction after the delay compensation microinstruction and the delay cycle number; The difference is compared with the execution cycle count value, and when the difference is equal to the execution cycle count value, the corresponding microinstruction is executed.

[0012] In some embodiments, before sequentially expanding each test instruction into one or more microinstructions based on the order of the multiple test instructions preloaded into the cache, the method further includes: Based on the received storage addresses and lengths of the preload instructions and the test instructions, the plurality of test instructions are sequentially read into the cache; Setting a preload flag based on the length of the test instruction, the number of test instructions read into the cache, and the maximum storage quantity of the cache; When the value of the preload flag is equal to a preset value, each test instruction is sequentially expanded into one or more microinstructions based on the order of the test instructions in the cache.

[0013] In a second aspect, a microinstruction control test system is provided in the present embodiment, the system comprising a host computer, a communication board connected to the host computer for communication, and a plurality of resource boards connected to the communication board, the resource board comprising a microinstruction controller, the microinstruction controller comprising: A service decoding module, used for receiving the synchronous clock signal and the start instruction sent by the communication board and forwarding them to the microinstruction control module, wherein the start instruction includes a start count value; A test instruction cache module, for sequentially expanding each test instruction into one or more microinstructions and sending the microinstructions to the microinstruction control module based on the order of the preloaded multiple test instructions; The microinstruction control module is used to start cyclic counting based on the synchronous clock signal to obtain a clock count value; and compare the start count value with the clock count value, and when the clock count value is equal to the start count value for the first time, trigger the execution of the microinstruction.

[0014] In some embodiments, the microinstruction controller further includes a parameter control module, and the microinstruction control module is further used to: When the clock count value is equal to the start count value for the first time, counting starts based on the synchronous clock signal and a preconfigured execution cycle factor to obtain an execution cycle count value; Obtaining the execution cycle sequence number of each of the microinstructions in sequence and comparing it with the execution cycle count value; When the execution cycle sequence number is equal to the execution cycle count value, determining whether the microinstruction is valid for the resource board based on the valid channel of the microinstruction; If valid, sending the microinstruction to the parameter control module; In the invalid case, the microinstruction is ignored and the next microinstruction is fetched.

[0015] In some embodiments, the microinstruction controller further includes a loading control module and a parameter selection module, and the microinstruction includes an event type and an event parameter. The parameter control module is used for parsing the corresponding load instruction based on the microinstruction and sending it to the load control module when the event type in the microinstruction is instruction loading; In the case where the event type of the microinstruction is not instruction loading, generating instruction information of the microinstruction based on the event type and the event parameter, and sending the instruction information to the parameter selection module; The loading control module is used to read corresponding instruction information based on the loading instruction and send it to the parameter selection module.

[0016] In some of the embodiments, the microinstruction controller further includes a cross-clock domain control module and a controller transmission module. The parameter selection module is used to send the instruction information to the cross-clock domain control module or the controller transmission module based on the event type of the instruction information; The cross-clock domain control module is used to perform clock domain conversion on the instruction information and distribute it to the waveform generator or waveform collector; The controller transmission module is used to send the instruction information to the controller based on the communication protocol with the controller.

[0017] In some of the embodiments, the microinstruction controller further includes an instruction request module, wherein the instruction request module is used to: Based on the storage address and length of the received preloading instructions and test instructions, multiple test instructions are read into the test instruction cache module in sequence; based on the length of the test instructions, the number of test instructions read into the test instruction cache module and the maximum storage quantity of the test instruction cache module, a preloading flag is set.

[0018] Compared with the related art, in the inter-board synchronous triggering method of microinstructions provided in this embodiment, the resource board receives the synchronous clock signal sent by the communication board, and starts the cyclic counting based on the synchronous clock signal to obtain the clock count value, which provides a unified counting time for multiple resource boards to realize the synchronous operation of microinstructions; by sorting multiple test instructions pre-loaded into the cache, each test instruction is sequentially expanded into one or more microinstructions, and each microinstruction is sequentially stored in the cache according to the execution cycle sequence number generated during the expansion, so as to prepare for subsequent execution; the execution of the microinstruction is started by receiving the start instruction sent by the communication board, and the start instruction receiving time of each resource board is not synchronized; by comparing the start count value in the start instruction with the clock count value, when the clock count value is equal to the start count value for the first time, the operation of the microinstruction is triggered, and each resource board determines the triggering time of the microinstruction according to the same start count value, so as to ensure that each resource board starts to run the microinstruction at the same time, without spending communication time, thereby improving the control accuracy, synchronization accuracy and real-time operation of the instruction.

[0019] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 is a structural block diagram of a microinstruction control test system of some embodiments of the present application; Figure 2 is a flow chart of a method for synchronously triggering microinstructions between boards according to some embodiments of the present application; Figure 3 is a flowchart of microinstruction expansion of some embodiments of the present application; Figure 4is a flow chart of triggering microinstruction execution in some embodiments of the present application; Figure 5 is a flowchart of microinstruction execution of some embodiments of the present application; Figure 6 is a flow chart of microinstruction validity determination in some embodiments of the present application; Figure 7 is a flow chart of microinstruction delay compensation in some embodiments of the present application; Figure 8 is a flowchart of test instruction preloading in some embodiments of the present application; Fig. 9 is a structural block diagram of a microinstruction control test system of some embodiments of the present application; Fig.10 is a structural block diagram of a microinstruction controlled test system in some other embodiments of the present application; Fig.11 is a structural block diagram of a microinstruction control test system in some other embodiments of the present application; Fig.12 is a structural block diagram of a microinstruction control test system in some other embodiments of the present application; Fig.13 It is a structural block diagram of a microinstruction control test system of some preferred embodiments of the present application. DETAILED DESCRIPTION

[0021] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0023] The inter-board synchronous triggering method of microinstructions provided in the embodiment of the present application can be executed in a resource board in a microinstruction control test system. Figure 1 is a structural block diagram of a microinstruction control test system in some embodiments of the present application. Figure 1 As shown, the microinstruction control test system includes a host computer 10, a communication board 20 connected to the host computer 10, and a plurality of resource boards 30 (three are shown in the figure) connected to the communication board 20. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned microinstruction control test system. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0024] In this embodiment, a microinstruction inter-board synchronous triggering method is provided. Figure 2 is a flow chart of a method for synchronously triggering microinstructions between boards in some embodiments of the present application, such as Figure 2 As shown, the process includes the following steps: Step S201, receiving a synchronous clock signal sent by a communication board, and starting cyclic counting based on the synchronous clock signal to obtain a clock count value.

[0025] In the microinstruction control test system, the resource board is used to provide different types of test resources to the chip under test, and the types of multiple resource boards can be the same or different. The communication board connects the host computer and the resource board, and is used to send the host computer's test instructions and configuration information to the corresponding resource board, and send the resource board's status information to the host computer. The communication board and the resource board can be located in different slots of the test machine and are electrically connected through the backplane.

[0026] To ensure the coordinated operation of multiple resource boards, the communication board sends a synchronous clock signal MASTER_CLK to multiple resource boards as the clock reference for the synchronous operation of multiple resource boards. After all resource boards are powered on, the communication board starts to send the synchronous clock signal MASTER_CLK and sets the effective time of the synchronous clock signal. Specifically, the first rising edge of MASTER_CLK can be effective.

[0027] When each resource board receives the first rising edge of the synchronous clock signal, it starts cyclic counting, and the maximum value of the cyclic counting can be preset.

[0028] Furthermore, when the clock frequency of the synchronous clock signal needs to be changed, the output of the synchronous clock signal can be stopped first. When each resource board fails to receive the synchronous clock signal within the preset time period, the loop counter is cleared until the first rising edge of the synchronous clock signal is received next time and counting starts. At this time, it can be ensured that all boards are synchronized in counting time.

[0029] Step S202 , based on the order of the multiple test instructions preloaded into the cache, sequentially expand each test instruction into one or more microinstructions.

[0030] Multiple test instructions (PATTERN) to be executed are pre-loaded into the cache of the resource board, which may be a FIFO. Specifically, a preset number of test instructions may be loaded from the DDR into the FIFO based on a pre-load instruction, which includes the address and length of the test instruction.

[0031] The test instructions of this embodiment may only include instructions for controlling the execution time and execution order of statements, and instructions for controlling external devices, without including specific chip pin IO operation information. Specifically, the instructions for controlling the execution time and execution order of statements may include REPAET (single-line loop), LOOP (block loop), ENDLOOP, and TRIG (trigger function test) statements, and the instructions for controlling external devices may include EVENT_AD statements. Among them, EVENT_AD statements are a collection of multiple microinstructions.

[0032] According to the order of multiple test instructions in the cache, each test instruction is expanded in turn. For example, the test instruction executed in a loop can be expanded into multiple repeated microinstructions according to the number of executions. The EVENT_AD statement can also be decoded based on preset rules to obtain the corresponding microinstructions.

[0033] Step S203, receiving a start instruction sent by the communication board, where the start instruction includes a start count value.

[0034] When the microinstruction is ready to start running, the host computer sends a start instruction to the communication board, and the communication board forwards the start instruction to each resource board. The time when each resource board receives the start instruction may not be exactly the same.

[0035] In some embodiments, a counter may be provided on the communication board, which also counts based on the synchronous clock signal MASTER_CLK, and uses the count value when receiving the start instruction as the start count value, adds it to the start instruction, and forwards it to each resource board.

[0036] Step S204, comparing the startup count value with the clock count value, when the clock count value is equal to the startup count value for the first time, triggering the execution of the microinstruction.

[0037] Each resource board compares the startup count value with its own clock count value, and when the clock count value is equal to the startup count value for the first time, the microinstruction is triggered to run. Since the clock counts of each resource board are executed in a synchronous cycle, the time when the clock count value of each resource board is equal to the startup count value for the first time is the same, and the microinstruction is triggered to run synchronously, realizing the synchronous running of the microinstructions.

[0038] In some embodiments, the startup count value is equal to the count value when the communication board receives the startup instruction. Therefore, when each resource board receives the startup instruction, the clock count value of each resource board must be greater than the startup count value. At this time, when the next cycle count of each resource board reaches the startup count value, the execution of the microinstruction is triggered.

[0039] Through steps S201 to S204, by receiving the synchronous clock signal sent by the communication board, and starting the cyclic counting based on the synchronous clock signal, the clock count value is obtained, and a unified counting time is provided for multiple resource boards to realize the synchronous operation of microinstructions; by sorting based on multiple test instructions pre-loaded into the cache, each test instruction is sequentially expanded into one or more microinstructions, and each microinstruction is sequentially stored in the cache according to the execution cycle sequence number generated when it is expanded, so as to prepare for subsequent execution; the execution of the microinstruction is started by receiving the start instruction sent by the communication board, and the start instruction receiving time of each resource board is not synchronized; by comparing the start count value in the start instruction with the clock count value, when the clock count value is equal to the start count value for the first time, the operation of the microinstruction is triggered, and each resource board determines the triggering time of the microinstruction according to the same start count value, so as to ensure that each resource board starts to run the microinstruction at the same time, without spending communication time, thereby improving the control accuracy, synchronization accuracy and real-time operation of the instruction.

[0040] In some embodiments, Figure 3 is a flowchart of the microinstruction expansion of some embodiments of the present application, such as Figure 3 As shown, the process includes the following steps: Step S301, based on the operation code and function information, obtain the number of execution cycles corresponding to the test instruction.

[0041] Specifically, the test instruction includes a valid channel Ch_enable, a row difference Vector_num, an operation code Opcode, and function information Operand.

[0042] Among them, the effective channel Ch_enable is used to identify which resource boards the test instruction is valid for. Each resource board corresponds to a channel number, and each bit can identify a channel. The row difference Vector_num is used to indicate the row difference between this test instruction and the previous test instruction. The operation code Opcode is the instruction statement, including REPAET, LOOP, ENDLOOP, TRIG, and EVENT_AD statements. For test instructions other than EVENT_AD, the function information Operand is used to record the number of executions of the test instruction. For the EVENT_AD test instruction, the function information Operand is used to record the control object, event type, and event parameters of the test instruction according to preset rules.

[0043] In a specific embodiment, the control object of the EVENT_AD test instruction may be an arbitrary waveform generator AWG and a waveform collector DGT. Event types may include controlling the connection, disconnection, start, stop, and microinstruction loading of the AWG and DGT, and event parameters may be configuration parameters required in the process of controlling the AWG and DGT.

[0044] When the operation code of the test instruction is TRIG, the corresponding number of execution cycles is 1.

[0045] When the opcode of the test instruction is REPAET, LOOP, or ENDLOOP, the number of execution cycles corresponding to the test instruction is obtained according to the corresponding function information. Among them, the LOOP and ENDLOOP test instructions can support multi-level nesting, for example, three-level nesting. Since the LOOP and ENDLOOP instructions need to execute a section of the test instruction in a loop, RAM can be used to store the test instructions.

[0046] Step S302, based on the row difference and the number of execution cycles, obtain the execution cycle sequence number of each microinstruction corresponding to the test instruction.

[0047] According to the row difference and execution cycle number of each test instruction, the execution cycle sequence number of each microinstruction corresponding to the test instruction is assigned. The starting value of the execution cycle sequence number of the test instruction is equal to the sum of the end value of the execution cycle sequence number of the previous test instruction and the row difference.

[0048] Step S303, based on the valid channel, the execution cycle number, the operation code and the function information, one or more microinstructions corresponding to the test instruction are generated.

[0049] Specifically, the microinstruction format corresponding to the test instruction is as follows: Execution cycle number + operation code Opcode + function information Operand.

[0050] Furthermore, in the case of supporting the maximum operating rate, each test instruction can be expanded using one system clock. When the opcode of the test instruction is LOOP, while expanding a test instruction, the next test instruction is read out, and it is determined whether the next data is an ENDLOOP instruction and whether the loop quantity is reached at this time, so as to generate the corresponding microinstruction.

[0051] Through steps S301 to S303, the number of execution cycles corresponding to the test instruction, that is, the number of execution times of the test instruction, is obtained based on the operation code and function information; based on the line difference and the number of execution cycles, the execution cycle numbers of each microinstruction corresponding to the test instruction are obtained, and the execution order of each microinstruction is strictly corresponded to the execution time; based on the effective channel, the execution cycle number, the operation code and the function information, one or more microinstructions corresponding to the test instruction are generated, the test instruction executed in a loop is converted into microinstructions executed one by one, and the execution time of each microinstruction is obtained, thereby improving the control accuracy and synchronization accuracy of the test instruction.

[0052] In some embodiments, Figure 4is a flowchart of triggering microinstructions to run in some embodiments of the present application, such as Figure 4 As shown, the process includes the following steps: Step S401 : when the clock count value is equal to the start count value for the first time, counting starts based on the synchronous clock signal and the pre-configured execution cycle factor to obtain the execution cycle count value.

[0053] When the clock count value of the resource board equals the start count value for the first time, the execution cycle count is started to determine whether the execution time of each microinstruction is correct. Specifically, the execution time of the microinstruction = execution cycle factor × the period of the synchronous clock signal. The execution cycle factor is pre-configured by the host computer and sent to each resource board. Therefore, the resource board counts according to the synchronous clock signal and the execution cycle factor to obtain the execution cycle count value.

[0054] Step S402, sequentially obtain the execution cycle sequence number of each microinstruction and compare it with the execution cycle count value.

[0055] Each microinstruction includes a corresponding execution cycle number. Before the microinstructions are executed in sequence, the execution cycle number in the microinstruction is compared with the execution cycle count value.

[0056] Step S403, when the execution cycle sequence number is equal to the execution cycle count value, the microinstruction is executed until all microinstructions in the cache are executed.

[0057] According to the table content of step S303, due to the existence of row difference, the execution cycle sequence number of each microinstruction can be continuous or discontinuous.Before executing the microinstruction, first determine whether the execution cycle count value is equal to the execution cycle sequence number of this microinstruction, execute this microinstruction when equal, and read the next microinstruction simultaneously.If the execution cycle count value is less than the execution cycle sequence number, then wait for the execution cycle count value to equal the execution cycle sequence number and then execute.If the execution cycle count value is greater than the execution cycle sequence number, then the microinstruction is abnormally executed, and the process terminates.According to this process, all microinstructions in the cache are executed successively, and the execution completion signal is output, and the execution cycle count value can also be output simultaneously, to determine whether the microinstruction is normally executed.

[0058] Through steps S401 to S403, after the microinstruction is triggered to run, counting is started based on the synchronous clock signal and the pre-configured execution cycle factor to obtain an execution cycle count value, which is used as a time benchmark for determining whether the execution time of the microinstruction is correct; by sequentially obtaining the execution cycle number of each microinstruction and comparing it with the execution cycle count value, and when the execution cycle number is equal to the execution cycle count value, executing the microinstruction until all microinstructions in the cache are executed, each microinstruction is executed based on the correct execution time, thereby ensuring the time accuracy of the execution of each microinstruction.

[0059] In some embodiments, Figure 5 is a flowchart of the microinstruction execution of some embodiments of the present application, such as Figure 5 As shown, the process includes the following steps: Step S501, based on the event type and event parameters, obtain instruction information of the microinstruction.

[0060] For the EVENT_AD test instruction, its function information Operand can be divided into two parts: event type EVENT_TYPE and event parameter SIGNAL_NAME. The format of event type EVENT_TYPE can be control object_operation type. Among them, the control object can be arbitrary waveform generator AWG and waveform collector DGT, and the operation type can be connect, disconnect, start, stop, trigger, instruction load. Event parameters can be the configuration parameters required in the process of controlling AWG and DGT.

[0061] For the operation types of connection, disconnection, start, and stop, the instruction information of the microinstruction may be a control signal for the AWG and the DGT, and the control signal may be generated based on the event type and the event parameters; In some embodiments, when the event type of the microinstruction is instruction loading, the corresponding instruction information is read from the memory based on the loading address in the event parameter; when the event type of the microinstruction is not instruction loading, the corresponding instruction information is generated based on the event parameter.

[0062] Specifically, when the event type of the microinstruction is instruction loading, a loading operation is performed, corresponding control signals are loaded according to event parameters, and waveform files, FIR (finite impulse response) coefficients, etc. stored in DDR are read.

[0063] In the case where the event type of the microinstruction is not instruction loading, the event type of the microinstruction may include connection, disconnection, start, and stop. According to the event type and event parameters, a corresponding control signal may be generated, such as a start signal, a stop signal, a connection signal, etc. of an AWG or DGT.

[0064] Step S502, determining the sending object of the microinstruction based on the event parameters.

[0065] According to the event parameters of the microinstruction and with reference to the parameter information obtained in advance, the sending object of the instruction information is determined. The sending object includes AWG, DGT and controller FPGA. The controller FPGA is also connected to the AWG and DGT. The FPGA can further process the received instruction information and send it to the AWG and DGT. Therefore, it should be noted that the sending object is not completely equivalent to the control object in the microinstruction. In this embodiment, the control object is AWG and DGT, and the sending object also includes the controller FPGA.

[0066] Step S503: Send the instruction information to the sending object.

[0067] Specifically, when the sending object is a waveform generator or a waveform collector, the instruction information is converted into a clock domain and distributed to the waveform generator or the waveform collector. When the sending object is a controller, the instruction information is sent to the controller based on the communication protocol with the controller.

[0068] The clock domain conversion refers to converting the MASTER_CLK clock domain to the SYS_CLK system clock domain.

[0069] When the sending object is the controller FPGA, the command information is encoded in a custom protocol format and sent to the FE FPGA through the corresponding transmission channel.

[0070] Through steps S501 to S503, the instruction information of the microinstruction is obtained based on the event type and event parameters, and the corresponding control signal is generated or read; the sending object of the microinstruction is determined based on the event parameters, and the instruction information is sent to the sending object, thereby realizing flexible control of the test equipment and improving the level of automated control of the test equipment.

[0071] In some embodiments, Figure 6 Flowchart of microinstruction validity determination in some embodiments of the present application, such as Figure 6 As shown, the process includes the following steps: Step S601, determining whether the microinstruction is valid for the resource board based on the valid channel of the microinstruction.

[0072] When the execution cycle sequence number of step S403 is equal to the execution cycle count value, the microinstruction is executed. Before execution, it is determined whether the microinstruction is valid for the resource board based on the valid channel of the microinstruction. The valid channel of the test instruction is compared with the channel number of the resource board to determine whether the microinstruction is valid for the resource board.

[0073] Step S602, if valid, execute the microinstruction.

[0074] If it is a valid microinstruction, the microinstruction is sent to a parameter control module for executing the microinstruction.

[0075] Step S603: If invalid, ignore the microinstruction and read the next microinstruction.

[0076] If it is an invalid microinstruction, the next microinstruction in the cache FIFO is ignored and read, and the comparison between the execution cycle sequence number and the execution cycle count value is cyclically performed.

[0077] Through steps S601 to S603, it is determined whether the microinstruction is valid for the resource board through a valid channel based on the microinstruction. If it is valid, the microinstruction is executed. If it is invalid, the microinstruction is ignored and the next microinstruction is read. The corresponding microinstructions are executed for different resource boards, thereby improving the flexibility of microinstruction execution.

[0078] In some embodiments, Figure 7 is a flowchart of microinstruction delay compensation in some embodiments of the present application, such as Figure 7 As shown, the process includes the following steps: Step S701, determining whether the microinstruction is a delay compensation microinstruction, the delay compensation microinstruction including the number of delay cycles.

[0079] The microinstructions included in the EVENT_AD test instruction include, in addition to the microinstructions for connecting, disconnecting, starting, stopping, loading microinstructions, etc. for AWG and DGT in the above embodiments, a delay compensation microinstruction RESYNC is also included. The delay compensation microinstruction is used to provide a delay cycle number, which is used to compensate for the trigger delay of the signal after the start microinstruction is run.

[0080] In this embodiment, the trigger delay of the signal may include: 1) Trigger delay of logic processing. After the logic receives the run trigger instruction of the microinstruction, it needs to perform other business processing and cannot perform the trigger action immediately. There will be a delay here. The delay time is related to the system clock, which is recorded as N system clocks here; 2) Trigger delay of data processing. After the trigger instruction actually takes effect, there is a delay in the data output by the trigger reaching the IO of the DAC. The delay time is related to the sampling clock, which is recorded as M sampling clocks here; 3) After the data is input into the DAC chip, the DAC chip needs to convert it into an analog signal output. Here, the chip has an inherent delay that cannot be ignored. The delay time is related to the sampling clock, which is recorded here as T sampling clocks.

[0081] Therefore, without compensation, the actual trigger is delayed by N×system clock + (M+T)×sampling clock after receiving the trigger signal, and this delay is a fixed delay. In this embodiment, the sampling clock period is known, so the delay time is also fixed, and the delay time is converted into the number of delay cycles for compensation, where the number of delay cycles = (N×system clock + (M+T)×sampling clock) / MASTER_CLK. Rounding can be used here, and the accuracy loss is controlled within 1 MASTER_CLK.

[0082] In this embodiment, before running other microinstructions, the host computer sends the number of delay cycles that need to be compensated to the resource board through the delay compensation microinstruction RESYNC. When the resource board runs other microinstructions, it runs all microinstructions in advance based on the number of delay cycles.

[0083] Step S702: If yes, obtain the difference between the execution cycle number and the delay cycle number corresponding to each microinstruction after the delay compensation microinstruction.

[0084] If the microinstruction is a delay compensation microinstruction, the number of delay cycles is obtained, and the difference between the execution cycle number of each microinstruction after the delay compensation microinstruction and the number of delay cycles is calculated.

[0085] Step S703, comparing the difference with the execution cycle count value, and when the difference is equal to the execution cycle count value, executing the corresponding microinstruction.

[0086] In a specific embodiment, assuming that the execution cycle number of a microinstruction is 100, then without delay compensation, the microinstruction should be executed when the execution cycle count value is equal to 100. When the delay compensation microinstruction RESYNC is received, and the delay cycle number in RESYNC is 30, the microinstruction should be executed when the execution cycle count value is equal to 100-30=70. That is, each microinstruction after the delay compensation microinstruction is executed 30 delay cycles in advance.

[0087] Through steps S701 to S703, by determining whether a microinstruction is a delay compensation microinstruction, it is determined whether subsequent microinstructions need to be delayed compensated; by obtaining the difference between the execution cycle number and the number of delay cycles corresponding to each microinstruction after the delay compensation microinstruction, the time length of the delay compensation is determined; by comparing the difference with the execution cycle count value, when the difference is equal to the execution cycle count value, the corresponding microinstruction is executed to ensure the time accuracy of the early execution of the microinstruction and improve the triggering accuracy of the microinstruction operation.

[0088] In some embodiments, Figure 8 is a flowchart of test instruction preloading in some embodiments of the present application, such as Figure 8 As shown, the process includes the following steps: Step S801, based on the storage address and length of the received preload instruction and test instruction, multiple test instructions are read into the cache in sequence.

[0089] After receiving the preload instruction, the resource board reads the corresponding test instruction from the DDR into the cache of the resource board according to the storage address and length of the test instruction in the preload instruction. The cache may be a FIFO.

[0090] Step S802 : setting a preload flag based on the length of the test instruction, the number of test instructions read into the cache, and the maximum storage quantity of the cache.

[0091] During the loading process, whether the loading is complete is determined based on the number of test instructions read into the cache and the length of the test instructions to be loaded.

[0092] Specifically, a loading length threshold may be pre-set, and the loading length threshold may be equal to the maximum number of microinstructions that can be stored in the cache space. When the length of the test instruction to be loaded is less than the loading length threshold, it is determined whether the number of test instructions read into the cache is equal to the length of the test instruction to be loaded, and when the two are equal, it is determined that the loading is complete, and the preloading flag is set to a preset value, for example, the preloading flag is set to 1; when the length of the test instruction to be loaded is greater than or equal to the loading length threshold, it is determined whether the number of test instructions read into the cache is equal to the loading length threshold, and when the two are equal, it is determined that the loading is complete, and the preloading flag is set to a preset value.

[0093] Step S803, when the value of the preload flag is equal to the preset value, based on the order of the test instructions in the cache, each test instruction is sequentially expanded into one or more microinstructions.

[0094] The value of the preload flag equals the preset value, indicating that the test instruction has been loaded. At this time, each test instruction in the cache can be expanded into one or more microinstructions. When a test instruction is expanded, there is remaining storage space in the cache. At this time, the preload flag can be set to 0 again, and the loading of the test instruction continues until all the remaining test instructions are loaded into the cache.

[0095] Through steps S801 to S803, multiple test instructions are read into the cache in sequence based on the storage address and length of the received preload instructions and test instructions, so as to execute subsequent test instruction expansion; a preload flag is set based on the length of the test instruction, the number of test instructions read into the cache, and the maximum storage number of the cache, and loading is stopped when the number of loaded test instructions reaches the maximum value that can be stored in the cache to prevent data overflow; when the value of the preload flag is equal to the preset value, each test instruction is expanded into one or more microinstructions in sequence based on the sorting of the test instructions in the cache, thereby ensuring the orderly asynchronous execution of the loading and expansion of the test instructions.

[0096] Some embodiments of the present application also provide a microinstruction control test system, Fig. 9 is a structural block diagram of a microinstruction control test system of some embodiments of the present application, such as Fig. 9As shown, the microinstruction control test system includes a host computer 10, a communication board 20 connected to the host computer 10, and a plurality of resource boards 30 (one is shown in the figure) connected to the communication board. The resource board 30 includes a microinstruction controller 100, and the microinstruction controller includes: The service decoding module 101 is used to receive the synchronous clock signal and the start instruction sent by the communication board and forward them to the microinstruction control module 105, and the start instruction includes the start count value; The test instruction cache module 104 is used to sequentially expand each test instruction into one or more microinstructions based on the order of the pre-loaded multiple test instructions and send them to the microinstruction control module 105; The microinstruction control module 105 is used to start cyclic counting based on the synchronous clock signal to obtain a clock count value; and compare the start count value with the clock count value, and trigger the execution of the microinstruction when the clock count value is equal to the start count value for the first time.

[0097] The microinstruction control test system of the present embodiment orderly caches the test instructions through the test instruction cache module 104, and performs synchronous counting through the microinstruction control module 105, thereby providing a unified counting time for multiple resource boards to realize synchronous operation of microinstructions, and triggers the operation of the microinstructions when the clock count value is equal to the start count value for the first time. Each resource board determines the triggering timing of the microinstructions according to the same start count value, thereby ensuring that each resource board starts to run the microinstructions at the same time, without spending communication time, thereby improving the control accuracy, synchronization accuracy and real-time operation of the instructions.

[0098] In some embodiments, Fig.10 is a structural block diagram of a microinstruction control test system of other embodiments of the present application, such as Fig.10 As shown, the microinstruction controller 100 also includes a parameter control module 106, and the microinstruction control module 105 is also used for: When the clock count value is equal to the start count value for the first time, counting starts based on the synchronous clock signal and the pre-configured execution cycle factor to obtain the execution cycle count value; Obtain the execution cycle sequence number of each microinstruction in turn and compare it with the execution cycle count value; When the execution cycle sequence number is equal to the execution cycle count value, determining whether the microinstruction is valid for the resource board based on the valid channel of the microinstruction; If valid, the microinstruction is sent to the parameter control module 106; In the invalid case, the microinstruction is ignored and the next microinstruction is fetched.

[0099] The microinstruction control test system of this embodiment obtains the execution cycle count value through the microinstruction control module 105 as a time reference for determining whether the execution time of the microinstruction is correct, and executes the microinstruction when the execution cycle sequence number is equal to the execution cycle count value, thereby ensuring the time accuracy of the execution of each microinstruction; and executing corresponding microinstructions on different resource boards improves the flexibility of microinstruction execution.

[0100] In some embodiments, Fig.11 is a structural block diagram of a microinstruction control test system of some other embodiments of the present application, such as Fig.11 As shown, the microinstruction controller 100 also includes a loading control module 107 and a parameter selection module 108. The microinstruction includes an event type and event parameters. The parameter control module 106 is used for parsing the corresponding load instruction based on the microinstruction and sending it to the load control module 107 when the event type in the microinstruction is instruction load; In the case where the event type of the microinstruction is not instruction loading, based on the event type and event parameters, instruction information of the microinstruction is generated, and the instruction information is sent to the parameter selection module 108; The loading control module 107 is used to read corresponding instruction information based on the loading instruction and send it to the parameter selection module 108 .

[0101] The microinstruction control test system of this embodiment generates or reads control signals for controlling the test equipment through the parameter control module 106 and the loading control module 107 and sends them to the parameter selection module, thereby achieving flexible control of the test equipment and improving the level of automated control of the test equipment.

[0102] In some embodiments, Fig.12 is a structural block diagram of a microinstruction control test system of some other embodiments of the present application, such as Fig.12 As shown, the microinstruction controller also includes a cross-clock domain control module 109 and a controller transmission module 110. The parameter selection module 108 is used to send the instruction information to the cross-clock domain control module 109 or the controller transmission module 110 based on the event type of the instruction information; The cross-clock domain control module 109 is used to perform clock domain conversion on the instruction information and distribute it to the waveform generator or waveform collector; The controller transmission module 110 is used to send instruction information to the controller based on the communication protocol with the controller.

[0103] The microinstruction control test system of this embodiment sends instruction information to the functional module corresponding to the control object through the parameter selection module 108, realizes the clock domain conversion of the instruction information through the cross-clock domain control module 109, and realizes the package transmission of the instruction information through the controller transmission module 110, thereby ensuring the correct transmission of the instruction information to the test equipment and the controller.

[0104] In some embodiments, Fig.12 As shown, the microinstruction controller further includes an instruction request module 103, and the instruction request module 103 is used to: Based on the storage address and length of the received preload instruction and test instruction, multiple test instructions are read into the test instruction cache module 104 in sequence; based on the length of the test instruction, the number of test instructions read into the test instruction cache module 104 and the maximum storage quantity of the test instruction cache module, a preload flag is set.

[0105] The microinstruction control test system of this embodiment reads multiple test instructions in sequence to the test instruction cache module 104 through the instruction request module 103, and sets a preload flag. When the number of loaded test instructions reaches the maximum value that can be stored in the cache, loading is stopped to prevent data overflow, thereby ensuring the orderly asynchronous execution of loading and expansion of test instructions.

[0106] The microinstruction control test system of this embodiment is described and illustrated by a preferred embodiment. The microinstruction control test system includes a host computer, a communication board connected to the host computer, and a plurality of resource boards connected to the communication board, wherein the resource board includes a microinstruction controller. Fig.13 is a block diagram of the microinstruction controller of some preferred embodiments of the present application, such as Fig.13 As shown, the microinstruction controller includes: a service decoding module 101, a DDR control module 102, an instruction request module 103, a test instruction cache module 104, a microinstruction control module 105, a parameter control module 106, a loading control module 107, a parameter selection module 108, a cross-clock domain control module 109, a controller transmission module 110, an AWG control module 111, a DGT control module 112, and a GTX to FE sending control module 113.

[0107] Business decoding module 101: The main function is to decode the data sent by the host computer according to the communication protocol, convert the decoded data from the SYS_CLK system clock domain to the MASTER_CLK microinstruction clock domain, and send the decoded parameters to the corresponding modules, including the DDR control module 102, the instruction request module 103, the test instruction cache module 104, and the microinstruction control module 105. The main parameters include DDR read and write instructions, start instructions, test instruction execution cycle factor, test instruction storage address in DDR, length and other information, test instruction preload instructions, test instruction status clearing instructions and other parameters.

[0108] DDR control module 102: executes the read and write functions of DDR, and supports multiple DDR channels to initiate read and write requests simultaneously.

[0109] Instruction request module 103: Initiates a request to DDR according to the preloading instruction of the test instruction and the address, length and other information of the test instruction stored in DDR, reads the test instruction stored in DDR, and sends it to the test instruction cache module 104; at the same time, according to the length of the test instruction stored in DDR and the number sent to the test instruction cache module 104, determines whether the preloading status bit SET_UP is completed; the judgment condition is that when the length is less than 2000, the number of data sent is equal to the length, the SET_UP state is completed, otherwise it is not completed; when the length is greater than or equal to 2000, the number of data sent is equal to 2000, the SET_UP state is completed, otherwise it is not completed.

[0110] Test instruction cache module 104: After the SET_UP state is completed, the test instruction in the 128-bit format is decoded, and the test instruction is expanded according to the operation code OPCODE of the test instruction, and restored to the microinstruction corresponding to each execution cycle. Each microinstruction has its own execution cycle number, and is sent to the microinstruction control module 105 in the format of valid channel_execution cycle number_operation code_function information; the main purpose is to expand instructions such as REPEAT\LOOP\ENDLOOP\TRIG, and convert the original test instructions into instructions each with independent execution time information, which are stored in the microinstruction control module 105, waiting for the triggering of the microinstruction to take effect, and then perform the actual microinstruction operation.

[0111] Microinstruction control module 105: Generates an effective RUN_TRIG instruction according to the start instruction and the start count value TRIG_GST_CNT, as well as the counter for clock cycle counting starting at power-on; starts running the microinstruction according to the RUN_TRIG instruction, and starts CYCLE counting after the RUN_TRIG instruction takes effect, and MASTER_CLK counts CYCLE according to the execution cycle factor (CYCLE_CNT increases by 1 for every execution cycle factor MASTER_CLK clocks), and when the actual CYCLE_CNT count reaches the microinstruction, the microinstruction starts running. When the execution cycle number in the microinstruction is determined, it is determined whether the valid channels in this microinstruction include this board. If it is a valid microinstruction, it is sent to the parameter control module 106, otherwise the microinstruction is ignored, and the next microinstruction in the cache FIFO is read at the same time, and it is continued to be determined whether CYCLE_CNT is equal to the execution cycle number; when the data in the cache FIFO of the microinstruction control module 105 are processed, the RUN_VECTOR_DONE signal is output, indicating that the test instruction has been completed, and the CYCLE_COUNT count is output at the same time to determine whether the test instruction is running normally.

[0112] Parameter control module 106: decodes the microinstructions to obtain corresponding control signals, including AWG_TRIG, AWG_STOP, AWG_LOADSEETING, AWG_CONNECT, AWG_DISCONNECT, DGT_TRIG, DGT_STOP, DGT_LOADSEETING, DGT_CONNECT, DGT_DISCONNECT, etc. The control signals are sent to the loading control module 107 or the parameter selection module 108, of which AWG_LOADSEETING and DGT_LOADSEETING are sent to the loading control module 107, and the other 8 signals are sent to the parameter selection module 108.

[0113] The loading control module 107 requests DDR data according to the AWG_LOADSEETING and DGT_LOADSEETING instructions and the SIGNAL addresses, reads out the SIGNAL information stored in the DDR, and sends the read data to the parameter selection module 108 for data selection.

[0114] Parameter selection module 108: Determine which parameters need to be transmitted to the AWG module, DGT module, and FE FPGA peripheral chip based on the preset parameter information. After determination, send the data of the AWG module and the DGT module to the cross-clock domain control module 109 for cross-clock preprocessing; send the data of the FE FPGA peripheral chip to the controller transmission module 110.

[0115] The cross-clock domain control module 109 performs clock domain conversion through FIFO, converts the data of the AWG module and the DGT module from the MASTER_CLK clock domain to the SYS_CLK system clock domain, and then distributes them to the AWG control module 111 and the DGT control module 112 .

[0116] Controller transmission module 110: transmits the data to be transmitted to FE FPGA to FE FPGA according to the self-defined protocol format, encodes the data according to the transmission type to form 64-bit bit width data, and transmits it to FE FPGA through the GTX bus of GTX to FE sending control module 113.

[0117] The microinstruction control test system of this embodiment receives the synchronous clock signal and the start instruction through the service decoding module 101 and forwards them to the microinstruction control module 105; reads multiple test instructions from the DDR to the test instruction cache module 104 in sequence through the instruction request module 103, and sets a preload flag, stops loading when the number of test instructions loaded reaches the maximum value that can be stored in the cache, prevents data overflow, and ensures the orderly asynchronous execution of the loading and expansion of the test instructions; caches the test instructions through the test instruction cache module 104, and performs synchronous counting through the microinstruction control module 105, which provides a unified counting time for multiple resource boards to realize synchronous operation of microinstructions, and when the clock count value is first When it is equal to the start count value, the running of the microinstruction is triggered to ensure that each resource board starts running the microinstruction at the same time, thereby improving the synchronization accuracy of the instruction; when the execution cycle sequence number is equal to the execution cycle count value, the microinstruction is executed to ensure the time accuracy of the execution of each microinstruction; the control signal for controlling the test equipment is generated or read through the parameter control module 106 and the loading control module 107, the instruction information is sent to the functional module corresponding to the control object through the parameter selection module 108, the clock domain conversion of the instruction information is realized through the cross-clock domain control module 109, and the packet transmission of the instruction information is realized through the controller transmission module 110, thereby ensuring the correct transmission of the instruction information to the test equipment and the controller.

[0118] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0119] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0120] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0121] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0122] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A method for synchronously triggering microinstructions between boards, characterized in that: The method is applied to a resource board in a microinstruction control test system, wherein the system comprises a host computer, a communication board connected to the host computer for communication, and a plurality of resource boards connected to the communication board, and the method comprises: Receiving a synchronous clock signal sent by the communication board, and starting cyclic counting based on the synchronous clock signal to obtain a clock count value; Based on the order of the plurality of test instructions preloaded into the cache, sequentially expanding each test instruction into one or more microinstructions; Receiving a startup instruction sent by the communication board, wherein the startup instruction includes a startup count value; The startup count value is compared with the clock count value, and when the clock count value is equal to the startup count value for the first time, the execution of the microinstruction is triggered.

2. The method according to claim 1, characterized in that The microinstruction includes an execution cycle number, and when the clock count value is equal to the start count value for the first time, triggering the execution of the microinstruction includes: When the clock count value is equal to the start count value for the first time, counting starts based on the synchronous clock signal and a preconfigured execution cycle factor to obtain an execution cycle count value; Obtaining the execution cycle sequence number of each of the microinstructions in sequence and comparing it with the execution cycle count value; When the execution cycle sequence number is equal to the execution cycle count value, the microinstruction is executed until all microinstructions in the cache are executed.

3. The method according to claim 2, characterized in that The microinstruction also includes an event type and event parameters, and executing the microinstruction includes: Based on the event type and the event parameters, obtaining instruction information of the microinstruction; Based on the event parameters, determining a sending object of the microinstruction; The instruction information is sent to the sending object.

4. The method according to claim 3, characterized in that The sending of the instruction information to the sending object comprises: In the case where the sending object is a waveform generator or a waveform collector, performing clock domain conversion on the instruction information and distributing it to the waveform generator or the waveform collector; When the sending object is a controller, the instruction information is sent to the controller based on a communication protocol with the controller.

5. The method according to claim 3, characterized in that: The acquiring the instruction information of the microinstruction based on the event type and the event parameter comprises: In the case where the event type of the microinstruction is instruction loading, reading corresponding instruction information from a memory based on a loading address in the event parameter; When the event type of the microinstruction is not instruction loading, corresponding instruction information is generated based on the event parameters.

6. The method according to claim 2, characterized in that The microinstruction also includes a valid channel, and when the execution cycle sequence number is equal to the execution cycle count value, executing the microinstruction includes: Determining whether the microinstruction is valid for the resource board based on the valid channel of the microinstruction; If valid, executing the microinstruction; In the invalid case, the microinstruction is ignored and the next microinstruction is fetched.

7. The method according to claim 1, characterized in that The test instruction includes a valid channel, a row difference, an operation code and function information, and the sequence of the multiple test instructions preloaded into the cache is based on the order in which each test instruction is sequentially expanded into one or more microinstructions, including: Based on the operation code and the function information, obtaining the number of execution cycles corresponding to the test instruction; Based on the row difference and the number of execution cycles, obtaining the execution cycle sequence number of each microinstruction corresponding to the test instruction; Based on the valid channel, execution cycle number, operation code and function information, one or more microinstructions corresponding to the test instruction are generated.

8. The method according to claim 2, characterized in that: When the execution cycle sequence number is equal to the execution cycle count value, executing the microinstruction includes: Determining whether the microinstruction is a delay compensation microinstruction, wherein the delay compensation microinstruction includes a delay cycle number; If so, obtaining the difference between the execution cycle number corresponding to each microinstruction after the delay compensation microinstruction and the delay cycle number; The difference is compared with the execution cycle count value, and when the difference is equal to the execution cycle count value, the corresponding microinstruction is executed.

9. The method according to claim 1, characterized in that: Before sequentially expanding each test instruction into one or more microinstructions based on the order of the plurality of test instructions preloaded into the cache, the method further includes: Based on the received storage addresses and lengths of the preload instructions and the test instructions, the plurality of test instructions are sequentially read into the cache; Setting a preload flag based on the length of the test instruction, the number of test instructions read into the cache, and the maximum storage quantity of the cache; When the value of the preload flag is equal to a preset value, each test instruction is sequentially expanded into one or more microinstructions based on the order of the test instructions in the cache.

10. A microinstruction control test system, characterized in that: The system includes a host computer, a communication board connected to the host computer, and a plurality of resource boards connected to the communication board, wherein the resource board includes a microinstruction controller, and the microinstruction controller includes: A service decoding module, used for receiving the synchronous clock signal and the start instruction sent by the communication board and forwarding them to the microinstruction control module, wherein the start instruction includes a start count value; A test instruction cache module, for sequentially expanding each test instruction into one or more microinstructions and sending the microinstructions to the microinstruction control module based on the order of the preloaded multiple test instructions; The microinstruction control module is used to start cyclic counting based on the synchronous clock signal to obtain a clock count value; and compare the start count value with the clock count value, and when the clock count value is equal to the start count value for the first time, trigger the execution of the microinstruction.

11. The system according to claim 10, characterized in that The microinstruction controller also includes a parameter control module, and the microinstruction control module is also used for: When the clock count value is equal to the start count value for the first time, counting starts based on the synchronous clock signal and a preconfigured execution cycle factor to obtain an execution cycle count value; Obtaining the execution cycle sequence number of each of the microinstructions in sequence and comparing it with the execution cycle count value; When the execution cycle sequence number is equal to the execution cycle count value, determining whether the microinstruction is valid for the resource board based on the valid channel of the microinstruction; If valid, sending the microinstruction to the parameter control module; In the invalid case, the microinstruction is ignored and the next microinstruction is fetched.

12. The system according to claim 11, characterized in that The microinstruction controller also includes a loading control module and a parameter selection module. The microinstruction includes an event type and an event parameter. The parameter control module is used for parsing the corresponding load instruction based on the microinstruction and sending it to the load control module when the event type in the microinstruction is instruction loading; In the case where the event type of the microinstruction is not instruction loading, generating instruction information of the microinstruction based on the event type and the event parameter, and sending the instruction information to the parameter selection module; The loading control module is used to read corresponding instruction information based on the loading instruction and send it to the parameter selection module.

13. The system according to claim 12, characterized in that The microinstruction controller also includes a cross-clock domain control module and a controller transmission module. The parameter selection module is used to send the instruction information to the cross-clock domain control module or the controller transmission module based on the event type of the instruction information; The cross-clock domain control module is used to perform clock domain conversion on the instruction information and distribute it to the waveform generator or waveform collector; The controller transmission module is used to send the instruction information to the controller based on the communication protocol with the controller.

14. The system according to claim 10, characterized in that The microinstruction controller further comprises an instruction request module, wherein the instruction request module is used for: Based on the storage address and length of the received preload instructions and test instructions, multiple test instructions are read into the test instruction cache module in sequence; based on the length of the test instructions, the number of test instructions read into the test instruction cache module and the maximum storage quantity of the test instruction cache module, a preload flag is set.

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