A PCIe dual-port SSD low power consumption control device and method

Abstract

The present invention relates to the field of storage, and specifically to a PCIe dual-port SSD low-power control device and method. The device includes a load prediction unit and a power consumption control unit. The load prediction unit uses the PCIe power management module (ASPM)'s judgment result on the link idle state and the margin value of the receive / transmit buffer as input to calculate the current load state of each of the two ports and output a load level value. The power consumption control unit uses the load level output by the load prediction unit to timely adjust the operating state of each SSD module to achieve SSD power consumption control. The present invention detects the business pressure and load conditions of the two ports and adaptively adjusts the operating state of each SSD module to achieve dynamic adjustment of SSD power consumption. While ensuring timely and accurate data response, it minimizes the power consumption of the entire disk and improves the energy saving effect of the data center.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a PCIe dual-port SSD low power consumption control device and method. Background Art

[0002] PCIe dual-port SSDs are commonly used in data center services in active-active storage systems, providing data storage, read-write access, and other functions. Active-active storage systems are a widely used redundant storage method that uses a master-slave mechanism to enable two data sites to simultaneously handle user services. When a storage controller fails, it can quickly switch to the other controller to provide data access response for upper-layer services, ensuring highly reliable system operation. With the rapid development of data centers today, active-active systems no longer simply provide traditional disaster recovery capabilities but instead emphasize improved resource utilization, enabling the coordinated operation of two storage arrays, load balancing, and maximizing hardware resource utilization. When a PCIe dual-port SSD is in dual-port mode, both links are active, resulting in high overall power consumption. Reducing SSD power consumption is an issue that needs improvement.

[0003] To ensure the independence, security, and reliability of the active-active system, the PCIe dual-port SSD system is designed to take into account the physical isolation of the data read and write path resources of the two PCIe ports, such as the DMA data transmission engine. Therefore, the working status of related hardware resources can be automatically adjusted according to the read and write business conditions of the two ports of the active-active system, achieving adaptive adjustment of power consumption and achieving the goal of optimizing the power consumption of the entire disk. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a PCIe dual-port SSD low-power control device and method, which can accurately and efficiently implement port power consumption control in real time according to the load conditions of the dual-active storage system accessing the two ports, thereby reducing the power consumption of the entire disk.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: a PCIe dual-port SSD low-power control device, including a load prediction unit, a power consumption control unit and a clock switching unit:

[0006] The input of the load prediction unit is the judgment result of the PCIe power management module ASPM on the link idle state of port A and / or port B and the margin value of the receive / send buffer. The load state of port A and / or port B is calculated based on the input, and the load level value is output. Port A and port B represent the two PCIe ports of the PCIe dual-port SSD. The load state calculation method is: when the link does not enter the L0s state within the sampling time interval T and the receive and send buffers are more than half full within the sampling time interval T, the load prediction unit determines that the link is in a heavy load state and outputs load level A; when the number of times the link enters the L0s state within the sampling time interval T reaches the threshold Y0 and the receive and send buffers are less than half full within the sampling time interval T, the load prediction unit determines that the link is in a light load state and outputs load level B; when the number of times the link enters the L1 state within the sampling time interval T reaches the threshold Y1, the load prediction unit determines that the link is in a process of no data transmission and outputs load level C;

[0007] The input end of the power consumption control unit is connected to the output end of the load prediction unit. The working state of each SSD module is adjusted according to the load level output by the load prediction unit to realize the power consumption control of the SSD. The working state of each SSD module is adjusted as follows: when the load prediction unit outputs level A, each SSD module is controlled to be in a full-load operation state and operate according to the maximum supportable frequency. When the load prediction unit outputs level B, each SSD module is controlled to be in a partially reduced-frequency operation state. When the load prediction unit outputs level C, the power consumption core module is controlled to enter a low-power standby state.

[0008] Furthermore, when the PCIe link power management module ASPM controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to level A, so that each module synchronously enters the full-load working state. When the PCIe link power management module ASPM controls the PCIe LTSSM from the L0 state to the L0s state, the load prediction unit updates the level to level B, so that each hardware unit begins to enter the low-power control state. When the PCIe link power management module ASPM controls the PCIe LTSSM from the L0s state to the L1 state, the load prediction unit updates the level to level C, so that each hardware unit enters the deep low-power control state.

[0009] Furthermore, the three load levels output by the load prediction unit have internal flow characteristics, and the load levels are managed by a logic operation state machine.

[0010] Furthermore, it also includes a clock switching unit, the input end of the clock switching unit is connected to the output end of the power consumption control unit, which is used to receive the frequency control signal for each SSD module output by the power consumption control unit and switch the clock frequency of each SSD module according to the frequency control signal.

[0011] Furthermore, the frequency control signal output by the power consumption control unit for each SSD module consists of 2 bits. When the load prediction unit outputs Level A, the frequency control signal is the maximum value 11. When the load prediction unit outputs Level B, the frequency control signal outputs the intermediate value 10. When the load prediction module outputs Level C, the frequency control signal is the second minimum value 01. When the clock needs to be turned off, the frequency control signal is the minimum value 00 (this state cannot be controlled by the load prediction unit and is a reserved control value).

[0012] Correspondingly, each SSD module has two control signals, which are combined into four division coefficients. The four division coefficients generate four clock frequency gears. Gear 3 represents the state of no frequency reduction, which meets the working scenario requirements of level A load. Gear 2 represents the state of partial frequency reduction, which meets the working scenario requirements of level B load. Gear 1 represents the state of deep frequency reduction, which meets the working scenario requirements of level C load. Gear 0 represents the clock stop state.

[0013] Furthermore, when the load prediction unit outputs level B or level C, the power consumption core modules that enter a low power consumption state and standby include the NVMe controller, DDR controller, AXI bus, and CPU.

[0014] The present invention also discloses a PCIe dual-port SSD low power consumption control method, comprising the following steps:

[0015] S01, enable the PCIe dual-port SSD in dual-port working mode;

[0016] S02, initialize the sampling time interval T of the load prediction unit, and initialize the number of times the link working state enters L0s and L1 thresholds Y0 and Y1;

[0017] S03, PCIe dual-port SSD performs business command processing;

[0018] S04. The load prediction unit determines the status of the workload of the two ports in real time and provides a load level indication signal to the power consumption control unit. The load levels include level A, level B, and level C. The calculation method is as follows: when the link does not enter the L0s state within the sampling time interval T and the receiving and sending buffers are more than half full within the sampling time interval T, the load prediction unit determines that the link is in a heavy load state and outputs load level level A; when the number of times the link enters the L0s state within the sampling time interval T reaches a threshold value Y0 and the receiving and sending buffers are less than half full within the sampling time interval T, the load prediction unit determines that the link is in a light load state and outputs load level level B; when the number of times the link enters the L1 state within the sampling time interval T reaches a threshold value Y1, the load prediction unit determines that the link is in a process of no data transmission and outputs load level level C;

[0019] S05. The power consumption control unit uses the load level output by the load prediction unit as input to adjust the working state of each SSD module to achieve power consumption control of the SSD. The working state of each SSD module is adjusted as follows: when the load prediction unit outputs level A, each SSD module is controlled to be in a full-load operation state and operate at the maximum supportable frequency; when the load prediction unit outputs level B, each SSD module is controlled to be in a partially reduced-frequency operation state; when the load prediction unit outputs level C, the power consumption core module is controlled to enter a low-power state and standby.

[0020] Furthermore, step S04 also includes: when the PCIe link power management module ASPM controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to level A, so that each module synchronously enters the full-load working state; when the PCIe link power management module ASPM controls the PCIe LTSSM from the L0 state to the L0s state, the load prediction unit updates the level to level B, so that each hardware unit starts to enter the low power consumption control state; when the PCIe link power management module ASPM controls the PCIe LTSSM from the L0s state to the L1 state, the load prediction unit updates the level to level C, so that each hardware unit enters the deep low power consumption control state.

[0021] Furthermore, in step S05, the power consumption control unit uses the load level output by the load prediction unit as input, calculates and outputs frequency control signals for each SSD module, and sets a clock switching unit. The clock switching unit receives the frequency control signal output by the power consumption control unit and controls the clock frequency of each SSD module.

[0022] The power consumption control unit outputs a 2-bit frequency control signal for each SSD module. When the load prediction unit outputs Level A, the frequency control signal is the maximum value 11. When the load prediction unit outputs Level B, the frequency control signal outputs the intermediate value 10. When the load prediction module outputs Level C, the frequency control signal is the next minimum value 01. When the clock needs to be shut down, the frequency control signal is the minimum value 00 (this state cannot be controlled by the prediction unit and is a reserved control value).

[0023] Correspondingly, each SSD module has two control signals, which are combined into four division coefficients. The four division coefficients generate four clock frequency gears. Gear 3 represents the state of no frequency reduction, which meets the working scenario requirements of level A load. Gear 2 represents the state of partial frequency reduction, which meets the working scenario requirements of level B load. Gear 1 represents the state of deep frequency reduction, which meets the working scenario requirements of level C load. Gear 0 represents the clock stop state.

[0024] Beneficial effects of the present invention: The present invention detects the business pressure and load conditions of the two ports, adaptively coordinates and schedules the working status of the hardware modules involved in the two physical paths, such as DMA and NVMe controllers, to achieve dynamic adjustment of SSD power consumption. While ensuring timely and accurate data response, the power consumption of the entire disk is reduced to the greatest extent possible, thereby improving the energy saving effect of the data center. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of an SSD equipped with the low-power control device described in Example 1;

[0026] Figure 2 This is a flow chart of the method described in Example 2. DETAILED DESCRIPTION

[0027] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0028] Example 1

[0029] This embodiment discloses a PCIe dual-port SSD low power consumption control device, such as Figure 1As shown, the basic hardware components of an SSD include a PCIe dual-port module, an NVMe controller, a DDR controller, a CPU, and a bus. The PCIe dual-port module serves as the interface for communication between the SSD and the host. The NVMe controller functions as the functional unit for NVMe protocol parsing, queue management, and command processing. The DDR controller serves as the control module for the DDR data cache medium. The CPU core serves as the central processing unit for software execution. The bus connects the various hardware components. This device monitors the traffic pressure and load of the two ports and adaptively coordinates the operating status of the hardware modules involved in the two physical paths, such as the DMA and NVMe controller. This allows for dynamic adjustment of SSD power consumption, minimizing overall drive power consumption while ensuring timely and accurate data response, thereby reducing energy consumption in the data center.

[0030] Specifically, the device includes a load prediction unit and an adaptive power consumption coordination and clock switching unit. The load prediction unit is used to determine the workload status of the PCIe port. The input is the PCIe power management module (ASPM)'s judgment result on the link idle status of port A and / or port B and the margin value of the receive / transmit buffer. Based on the input, the load status of port A and / or port B is calculated and a load level value is output. Port A and port B represent the two PCIe ports of a PCIe dual-port SSD.

[0031] In this embodiment, the load state is calculated as follows: when the link does not enter the L0s state within a sampling time interval T and the receive and transmit buffers are more than half full within the sampling time interval T, the load prediction unit determines that the link is in a heavily loaded state and outputs load level A; when the number of times the link enters the L0s state within the sampling time interval T reaches a threshold value Y0 and the receive and transmit buffers are less than half full within the sampling time interval T, the load prediction unit determines that the link is in a lightly loaded state and outputs load level B; when the number of times the link enters the L1 state within the sampling time interval T reaches a threshold value Y1, the load prediction unit determines that the link is in a process of no data transmission and outputs load level C. In this embodiment, the three load levels output by the load prediction unit have an internal flow characteristic, that is, the levels can flow between each other. The load levels are managed by a logic operation state machine, and the switching between the levels is controlled by a state machine to ensure effective management of the load levels.

[0032] The power consumption control unit's input is connected to the output of the load prediction unit. The load level output by the load prediction unit adjusts the operating state of each SSD module to achieve SSD power consumption control. The operating state of each SSD module is adjusted as follows: when the load prediction unit outputs level A, each SSD module is controlled to operate at full load and at the maximum supported frequency. When the load prediction unit outputs level B, each SSD module is controlled to operate at a partially reduced frequency. When the load prediction unit outputs level C, the power consumption core module is controlled to enter a low-power standby state. When the PCIe link power management module (ASPM) controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to level A, causing each module to simultaneously enter full load operation. When the PCIe link power management module (ASPM) controls the PCIe LTSSM from L0 to L0s, the load prediction unit updates the level to level B, causing each hardware unit to enter a low-power control state. When the PCIe link power management module ASPM controls the PCIe LTSSM from the L0s state to the L1 state, the load prediction unit updates the level to level C, causing each hardware unit to enter a deep low power control state.

[0033] In this embodiment, the frequency switching of each SSD module is achieved through a clock switching unit. The input end of the clock switching unit is connected to the output end of the power consumption control unit, and is used to receive the frequency control signal for each SSD module output by the power consumption control unit, and switch the clock frequency of each SSD module according to the frequency control signal.

[0034] Specifically, the frequency control signal output by the power consumption control unit for each SSD module consists of 2 bits. When the load prediction unit outputs Level A, the frequency control signal is the maximum value 11. When the load prediction unit outputs Level B, the frequency control signal outputs the intermediate value 10. When the load prediction module outputs Level C, the frequency control signal is the second minimum value 01. When the clock needs to be turned off, the frequency control signal is the minimum value 00 (this state cannot be controlled by the prediction unit and is a reserved control value).

[0035] Accordingly, each SSD module receives two control signals, which combine to form four frequency division coefficients. These four division coefficients generate four clock frequency levels, enabling adaptive frequency switching. Level 3 represents no frequency reduction, meeting the requirements of Level A load scenarios; Level 2 represents partial frequency reduction, meeting the requirements of Level B load scenarios; Level 1 represents deep frequency reduction, meeting the requirements of Level C load scenarios; and Level 0 represents a clock-free state. By selecting the frequency control signal level, safe frequency switching is achieved for each module.

[0036] In this embodiment, when the load prediction unit outputs level B or level C, the power consumption core modules that enter the low power consumption state and standby include the NVMe controller, the DDR controller, the AXI bus and the CPU.

[0037] When changing the frequency of each SSD module, since the PCIe NVMe controller is unique to each port, the PCIe NVMe controller frequency can be adjusted directly based on the load level. The AXI bus, DDR controller, and CPU core are shared by both ports, so the power consumption levels of both ports must be comprehensively assessed before confirming their operating status. For example, if port A's power consumption level is level B and port B's power consumption level is level C, the AXI bus, DDR controller, and CPU core will be partially downgraded to the corresponding level B state based on the power consumption levels of ports A and B to ensure normal operation of port A.

[0038] Example 2

[0039] In this embodiment, the frequency control signal output by the power consumption control unit is implemented by the CPU or software, and a clock switching unit is not required. It should be noted that the CPU or software switches the frequency of the SSD module when it is idle.

[0040] Example 3

[0041] This embodiment discloses a PCIe dual-port SSD low power consumption control method, such as Figure 2 As shown, the following steps are included:

[0042] S01, the SOC chip detects the validity of the DualPortEn# signal of the PCIe gold finger and enables the PCIe dual-port SSD in dual-port working mode;

[0043] S02, initialize the sampling time interval T of the load prediction unit, and initialize the number of times the link working state enters L0s and L1 thresholds Y0 and Y1;

[0044] S03, PCIe dual-port SSD performs business command processing;

[0045] S04. The load prediction unit determines the status of the workload of the two ports in real time and provides a load level indication signal to the power consumption control unit. The load levels include level A, level B, and level C. The calculation method is as follows: when the link does not enter the L0s state within the sampling time interval T and the receiving and sending buffers are more than half full within the sampling time interval T, the load prediction unit determines that the link is in a heavy load state and outputs load level level A; when the number of times the link enters the L0s state within the sampling time interval T reaches a threshold value Y0 and the receiving and sending buffers are less than half full within the sampling time interval T, the load prediction unit determines that the link is in a light load state and outputs load level level B; when the number of times the link enters the L1 state within the sampling time interval T reaches a threshold value Y1, the load prediction unit determines that the link is in a process of no data transmission and outputs load level level C;

[0046] S05. The power consumption control unit uses the load level output by the load prediction unit as input to adjust the working state of each SSD module to achieve power consumption control of the SSD. The working state of each SSD module is adjusted as follows: when the load prediction unit outputs level A, each SSD module is controlled to be in a full-load operation state and operate at the maximum supportable frequency; when the load prediction unit outputs level B, each SSD module is controlled to be in a partially reduced-frequency operation state; when the load prediction unit outputs level C, the power consumption core module is controlled to enter a low-power state and standby.

[0047] In this embodiment, step S04 further includes: when the PCIe link power management module ASPM controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to level A, so that each module synchronously enters the full-load working state; when the PCIe link power management module ASPM controls the PCIe LTSSM to enter the L0s state from the L0 state, the load prediction unit updates the level to level B, so that each hardware unit begins to enter a low-power control state; and when the PCIe link power management module ASPM controls the PCIe LTSSM to enter the L1 state from the L0s state, the load prediction unit updates the level to level C, so that each hardware unit enters a deep low-power control state.

[0048] In step S05, the power consumption control unit takes the load level output by the load prediction unit as input, obtains and outputs the frequency control signal of each SSD module through calculation, sets a clock switching unit, and the clock switching unit receives the frequency control signal output by the power consumption control unit to control the clock frequency of each SSD module.

[0049] The frequency control signal output by the power consumption control unit for each SSD module consists of 2 bits. When the load prediction unit outputs Level A, the frequency control signal is the maximum value 11. When the load prediction module outputs Level C, the frequency control signal is the sub-minimum value 01. The NVMe controller, DDR controller, corresponding AXI bus and CPU and other power-consuming core modules enter a low-power standby state. When the load prediction unit outputs Level B, the frequency control signal outputs the middle value 10, ensuring that each functional module basically works normally and the operating frequency is moderate.

[0050] Accordingly, each SSD module has two control signals, which are combined into four frequency division coefficients. These four division coefficients generate four clock frequency levels: Level 3 represents no frequency reduction, meeting the requirements of Level A load scenarios; Level 2 represents partial frequency reduction, meeting the requirements of Level B load scenarios; and Level 1 represents deep frequency reduction, meeting the requirements of Level C load scenarios. By selecting the frequency control signal level, safe switching of the frequency of each module is achieved.

[0051] In the above description, PCIe LTSSM represents the PCIe link training state machine. L0s, L0, and L1 are the operating states of the PCIe link. L0 is the normal operating state of the PCIe link. In this state, the PCIe link can normally send and receive TLPs, DLLPs, and Ordered Sets. L0s is the first low-power state, which can be quickly transitioned to L0. L1 is the second low-power state, which consumes less power than L0s but takes longer to transition to L0. When the PCIe link needs to be retrained, it enters the Recovery state. In the Recovery state, the bit lock and symbol / block lock are reestablished.

[0052] The present invention accurately and efficiently controls the power consumption of the ports in real time based on the load conditions of the active-active storage system accessing the two ports, thereby reducing the power consumption of the entire disk, contributing to the green, low-carbon and energy-saving development of the cloud computing center, and reducing the operating costs of the enterprise.

[0053] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention fall within the protection scope of the present invention.

Claims

1. A PCIe dual-port SSD low power consumption control device, characterized by: Including load prediction unit, power consumption control unit and clock switching unit: The load prediction unit takes as input the link idle status of port A and / or port B determined by the PCIe power management module (ASPM) and the receive / transmit buffer margin. Based on this input, it calculates the load status of port A and / or port B and outputs a load level. Port A and port B represent the two PCIe ports of a PCIe dual-port SSD. The load status is calculated as follows: when the link does not enter the L0s state within the sampling interval T and the receive and transmit buffers are more than half full within the sampling interval T, the load prediction unit determines that the link is in a heavy load state and outputs load level A; When the number of times the link enters the L0s state within the sampling interval T reaches a threshold value Y0 and the receive and transmit buffers are below half full within the sampling interval T, the load prediction unit determines that the link is in a lightly loaded state and outputs a load level of level B. When the number of times the link enters the L1 state within the sampling interval T reaches a threshold value Y1, the load prediction unit determines that the link is in a non-data transmission process and outputs a load level of level C. The input end of the power consumption control unit is connected to the output end of the load prediction unit. The working state of each SSD module is adjusted according to the load level output by the load prediction unit to realize the power consumption control of the SSD. The working state of each SSD module is adjusted as follows: when the load prediction unit outputs level A, each SSD module is controlled to be in a full-load operation state and operate according to the maximum supportable frequency. When the load prediction unit outputs level B, each SSD module is controlled to be in a partially reduced-frequency operation state. When the load prediction unit outputs level C, the power consumption core module is controlled to enter a low-power standby state.

2. The PCIe dual-port SSD low power consumption control device according to claim 1, characterized in that: When the PCIe link power management module ASPM controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to levelA. When the PCIe link power management module ASPM controls the PCIe LTSSM to enter the L0s state from the L0 state, the load prediction unit updates the level to levelB, so that each hardware unit starts to enter the low power control state. When the PCIe link power management module ASPM controls the PCIe LTSSM to enter the L1 state from the L0s state, the load prediction unit updates the level to levelC, so that each hardware unit enters the deep low power control state.

3. The PCIe dual-port SSD low power consumption control device according to claim 1, wherein: The three load levels output by the load prediction unit have internal flow characteristics, and the load levels are managed by a logic operation state machine.

4. The PCIe dual-port SSD low power consumption control device according to claim 1, wherein: It also includes a clock switching unit, the input end of the clock switching unit is connected to the output end of the power consumption control unit, which is used to receive the frequency control signal for each SSD module output by the power consumption control unit and switch the clock frequency of each SSD module according to the frequency control signal.

5. The PCIe dual-port SSD low power consumption control device according to claim 4, characterized in that: The frequency control signal output by the power consumption control unit for each SSD module consists of 2 bits. When the load prediction unit outputs Level A, the frequency control signal is the maximum value 11; when the load prediction unit outputs Level B, the frequency control signal outputs the intermediate value 10; when the load prediction unit outputs Level C, the frequency control signal is the second minimum value 01; when the clock needs to be shut down, the frequency control signal is the minimum value 00. Accordingly, each SSD module has two control signals, which are combined into four frequency division coefficients. The four frequency division coefficients generate four clock frequency levels. Level 3 represents no frequency reduction, which meets the working scenario requirements of level A load; Level 2 represents partial frequency reduction, which meets the working scenario requirements of level B load; Level 1 represents deep frequency reduction, which meets the working scenario requirements of level C load. 0 gear position: the clock is stopped.

6. The PCIe dual-port SSD low power consumption control device according to claim 1, characterized in that: When the load prediction unit outputs Level B or Level C, the power-consuming core modules that enter a low-power state and standby include the NVMe controller, DDR controller, AXI bus, and CPU.

7. A PCIe dual-port SSD low power consumption control method, characterized by: The following steps are involved: S01, enable the PCIe dual-port SSD in dual-port working mode; S02, initialize the sampling time interval T of the load prediction unit, and initialize the number of times the link working state enters L0s and L1 thresholds Y0 and Y1; S03, PCIe dual-port SSD performs business command processing; S04. The load prediction unit determines the workload status of the two ports in real time and provides a load level indication signal to the power consumption control unit. The load levels include level A, level B, and level C. The calculation method is as follows: when the link does not enter the L0s state within the sampling time interval T and the receive and transmit buffers are more than half full within the sampling time interval T, the load prediction unit determines that the link is in a heavy load state and outputs load level A. When the number of times the link enters the L0s state within the sampling interval T reaches a threshold value Y0 and the receive and transmit buffers are below half full within the sampling interval T, the load prediction unit determines that the link is in a lightly loaded state and outputs a load level of level B. When the number of times the link enters the L1 state within the sampling interval T reaches a threshold value Y1, the load prediction unit determines that the link is in a non-data transmission process and outputs a load level of level C. S05. The power consumption control unit uses the load level output by the load prediction unit as input to adjust the working state of each SSD module to achieve power consumption control of the SSD. The working state of each SSD module is adjusted as follows: when the load prediction unit outputs level A, each SSD module is controlled to be in a full-load operation state and operate at the maximum supportable frequency; when the load prediction unit outputs level B, each SSD module is controlled to be in a partially reduced-frequency operation state; when the load prediction unit outputs level C, the power consumption core module is controlled to enter a low-power state and standby.

8. The PCIe dual-port SSD low power consumption control method according to claim 7, wherein: Step S04 also includes: when the PCIe link power management module ASPM controls the PCIe LTSSM to exit L1 and enter the recovery state, the load prediction unit updates the level to level A, so that each module synchronously enters the full-load working state; when the PCIe link power management module ASPM controls the PCIe LTSSM from the L0 state to the L0s state, the load prediction unit updates the level to level B, so that each hardware unit starts to enter the low power consumption control state; when the PCIe link power management module ASPM controls the PCIe LTSSM from the L0s state to the L1 state, the load prediction unit updates the level to level C, so that each hardware unit enters the deep low power consumption control state.

9. The PCIe dual-port SSD low power consumption control method according to claim 7, wherein: In step S05, the power consumption control unit uses the load level output by the load prediction unit as input, calculates and outputs frequency control signals for each SSD module, and sets a clock switching unit. The clock switching unit receives the frequency control signal output by the power consumption control unit and controls the clock frequency of each SSD module. The power consumption control unit outputs a 2-bit frequency control signal for each SSD module. When the load prediction unit outputs Level A, the frequency control signal is the maximum value of 11. When the load prediction unit outputs Level B, the frequency control signal outputs the intermediate value of 10. When the load prediction unit outputs Level C, the frequency control signal is the second minimum value of 01. When the clock needs to be shut down, the frequency control signal is the minimum value of 00. Correspondingly, each SSD module has two control signals, which are combined into four division coefficients. The four division coefficients generate four clock frequency gears. Gear 3 represents the state of no frequency reduction, which meets the working scenario requirements of level A load. Gear 2 represents the state of partial frequency reduction, which meets the working scenario requirements of level B load. Gear 1 represents the state of deep frequency reduction, which meets the working scenario requirements of level C load. Gear 0 represents the clock stop state.

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