Storage device and method for storage error management

Abstract

According to one general aspect, a memory device and a multi-chip system are provided. In one embodiment, a memory device may include a plurality of stacked integrated circuit dies including a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface with the stacked integrated circuit die and the interface is configured to transfer memory accesses between the memory cell die and at least one external device. The logic die may include reliability circuitry configured to improve data errors within the memory cell die. The reliability circuit may include a backup memory configured to store data, and an address table configured to map memory addresses associated with errors to the backup memory. The reliability circuit may be configured to determine whether the memory access is associated with an error, and if so, complete the memory access with the backup memory.

Description

[0001] The present invention is a divisional application of the invention patent application with application number 201910496617.X filed on June 3, 2019 and invention name “Storage Device and Multi-Chip System”. Technical Field

[0002] The present disclosure relates to memory error correction, and more particularly to a high bandwidth memory (HBM) reliability, accessibility, and serviceability (RAS) cache architecture. Background Art

[0003] High Bandwidth Memory (HBM) is a high-performance random-access memory (RAM) interface for stacked dynamic random-access memory (DRAM). High-bandwidth memory is often used in conjunction with high-performance graphics accelerators and network devices. The first device to use HBM was the Graphical Processing Unit (GPU).

[0004] Compared to double data rate fourth-generation synchronous DRAM (DDR4) or double data rate type five synchronous graphics random-access memory (GDDR5), HBM achieves higher bandwidth in a substantially smaller form factor while using less power. This is often achieved by stacking many (e.g., 8) DRAM dies, including an optional base die with a memory controller and interconnected by through-silicon vias (TSVs) and microbumps.

[0005] The HBM memory bus is very wide compared to other DRAM memories (e.g. DDR4 or GDDR5). Each die of an HBM stack of four DRAM dies (4-Hi) typically has two 128-bit channels for a total of 8 channels and a total width of 1024 bits. A graphics card / GPU with four 4-Hi HBM stacks will therefore have a memory bus with a width of 4096 bits. In contrast, the bus width of GDDR memory is 32 bits, which is 16 channels for a graphics card with a 512-bit memory interface.

[0006] The larger number of connections to the memory requires a new method of connecting HBM memory to the GPU (or other processor) relative to DDR4 or GDDR5. Some companies use specialized silicon chips (called interposers) to connect the memory to the GPU. Such interposers have added the advantage of requiring physical proximity of the memory to the processor, thereby reducing the memory path. However, since semiconductor device manufacturing is significantly more expensive than printed circuit board manufacturing, this can increase the cost of the final product. Summary of the invention

[0007] According to one general aspect, a storage device may include a plurality of stacked integrated circuit dies. The stacked integrated circuit dies may include a memory cell die and a logic die. The memory cell die may be configured to store data in a random access manner based on a storage address. The logic die may include an interface with the plurality of stacked integrated circuit dies, and the interface is configured to transmit memory access between the memory cell die and at least one external device. The logic die may include a reliability circuit, the reliability circuit being configured to improve data errors within the memory cell die. The reliability circuit may include a spare memory and an address table, the spare memory being configured to store data in a random access manner, the address table being configured to map a storage address associated with an error to a portion of the spare memory. The reliability circuit may be configured to determine whether the memory access is associated with an error when performing a memory access to the plurality of stacked integrated circuit dies, and if so, at least partially utilize the spare memory to complete the memory access.

[0008] According to another general aspect, a multi-chip system may include a processor, the processor including a memory controller and an error correction circuit, the memory controller being configured to manage data flow to and from the processor, the error correction circuit being configured to detect whether an error occurs in the stored data. The system may include a high-bandwidth memory stack of an integrated circuit, the high-bandwidth memory stack of the integrated circuit including: a high-bandwidth memory cell configured to store data based on a memory address; and a reliability circuit configured to improve data errors within the high-bandwidth memory cell. The reliability circuit may include a spare memory and an address table, the spare memory being configured to store data, the address table being configured to map a memory address associated with the error to a portion of the spare memory. The reliability circuit is configured to determine whether a memory access is associated with an error when performing a memory access to the high-bandwidth memory stack of the integrated circuit, and if so, at least partially utilize the spare memory to complete the memory access.

[0009] According to another general aspect, a storage device may include a logic die, the logic die including an internal interface with a high bandwidth memory die, wherein the high bandwidth memory die is configured to store data based on a storage address. The logic die may include an external interface, the external interface configured to transmit memory accesses between the high bandwidth memory die and at least one external device. The logic die may include a reliability circuit, the reliability circuit configured to improve data errors within the high bandwidth memory die. The reliability circuit may include a spare memory and an address table, the spare memory configured to store data, the address table configured to map a storage address associated with an error to a portion of the spare memory. The reliability circuit may be configured to determine whether a memory access to the high bandwidth memory die is associated with an error when the memory access is performed, and if so, at least partially utilize the spare memory to complete the memory access.

[0010] The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from a reading of the description and drawings, and from a reading of the claims.

[0011] Systems and / or methods for memory error correction, and more particularly a high bandwidth memory (HBM) reliability, accessibility, and serviceability (RAS) cache architecture, are substantially as shown in and / or described in conjunction with at least one of the figures, as more fully described in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0013] Figure 2A is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0014] Figure 2B is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0015] Figure 2C is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0016] Figure 3 is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0017] Figure 4A is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0018] Figure 4B is a block diagram of an exemplary embodiment of a system in accordance with the disclosed subject matter.

[0019] Figure 5 is a schematic block diagram of an information processing system that may include devices formed according to the principles of the disclosed subject matter.

[0020] Like reference symbols in the various drawings represent like elements.

[0021] [Explanation of Symbols]

[0022] 100: System / Multi-Chip System;

[0023] 102: logic die;

[0024] 104: memory die;

[0025] 106: Routing die;

[0026] 112: Logic circuit;

[0027] 113: RAS cache or circuit;

[0028] 114: storage array / memory;

[0029] 123: Input / output terminal or interface / input / output interface;

[0030] 123a, 123b: input / output interface;

[0031] 126: through hole;

[0032] 127: routing structure;

[0033] 200, 201, 400, 401: system;

[0034] 202: HBM die / die / HBM module;

[0035] 204: Processor / GPU;

[0036] 206: host device / host;

[0037] 212: Reliability, accessibility, and serviceability (RAS) cache or circuit / RAS circuit / reliability circuit;

[0038] 214: storage unit;

[0039] 216: ECC storage device;

[0040] 218: HBM interface;

[0041] 220: Address table / table;

[0042] 222: RAS or backup storage or storage device / backup storage device / backup storage / storage device;

[0043] 232: memory controller;

[0044] 234: ECC engine or circuit / ECC engine;

[0045] 236, 530: non-volatile memory;

[0046] 242: driver software or firmware / device driver / driver;

[0047] 282, 284, 286, 292, 434, 436, 474, 476: arrows;

[0048] 294: ECC engine;

[0049] 300, 302: data structure;

[0050] 312: columns;

[0051] 314: valid bit or flag column / valid flag;

[0052] 316: mapped address column / mapped storage address;

[0053] 412: command bus;

[0054] 414: data bus;

[0055] 420, 470: routing circuit;

[0056] 424: signal / address table hit / miss;

[0057] 432: mapped storage address;

[0058] 500: Information processing system;

[0059] 505: system bus;

[0060] 510: processor / logic;

[0061] 515: Combinational logic block;

[0062] 520: Volatile memory;

[0063] 540: network interface;

[0064] 550: user interface unit;

[0065] 560: Hardware components;

[0066] 570: software components;

[0067] ADDRESS#1, ADDRESS#2, ADDRESS#N: storage address entries. DETAILED DESCRIPTION

[0068] Hereinafter, various exemplary embodiments will be more fully described with reference to the accompanying drawings, in which some exemplary embodiments are shown. However, the subject matter disclosed herein may be implemented in many different forms and should not be considered to be limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the subject matter disclosed herein to those skilled in the art. In the drawings, the size and relative size of various layers and various regions may be exaggerated for clarity.

[0069] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. Like numbers refer to like elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0070] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited to these terms. These terms are only used to distinguish various elements, components, regions, layers or sections. Therefore, the first element, component, region, layer or section discussed below may also be referred to as the second element, component, region, layer or section without departing from the teachings of the subject matter disclosed in the present invention.

[0071] For ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in a figure to another (other) element or feature. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figure. For example, if the device shown in the figure is turned over, the elements described as being "below" or "beneath" other elements or features will now be oriented to be "above" the other elements or features. Therefore, the exemplary term "below" can encompass both "above" and "below" orientations. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly.

[0072] Likewise, for ease of description, electrical terms such as "high", "low", "pullup", "pull down", "1", "0", etc. may be used herein to describe the relationship of the voltage level or current shown in the figure relative to other voltage levels or currents or relative to another (other) element or feature. It should be understood that the electrically relative terms are intended to encompass different reference voltages of the device in use or operation in addition to the voltages or currents shown in the figure. For example, if the device or signal shown in the figure is inverted or uses other reference voltages, currents, or charges, the element described as "high" or "pulled up" will now be "low" or "pulled down" compared to the new reference voltage or current. Therefore, the exemplary term "high" can encompass both relatively low voltages or currents or relatively high voltages or currents. The device may be otherwise based on a different electrical reference framework and the electrically relative descriptors used herein are interpreted accordingly.

[0073] The terms used herein are only for the purpose of describing specific exemplary embodiments and are not intended to limit the subject matter disclosed in the present invention. Unless the context clearly indicates otherwise, the singular forms "a, an" and "the" used herein are intended to include plural forms as well. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, it indicates the presence of stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0074] Exemplary embodiments are described herein with reference to cross-sectional views, which are schematic illustrations of ideal exemplary embodiments (and intermediate structures). Thus, variations relative to the illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be considered to be limited to the specific shapes of the regions shown herein, but should include shape deviations caused by, for example, manufacturing. For example, an implanted region illustrated as a rectangle should generally have circular features or curvilinear features and / or a gradient of implant concentration at its edge rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may cause some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions illustrated in the figure are schematic and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the subject matter disclosed in the present invention.

[0075] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter disclosed herein belongs. It should also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted as having an idealized or overly formal meaning unless explicitly defined herein.

[0076] Hereinafter, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0077] Figure 1 is an isometric block diagram of an exemplary embodiment of a system 100 according to the disclosed subject matter. In the illustrated embodiment, multiple integrated circuit dies may be stacked (or otherwise integrated) to form a multi-chip system. In various embodiments, such a multi-chip system 100 may include a RAS cache or circuit as described below.

[0078] In various embodiments, high bandwidth memory (HBM) may include a high performance form of random access memory (RAM). In some embodiments, HBM may include stacked dynamic RAM (DRAM) memory that communicates using through silicon vias (TSVs). Generally speaking, high bandwidth memory combines through silicon vias (TSVs) with microbumps to connect multiple (e.g., 4, 8, etc.) memory cell array dies stacked on top of each other. In some embodiments, a memory controller may be included on a separate die at the very bottom of the stack.

[0079] In the illustrated embodiment, system 100 may include one or more memory (eg, DRAM, etc.) dies 104 and logic die 102. In one embodiment, memory die 104 and logic die 102 may or may not be created or manufactured using the same manufacturing process.

[0080] In the illustrated embodiment, memory die 104 may include multiple storage arrays 114. In such an embodiment, storage arrays 114 may be configured to store various data. In some embodiments, the data may be accessed by logic die 102 or an external device (e.g., an external processor or host, as described below).

[0081] In the illustrated embodiment, logic die 102 may include one or more logic circuits 112. In such an embodiment, logic circuits 112 may include an interface for accepting read / write requests or more generally memory accesses to read or store data within memory 114. In various embodiments, logic die 102 may include a RAS cache or circuit 113, as described below.

[0082] In various embodiments, logic circuit 112 may use one or more vias 126 (or microbumps, etc.) to communicate with memory 114. In such embodiments, this may enable high-speed communication between processing elements (e.g., logic circuit 112) and stored data (memory 114) without the need to communicate through a bus or external interface.

[0083] In various embodiments, the system 100 may also include a routing die 106. The routing die 106 may be configured to dynamically route signals between the logic die 102 and the memory die 104. In various embodiments, the routing die 106 may be coupled to the logic die 102 via one or more vias 126. The via 126 (or a portion of the via 126) may terminate at an input / output (I / O) terminal or interface 123. In such an embodiment, the routing die 106 may dynamically route signals between the input / output interface 123 and the memory 114 storing the desired data.

[0084] In various embodiments, the routing may be implemented by a routing structure 127. In various embodiments, the routing structure 127 may include various routing components, such as, for example, a multiplexer, a de-multiplexer, a crossbar switch, a switch, a rotary switch, a memory switch, a crossover switch, etc. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0085] In some embodiments, routing structure 127 may be configured to route input / output signals between input / output interface 123 of logic circuit 112 and similar input / output interface 123a or 123b of memory 114. In the illustrated embodiment, two possible routing schemes are shown. For example, a solid line shows a first route, which may be used to connect logic circuit 112 to input / output interface 123a of a first memory (shown in the lower left corner of memory die 104). In another example, a dotted line shows a second route, which may be used to connect logic circuit 112 to input / output interface 123b of a second memory (shown in the right side of memory die 104). However, in various embodiments, memory 114 may be monolithic and not separated as shown in the figure. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above-mentioned several illustrative examples.

[0086] Figure 2A is a block diagram of an exemplary embodiment of a system 200 according to the disclosed subject matter. In various embodiments, the system 200 may be part of a plurality of discrete integrated circuits, a multi chip module (MCM), and / or a system-on-a-chip (SoC). In various embodiments, the system 200 may be used in computing devices such as, for example, a laptop computer, a desktop computer, a workstation, a personal digital assistant, a smart phone, a tablet computer, and other suitable computers or virtual machines or virtual computing devices of virtual machines.

[0087] In one embodiment, the system 200 may include a host device 206. In various embodiments, such a host device may include a central processing unit (CPU), a motherboard, a computing system. In various embodiments, the host device 206 may include a processor (not shown) that executes instructions and generally reads and stores data. As part of this process, the host device 206 may execute driver software or firmware 242. In the illustrated embodiment, the device driver 242 may include a computer program that runs or controls a specific type of device (e.g., a processor 204 or an HBM die 202) attached to the computer. In such an embodiment, the driver 242 may provide a software interface to the hardware device so that the operating system and other computer programs can access the hardware functions without knowing the exact details about the hardware being used.

[0088] In the illustrated embodiment, the system 200 may include a processor 204. In various embodiments, the processor 204 may include one of a variety of types of processors (e.g., a graphics processor, a central processor, a device-specific processor, a physical processor, etc.). For ease of illustration, the processor 204 will be described as a graphics processing unit (GPU); however, it should be understood that the above is only an illustrative example and the disclosed subject matter is not limited to the above one illustrative example. In various embodiments, the GPU 204 may be employed to generate graphics data or implement large-scale parallel computing tasks.

[0089] In various embodiments, the processor 204 may include a memory controller 232. In such embodiments, the memory controller 232 may be configured to manage data flow to and from the processor 204. Specifically, in the illustrated embodiment, the memory controller 232 may be configured to manage data flow between the processor 204 and the HBM die 202.

[0090] In the illustrated embodiment, the processor 204 may include an error correcting or correction code (ECC) engine or circuit 234. In such an embodiment, the ECC engine or circuit 234 may be configured to detect whether an error has occurred in some or any of the data received from the HBM die 202. In various embodiments, the ECC engine 234 may be integrated with the memory controller 232 or may be part of the memory controller 232. In various embodiments, the ECC engine 234 may be configured to detect single-bit errors or double-bit errors. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0091] In the illustrated embodiment, the processor 204 may include a non-volatile memory 236. However, in various embodiments, the memory may be volatile or external to the processor 204, as described below. In such embodiments, the non-volatile memory 236 may be configured to store information about which memory addresses are associated with errors. In some embodiments, bad or erroneous memory addresses may be avoided. In another embodiment, bad or erroneous memory addresses may be remapped to good memory cells or working memory cells.

[0092] As described above, in the illustrated embodiment, these bad or erroneous memory addresses may be remembered between power cycles of the processor 204 by acting as non-volatile memory 236. In another embodiment, volatile memory may be used and the bad or erroneous memory addresses may have to be rediscovered at each power cycle. In another embodiment, the processor 204 may include local or integrated volatile memory, but when the processor 204 is powered off, the data may be stored in a non-volatile memory (e.g., a hard drive) remote or external to the processor 204 and retrieved when the processor 204 is restarted. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0093] In the illustrated embodiment, the system 200 may include an HBM die, or more precisely, a stack of dies 202, as described above. In various embodiments, the HBM die 202 may include a plurality of memory cells 214, as described above. In various embodiments, the memory cells 214 may be spread over a plurality of integrated circuit (IC) dies and configured to store data at corresponding memory addresses.

[0094] In various embodiments, the HBM die 202 may include an ECC storage device 216 for the memory cell. In such an embodiment, the ECC storage device 216 may include additional information (e.g., parity) bits to allow or facilitate detection of errors within the data stored in the memory cell 214. In various embodiments, the ECC storage device 216 may be part of the memory cell 214 and may be similarly spread across multiple integrated circuit (IC) dies even if the ECC storage device 216 is physically separate, as described above. In such an embodiment, the ECC engine 234 may use such ECC data to detect any errors.

[0095] In various embodiments, the HBM die 202 may include an HBM interface 218 configured to communicate with or between the processor 204 and / or the host device 206. In various embodiments, the system 200 may include one or more communication buses (not shown) to facilitate inter-die (e.g., processor 204 to HBM die 202) communications. In such embodiments, this may include the sending of memory accesses (e.g., requests and responses).

[0096] In various embodiments, the HBM die 202 may include a reliability, accessibility, and serviceability (RAS) cache or circuit 212 (or reliability circuit 212). In such embodiments, the RAS circuit 212 may not be configured to act as a traditional cache to store small amounts of data in a quickly accessible manner while a larger memory provides additional storage. Instead, the RAS cache or circuit 212 may be configured to act as a backup memory or spare memory to correct (or appear to correct) or otherwise improve errors found within the storage unit 214. As described below, traditionally, once an error is detected in the storage unit 214, it may not be possible to repair or correct the error without taking extensive and time-consuming actions. Utilizing the RAS cache or circuit 212, such repair or correction may be performed more quickly and efficiently.

[0097] In various embodiments, RAS circuit 212 may include RAS or backup memory or storage 222. In various embodiments, backup storage 222 may be configured to store data associated with errors or otherwise disrepaired portions of storage unit 214. The operation of these components will be described below.

[0098] In various embodiments, RAS circuit 212 may include address table 220 configured to store a series of memory addresses (within memory cells 214 ) associated with errors and map such memory address errors to a portion of spare memory 222 .

[0099] Figure 2B is a block diagram of an exemplary embodiment of a system 200 in accordance with the disclosed subject matter. Figure 2B The illustrated system 200 shows the information flow and the relative timing of events as a system for detecting errors. It should be understood that the above is only an illustrative example, and the disclosed subject matter is not limited to the above one illustrative example.

[0100] In terms of error handling and detection, storage error management of conventional GPUs generally proceeds as follows. First, an unrecoverable error is detected by the ECC engine 234. Such errors are often associated with a specific storage address of the storage unit 214 and generally involve a double-bit error or two single-bit errors. Such errors can be reported to the driver 242.

[0101] In such an embodiment, the driver 242 may in turn report the error to an application (not shown) or a portion of the host device 206. The driver 242 may also log the storage error in the GPU's non-volatile memory 236. Traditionally, the system would be unable to ameliorate or prevent the recurrence of such an error while the current GPU interaction is ongoing.

[0102] However, upon the next reattachment, reset, restart of the system, or the next order or sequence of GPU interactions, a frame buffer manager (not shown, but part of processor 204) may blacklist the retired page with the error. In such an embodiment, the memory address or page may no longer be used for storage. Thus, the memory address or page is permanently retired and the functional capacity of the memory is reduced.

[0103] This conventional process has several drawbacks. First, it is not possible to blacklist a page while the client (e.g., a host device or software running on a host device) remains active. Second, the number of pages or storage addresses that can be deactivated on current GPUs is limited in part by the current NVM capabilities of the GPU. Third, there is a large deactivation granularity; that is, a 2-bit error can cause a 4 kilobyte (KB) page to be deactivated. Additionally, this conventional process ultimately causes memory capacity to be reduced and more and more portions of storage unit 214 to be blacklisted.

[0104] In the illustrated embodiment, the system 200 remedies the situation by implementing additional logic and memory on the HBM module or die 202 to cache and repair errors. In detail, the RAS circuit 212 is implemented on the HBM logic die with a size of at least several kilobytes; however, it should be understood that the above is only an illustrative example and the disclosed subject matter is not limited to the above illustrative examples. Such a RAS circuit 212 includes an index area or address table 220 to store addresses received by the host 206 or processor 204, and can be protected by the internal error correction mechanism of the HBM die 202. The RAS circuit 212 may also include a data area or spare storage device 222, which is configured to store repaired data (which can be of any given size). The table 220 and the storage device 222 area may have a 1-1 mapping. In addition, these areas can be implemented using any technology compatible with the HBM logic die (e.g., DRAM, static random access memory (SRAM), flash memory, etc.).

[0105] In the illustrated embodiment, again, the error correction process may begin when the ECC engine 234 detects that an error has occurred at a given storage address. As indicated by arrow 282, the ECC engine 234 may alert the drive 242, as described above. Again, as indicated by arrow 284, the drive 242 may record this in the non-volatile memory 236.

[0106] However, instead of blacklisting a memory address or page and waiting until it is no longer immediately used by the processor 204, the processor 204 (shown by arrow 286) may notify the HBM die 202 (or a logic die of the HBM die 202) that a given memory address is bad. The HBM die 202 (and more specifically the RAS circuit 212) may then take corrective action.

[0107] In the illustrated embodiment, the RAS circuit 212 may register or enter the bad storage address into the address table 220. The bad storage address may be mapped to a portion or storage address of the spare storage device 222. In various embodiments, the data contained in the storage unit 214 at the storage address may be copied (including errors and all) to the mapped portion of the spare storage device 222. In various embodiments, this may be undesirable because the data does contain errors. In such an embodiment, the processor 204 may require that the new data be written to the HBM die 202 before the new data (data without errors) can be read back. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above several illustrative examples.

[0108] In such an embodiment, once a new memory access (e.g., read or write) is made to a memory address, RAS circuit 212 checks whether the memory address is located in address table 220 (and is thus associated with an error). If not, the memory access is processed normally. The memory access is implemented by storage unit 214. If the memory address is associated with an error, the memory access is implemented by spare storage device 222, specifically, the portion of the address mapped by address table 220.

[0109] In this embodiment, all memory accesses to bad storage addresses can be implemented seamlessly (to the processor 204 or the host device 206) by the spare storage device 222. In this embodiment, this can be achieved even when the processor 204 is engaged with the client. There is no need to wait until the processor 204 is disengaged, unused, or as part of a reattachment. Second, by remapping specific storage addresses to the spare storage device 222, the storage capacity of the HBM die 202 is not reduced. Without adding a blacklist, the HBM die 202 appears to have the same amount of storage capacity. Third, the RAS circuit 212 can provide various granularities of memory mapping. Although traditional methods require 4KB pages to be blacklisted and disabled, the RAS circuit 212 allows mapping of cache lines, pages, or other sizes of memory.

[0110] In various embodiments, adding a new memory address to the address table 220 (arrow 286) may involve the processor 204 (or host device 206) performing a memory write request to a predefined or reserved memory address. In such an embodiment, the RAS circuit 212 may know that any write to the memory address means placing a new entry in the address table 220. In such an embodiment, the data portion of the memory write request may include a bad memory address. In another embodiment, adding a new memory address to the address table 220 (arrow 286) may involve using a new message type or protocol. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above several illustrative examples.

[0111] In various embodiments, the processor 204 or the host device 206 may be able to check the capacity of the spare storage device 222 being used or available for remapping by implementing a memory read request to another predefined or reserved storage address. In such an embodiment, the RAS storage device may update the register or storage address with the current storage capacity or usage level of the spare storage device 222, and the processor 204 or the host device 206 may be able to read from the storage address at any desired time. In various embodiments, this may be done before the operation of arrow 286 to confirm that such space is available. In some embodiments, if the spare storage device 222 is full or all in use, the processor 204 and the host device 206 may fall back to traditional blacklisting / disabling technology. In another embodiment, checking the free capacity of the spare storage device 222 may involve the use of a new message type or protocol. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above-mentioned several illustrative examples.

[0112] In various embodiments, when the system 200 is initialized (e.g., booted), information may be read from the HBM die 202 (by the host device 206 or the processor 204). In one embodiment, it may be determined whether the HBM die 202 includes or supports the RAS circuit 212. In one embodiment, it may be determined what level of remapping granularity to use (e.g., 256 bits, 512 bits, etc.). In another embodiment, it may be determined how cache or spare storage 222 entries and / or address table 220 entries may be supported. In various embodiments, these queries may be made through memory read requests to predefined or reserved addresses or through specific messages or protocols. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0113] Likewise, in various embodiments, when the system 200 is initialized (e.g., booted), information or settings may be written to the HBM die 202 (by the host device 206 or the processor 204). In one embodiment, a pre-existing list of bad storage addresses may be written to the address table 220 (e.g., from the non-volatile memory 236). In another embodiment, a remapping granularity level (e.g., 256 bits, 512 bits, etc.) may be set for the spare storage device 222. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0114] Figure 2C is a block diagram of an exemplary embodiment of a system 201 in accordance with the disclosed subject matter. In various embodiments, system 201 illustrates another variation of the disclosed subject matter.

[0115] In such an embodiment, the host device 206 and the processor 204 may include the same components as described above. The HBM die 202 (and specifically the logic die) may include its own ECC engine 294. In such an embodiment, the HBM die 202 may be able to detect errors in the storage unit 214 and remap one or more bad storage addresses to the spare storage device 222 without the assistance of the host device 206 and the processor 204. In various embodiments, by using non-volatile memory, this remapping may be substantially permanent. However, in other embodiments, the remapping may be performed after each reboot, even if this is not efficient or desirable.

[0116] In such an embodiment, the ECC engine 294 may detect errors instead of the ECC engine 234. In such an embodiment, the host device 206 and the processor 204 may be unaware of any such errors. In various embodiments, the host device 206 and the processor 204 may continue to participate in the traditional blacklisting / disabling techniques described above, but such blacklisting / disabling may not be performed or may only be performed occasionally due to HBM die 202 internal improvement efforts.

[0117] In various embodiments, the ECC engine 294 in the HBM die 202 may add the bad memory address to the address table 220, as indicated by arrow 292. The bad memory address may then be mapped to a portion of the spare memory device 222, and any future memory accesses may be made as described above.

[0118] Figure 3 is a block diagram of an exemplary embodiment of data structures 300 and 302 in accordance with the disclosed subject matter. In the illustrated embodiment, data structures 300 and 302 may represent tables and storage devices of a RAS circuit, as described above.

[0119] In the illustrated embodiment, data structure 300 may represent one possible embodiment of the address table or index area described above. In such an embodiment, data structure 300 (address table or index area) may be configured to store bad or erroneous storage addresses (or storage areas, such as pages). In various embodiments, these bad storage addresses may be received from a host device or processor. In various embodiments, data structure 300 may be protected by its own form of ECC.

[0120] In the illustrated embodiment, each row of the data structure 300 may be considered a storage address entry. In such an embodiment, the data structure 300 may include a column 312 indicating which storage address is bad. This may be the column 312 that is checked when a memory access is made to determine whether the memory access should be implemented by the HBM storage unit or by the spare storage device, as described above.

[0121] In the illustrated embodiment, each memory address entry may include a valid bit or flag column 314. In such an embodiment, such a valid flag 314 may indicate whether the corresponding memory address entry is in use. In such an embodiment, the valid flag 314 may be set when the host or processor writes the entry into the data structure 300. In another embodiment, the data structure 300 may be periodically erased (e.g., as part of a reboot) and may not include the valid flag 314.

[0122] In various embodiments, each storage address entry may include a column type field 315. In such embodiments, such a field 315 may not be included because the error improvement may be uniform or the same size (e.g., in words or rows) may be achieved in all addresses. However, in the illustrated embodiment, each address may be associated with a different level, amount, or type of error improvement (e.g., 1 bit, 1 word, or various numbers of bits). In some embodiments, field 315 may include the number of bits of the storage address that have been corrected. However, in the illustrated embodiment, predefined may be used, such as a value of 1 for 1 bit, a value of 2 for 1 word, and so on. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above several illustrative examples.

[0123] In the illustrated embodiment, each storage address entry may include a mapped address column 316. In such an embodiment, the mapped address column 316 may be a storage address or location in the spare storage device where the data associated with the bad storage address (column 312) is actually stored. In such an embodiment, when a memory access is made to the bad storage address, the access is not only redirected to the spare storage device but also redirected to the mapped storage address 316. In various embodiments, this may be a fixed mapping. In the illustrated embodiment, the mapping may be 1 to 1. However, in another embodiment, the mapping may be group-associative or employ another scheme.

[0124] In the illustrated embodiment, data structure 300 may include storage address entry ADDRESS#1, which has a valid flag of 1 or is set and is mapped to address #M1. Similarly, storage address entry ADDRESS#2 may include a valid flag of 1 or is set and is mapped to address #M2. There may be multiple other storage address entries. Finally, storage address entry ADDRESS#N may include a valid flag of 0 or is cleared and is mapped to address #MN. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0125] In the illustrated embodiment, data structure 302 may include a plurality of storage units, each of which is configured to store data at a corresponding storage address. In various embodiments, data structure 302 may employ ECC protection. As described above, when a memory write request to a bad storage address is made, new data may be stored in a spare storage device or data structure 302 (e.g., DATA#1, DATA#2, DATA#N). As described above, the location of the stored data may be based on the storage address entry.

[0126] In various embodiments, data structure 302 can be of any size. In one such embodiment, data structure 302 can include 150 kilobytes; however, it should be understood that the above is only an illustrative example and the disclosed subject matter is not limited to the above one illustrative example. In various embodiments, the granularity level can also be of variable size (e.g., 256 bits).

[0127] In some embodiments, the RAS circuit may include multiple data structures 302 and / or 300 to accommodate different sizes or error patterns. For example, in various embodiments, the RAS circuit may accommodate the following error patterns and include the following data structures: single-bit data errors, single-word data errors, single-row data errors, and / or single-column data errors. It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0128] Figure 4A 4 is a block diagram of an exemplary embodiment of a system 400 according to the disclosed subject matter. In the illustrated embodiment, a memory write request is shown. It should be understood that the above is only one illustrative example and the disclosed subject matter is not limited to the above one illustrative example.

[0129] In the illustrated embodiment, the system 400 may include a processor 204 and an HBM die 202, as described above. In various embodiments, the processor 204 may include a memory controller 232. The HBM die 202 may include an HBM array or storage unit 214 (which may include an ECC storage device) and a RAS circuit 212, as described above. In the illustrated embodiment, the RAS circuit 212 may include an index area or address table 220 and a RAS or spare storage device 222, as described above. In the illustrated embodiment, the system 401 may also include a command bus 412 and a data bus 414.

[0130] In the illustrated embodiment, the memory controller 232 may issue a memory write request to the HBM die 202. In such an embodiment, the command itself (and the memory address) may be sent via the command bus 412 and the data to be written may be sent via the data bus 414. It should be understood that the above is only one illustrative example and the disclosed subject matter is not limited to the above one illustrative example.

[0131] Once a memory write request is received, RAS circuit 212 may determine whether the memory address associated with the memory access is listed (and valid) in address table 220. Address table 220 may generate an address table hit (if the address is listed) or an address table miss (if the address is not listed). This is shown by signal 424.

[0132] In the illustrated embodiment, the RAS circuit 212 may include a demultiplexer (DeMUX) or routing circuit 420. The routing circuit 420 may be configured to route data to the memory cell 214 or the spare memory device 222 based on the address table hit / miss 424. As described above, if an address table hit occurs, the routing circuit 420 may send the data to be written to the spare memory device (shown by arrow 434). Likewise, the address table 220 may generate a mapped memory address 432 and send the mapped memory address 432 to the spare memory device 222. Conversely and also as described above, if an address table miss occurs, the routing circuit 420 may send the data to be written to the memory cell 214 (shown by arrow 436). Likewise, but not shown, the memory address from the command bus 412 may be used by the memory cell 214 to store the data.

[0133] In various embodiments, data may always be written to the storage unit regardless of whether an address table hit / miss occurs. In such embodiments, the logic for implementing memory access to the storage unit 214 does not need to be changed to accommodate the addition of the RAS circuit 212. In such embodiments, when an address table hit occurs, data may be written to both the storage unit 214 and the spare storage device 222, but the data in the storage unit 214 may be simply ignored, as shown below. It should be understood that the above is merely an illustrative example, and the disclosed subject matter is not limited to the above one illustrative example.

[0134] Figure 4B is a block diagram of an exemplary embodiment of a system 401 according to the disclosed subject matter. In the illustrated embodiment, a memory read request is shown. It should be understood that the above is only one illustrative example and the disclosed subject matter is not limited to the above one illustrative example.

[0135] In the illustrated embodiment, the system 401 may include a processor 204 and an HBM die 202, as described above. In various embodiments, the processor 204 may include a memory controller 232. The HBM die 202 may include an HBM array or storage unit 214 (which may include an ECC storage device) and a RAS circuit 212, as described above. In the illustrated embodiment, the RAS circuit 212 may include an index area or address table 220 and a RAS or spare storage device 222, as described above. In the illustrated embodiment, the system 400 may also include a command bus 412 and a data bus 414.

[0136] In the illustrated embodiment, the memory controller 232 may issue a memory read request to the HBM die 202. In such an embodiment, the command itself (and the memory address) may be sent via the command bus 412 and the data will be returned via the data bus 414. It should be understood that the above is only one illustrative example and the disclosed subject matter is not limited to the above one illustrative example.

[0137] Once a memory read request is received, RAS circuit 212 may determine whether the memory address associated with the memory access is listed (and valid) in address table 220. Address table 220 may generate an address table hit (if the address is listed) or an address table miss (if the address is not listed). This is shown by signal 424.

[0138] In the illustrated embodiment, the RAS circuit 212 may include a multiplexer (MUX), gating, or routing circuit 470. The routing circuit 470 may be configured to route data from the memory cell 214 or the spare memory device 222 to the data bus 414 based on the address table hit / miss 424. As described above, if an address table hit occurs, the routing circuit 470 may send the data retrieved from the spare memory device (shown by arrow 474) to the data bus 414. Likewise, the address table 220 may generate a mapped memory address 432 and send the mapped memory address 432 to the spare memory device 222. Conversely and also as described above, if an address table miss occurs, the routing circuit 470 may send the data retrieved from the memory cell 214 (shown by arrow 476) to the data bus 414. Likewise, but not shown, the memory address from the command bus 412 may be used by the memory cell 214 to retrieve data.

[0139] In various embodiments, data may always be written to the memory cell regardless of whether an address table hit / miss occurs, as described above. In such embodiments, routing circuitry 470 prevents bad or erroneous data from being placed on data bus 414 despite the data being stored in a bad or erroneous memory address of memory cell 214. Instead, good data from spare memory device 222 is used. In such embodiments, data may always be read from memory cell 214 but then gated by routing circuitry 470.

[0140] Figure 5 is a schematic block diagram of an information processing system 500 that may include a semiconductor device formed according to the principles of the disclosed subject matter.

[0141] Reference Figure 5 , information processing system 500 may include one or more devices constructed according to the principles of the disclosed subject matter. In another embodiment, information processing system 500 may employ or perform one or more techniques according to the principles of the disclosed subject matter.

[0142] In various embodiments, information handling system 500 may include a computing device, such as, for example, a laptop computer, a desktop computer, a workstation, a server, a blade server, a personal digital assistant, a smart phone, a tablet computer, and other suitable computers or a virtual machine or a virtual computing device of a virtual machine. In various embodiments, information handling system 500 may be used by a user (not shown).

[0143] The information processing system 500 according to the disclosed subject matter may also include a central processing unit (CPU), logic or processor 510. In some embodiments, the processor 510 may include one or more functional unit blocks (FUB) or combinatorial logic blocks (CLB) 515. In such embodiments, the combinatorial logic block may include various Boolean logic operations (e.g., NAND, NOR, NOR, XOR), stabilization logic devices (e.g., flip-flops, latches), other logic devices, or combinations thereof. These combinatorial logic operations may be configured in a simple or complex manner to process input signals to achieve desired results. It should be understood that although several illustrative examples of synchronous combinatorial logic operations are described, the disclosed subject matter is not limited thereto and may include asynchronous operations or a mixture thereof. In one embodiment, the combinatorial logic operation may include a plurality of complementary metal oxide semiconductor (CMOS) transistors. In various embodiments, these CMOS transistors may be arranged as gates for performing logic operations; however, it should be understood that other technologies may be used and are within the scope of the disclosed subject matter.

[0144] The information handling system 500 according to the disclosed subject matter may also include volatile memory 520 (e.g., random access memory (RAM)). The information handling system 500 according to the disclosed subject matter may also include non-volatile memory 530 (e.g., hard drive, optical memory, NAND memory, or flash memory). In some embodiments, the volatile memory 520, the non-volatile memory 530, or a combination or some portion thereof may be referred to as a "storage medium". In various embodiments, the volatile memory 520 and / or the non-volatile memory 530 may be configured to store data in a semi-permanent form or a substantially permanent form.

[0145] In various embodiments, the information handling system 500 may include one or more network interfaces 540 configured to enable the information handling system 500 to become part of a communication network and communicate through the communication network. Examples of Wi-Fi protocols may include, but are not limited to, Institute of Electrical and Electronics Engineers (IEEE) 802.11g, IEEE 802.11n. Examples of cellular protocols may include, but are not limited to, IEEE 802.16m (also known as Metropolitan Area Network (MAN), Long Term Evolution (LTE), Enhanced Data rates for GSM Evolution (EDGE), Evolved High-Speed ​​Packet Access (HSPA+). Examples of wired protocols may include, but are not limited to, IEEE 802.3 (also known as Ethernet), Fibre Channel, Power Line Communications (e.g., HomePlug, IEEE 1901). It should be understood that the above are only a few exemplary examples, and the disclosed subject matter is not limited to the above several exemplary examples.

[0146] The information processing system 500 according to the disclosed subject matter may also include a user interface unit 550 (e.g., a display adapter, a tactile interface, a human-machine interface device). In various embodiments, such a user interface unit 550 may be configured to receive input from a user and / or provide output to a user. Other types of devices may also be used to implement interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and the input from the user may be received in any form, including acoustic input, voice input, or tactile input.

[0147] In various embodiments, the information processing system 500 may include one or more other devices or hardware components 560 (e.g., a display or monitor, a keyboard, a mouse, a camera, a fingerprint reader, a video processor). It should be understood that the above are only a few illustrative examples, and the disclosed subject matter is not limited to the above illustrative examples.

[0148] The information processing system 500 according to the disclosed subject matter may also include one or more system buses 505. In such an embodiment, the system bus 505 may be configured to communicatively couple the processor 510, the volatile memory 520, the nonvolatile memory 530, the network interface 540, the user interface unit 550, and one or more hardware components 560. Data processed by the processor 510 or data input from outside the nonvolatile memory 530 may be stored in the nonvolatile memory 530 or in the volatile memory 520.

[0149] In various embodiments, the information handling system 500 may include or execute one or more software components 570. In some embodiments, the software component 570 may include an operating system (OS) and / or an application. In some embodiments, the OS may be configured to provide one or more services to the application and manage or act as an intermediate medium between the application and various hardware components (e.g., processor 510, network interface 540) of the information handling system 500. In such an embodiment, the information handling system 500 may include one or more local applications, which may be installed locally (e.g., installed in non-volatile memory 530) and configured to be directly executed by the processor 510 and interact directly with the OS. In such an embodiment, the local application may include pre-compiled machine executable code. In some embodiments, the local application may include a script interpreter (e.g., C shell (csh), AppleScript, AutoHotkey) or a virtual execution machine (VM) (e.g., Java virtual machine, Microsoft Common Language Runtime), which is configured to convert source code or object code into executable code, which is then executed by processor 510.

[0150] The semiconductor devices described above may be packaged using various packaging techniques. For example, a semiconductor device constructed according to the principles of the disclosed subject matter can be encapsulated using any of the following: package on package (POP) technology, ball grid array (BGA) technology, chip scale package (CSP) technology, plastic leaded chip carrier (PLCC) technology, plastic dual in-line package (PDIP) technology, die in waffle pack technology, die in wafer form technology, chip on board (COB) technology, ceramic dual in-line package (CERDIP) technology, plastic metric quad flat package (PMQFP) technology, plastic quad flat package (PQFP) technology, small outline integrated circuit (SOIC) technology, shrink small outline package (SSOP) technology, thin small outline package (TSP) technology. The present invention relates to a plurality of semiconductor devices, such as a thin quad flat package (TSOP) technology, a thin quad flat package (TQFP) technology, a system in package (SIP) technology, a multi-chip package (MCP) technology, a wafer-level fabricated package (WFP) technology, a wafer-level processed stack package (WSP) technology, or other technologies that will be known to technicians in the relevant field.

[0151] The method steps may be performed by one or more programmable processors executing a computer program to perform functions by operating on input data and generating output. The method steps may also be performed by, and the apparatus may be implemented as, special purpose logic circuitry (e.g., a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)).

[0152] In various embodiments, the computer readable medium may include instructions that, when executed, cause a device to perform at least a portion of the method steps. In some embodiments, the computer readable medium may be included in magnetic media, optical media, other media, or a combination thereof (e.g., compact disc read only memory (CD-ROM), hard drive, read only memory, flash drive). In such embodiments, the computer readable medium may be an article of manufacture that is tangible and implemented in a non-transitory manner.

[0153] Although the principles of the disclosed subject matter have been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of these disclosed concepts. Therefore, it should be understood that the above embodiments are not restrictive but merely illustrative. Therefore, the scope of the disclosed concepts will be determined by the broadest interpretation permitted by the above claims and their equivalents, and should not be constrained or limited by the above description. Therefore, it should be understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of the embodiments.

Claims

1. A storage device, comprising: A first device, comprising: a memory cell die configured to store data based at least in part on the memory address; and Logic die, including: an interface with the memory cell die, wherein the interface is configured to communicate memory accesses to the memory cell die; and a second device configured to transmit a memory address associated with the error; Wherein, the logic die is configured as follows: receiving the storage address from the second device; mapping the storage address to a portion of spare memory based on a state of the second device, wherein the state of the second device is interfaced with a client; and Based on a memory access with the memory cell die, it is determined that the memory access is associated with the error, and the memory access is completed at least in part utilizing the spare memory.

2. The storage device of claim 1 , wherein the storage address associated with the error is stored in an address data structure, the address data structure comprising: an error correction code portion, used to prevent errors in the address data structure; and A valid indicator is configured to indicate an active status of the storage address.

3. The memory device of claim 1 , wherein the logic die is configured as: receiving a memory write request for data at a memory address; determining that the memory address is associated with an error; and The data is written to the portion of the spare memory.

4. The memory device of claim 1 , wherein the memory address associated with the error is stored in an address data structure, and the logic die is configured to determine that the memory address is associated with the error by: determining to store the storage address as a storage address entry in the address data structure; and Determining the valid indicator indicates that the memory address entry is active.

5. The memory device of claim 1 , wherein the logic die is configured as: receiving a memory read request for data at a memory address; determining that the memory address is associated with an error; and The data is retrieved from a portion of the backup memory.

6. The memory device of claim 1 , wherein the memory address associated with the error is stored in an address data structure, and the logic die is configured to: receiving a message indicating that a storage address is associated with an error; placing the storage address in the address data structure; and The memory address is associated with the portion of the spare memory.

7. The memory device of claim 6, wherein the logic die is configured to receive a message indicating that a memory address is associated with an error by: A memory write request is received to a predefined memory address, wherein the predefined memory address is associated with the address data structure.

8. The memory device of claim 1, wherein the logic die is configured as: monitoring the usage level of the backup memory, and An indicator of the usage level of the backup memory is provided. 9 . The memory device of claim 1 , wherein the logic die is configured to provide information about an address mapping operation of the logic die based on an operation state of the first device.

10. A method for storage error management, the method comprising: determining, by a processing device, an error associated with a portion of a memory die based on a first access to a memory device comprising a memory die and a logic die; based on the determination, transmitting, from the processing device to the logic die, a first indication of the error associated with the portion of the memory die; based on the determination, transmitting from the processing device to a driver of the processing device a second indication of the error associated with the portion of the memory die, wherein the second indication indicates a memory address associated with the error; storing, by the driver, the storage address associated with the error in a data structure; communicating a second access to the portion of the memory die from the processing device to the logic die; as well as The second access is performed, by the reliability circuit, based on the first indication, using at least a portion of spare memory.

11. The method of claim 10, wherein the first indication comprises an address associated with the portion of the memory die.

12. The method of claim 11, further comprising mapping, by the reliability circuit, the address associated with the portion of the memory die to the portion of the spare memory.

13. The method according to claim 12, wherein: The second access comprises a write request; and Performing the second access includes writing data associated with the write request to the portion of the spare memory based on the mapping.

14. The method of claim 12, wherein: The second access comprises a read request; and Performing the second access includes reading data associated with the read request from the portion of the spare memory based on the mapping.

15. The method of claim 11, further comprising storing the address in a non-volatile memory. The method of claim 10 , wherein the first device comprises a host device.

17. The method of claim 10, wherein the reliability circuit is disposed on a logic die.

18. A storage device, comprising: A first device includes a logic die, wherein the logic die includes: a first interface with a memory die, wherein the memory die is configured to store data based on a memory address; a second interface configured to communicate memory accesses of the memory die; and a backup memory configured to store data; Wherein the logic die is configured as: receiving a memory address associated with the error from a second device; mapping the memory address associated with the error to a portion of the spare memory; storing the storage address in an address data structure, the address data structure including an error correction code portion for errors in the address data structure; determining, based on a memory access with the memory cell die, that the memory access is associated with the error, and completing the memory access at least in part using the portion of the spare memory; and An indication of the capacity of the backup memory is provided to the second device.

19. The memory device of claim 18, wherein the logic die is configured as: receiving a memory write request for data at the memory address; determining that the memory address is associated with the error; and The data is written to a portion of the backup memory.

20. The memory device of claim 18, wherein the logic die is configured as: receiving a memory read request for data at the memory address; determining that the memory address is associated with the error; and The data is retrieved from the mapped portion of the backup memory.

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