Multi-interface universal integration system and method based on FPGA (Field Programmable Gate Array)

Abstract

The invention provides a multi-interface universal integration system and method based on an FPGA (Field Programmable Gate Array). The system comprises a universal satellite-borne terminal and FPGA software, the FPGA software is embedded into the universal satellite-borne terminal, the universal satellite-borne terminal comprises an FPGA chip, a plurality of interface chips and a plurality of interfaces, and for a digital quantity interface, the FPGA software returns data of a specified interface to satellite service software or sends data of the satellite service software to the digital quantity interface; for the power interface, the FPGA software drives the power interface through the multi-way switch driving circuit; for the analog quantity interface, the FPGA software outputs a voltage value and a current value to the analog quantity interface or collects the voltage value and the current value of the analog quantity interface through the AD / DA drive circuit. According to the universal satellite-borne terminal, the satellite-borne operating system is used for conducting fine management on various interfaces through the FPGA, operating system software has high flexibility, the interfaces managed by the FPGA can be configured according to the requirements of different APPs, the diversified task requirements are met, and the universal satellite-borne terminal with efficient transmission and high integration level is successfully achieved.

Description

Technical Field

[0001] The present invention relates to the field of satellite management, and in particular to a FPGA-based multi-interface universal integrated system and method. Background Art

[0002] Satellite service management is the information processing and decision-making center for overall satellite management. It has many different types of interfaces with other satellite subsystems.

[0003] With the rapid development of micro-satellites, the requirements for the integration and refinement of interface management are getting higher and higher. In traditional satellite design, different types of interfaces are often managed by categories and managed by different FPGA modules, and the types of interfaces are managed at the module level. Compared with large satellites, although the number of micro-satellites is relatively small, there are still many types of interfaces. If the satellite service stand-alone configuration method of conventional satellites is used, a large number of modules need to be configured. However, the actual utilization rate of the interfaces of modules of various interface types is low. In addition, due to the power consumption and heat dissipation restrictions on the number of modules that can be accommodated by a micro-satellite satellite service stand-alone, the traditional satellite service system manages various interfaces through a single-board terminal, which is difficult to meet the actual needs of miniaturization, integration, and lightweight of current micro-satellites.

[0004] In the existing technology, for example, a spacecraft universal interface controller disclosed in the patent document with publication number CN105760335A can replace the processor to complete the timing control and protocol processing of various spacecraft communication interfaces and realize the standardization and generalization of spacecraft communication interfaces. However, this solution may have certain limitations in the scope of application and may be difficult to meet the multi-interface integration requirements in a wider range of fields and complex scenarios.

[0005] Another example is the flexible and universal intelligent satellite hardware architecture disclosed in the patent document with publication number CN111891398A, which solves the problem of lack of universality and flexibility of satellite hardware architecture. However, it may not be targeted enough for FPGA-based multi-interface universal integration, and cannot directly provide a complete solution for FPGA-based multi-interface universal integration.

[0006] In summary, there is an urgent need for a general multi-interface integration method based on FPGA to reduce the weight, power consumption, volume and other indicators of the entire satellite, and to solve the control problems of the numerous interfaces, integration requirements, weight and power consumption and other indicators on micro-satellites. Summary of the invention

[0007] The technical problem to be solved by the present invention is to reduce the weight, power consumption, volume and other indicators of the whole satellite, and solve the control problem of numerous interfaces and integration requirements and weight and power consumption and other indicators on micro-satellites.

[0008] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0009] The present invention is a FPGA-based multi-interface universal integrated system, comprising a FPGA-based universal satellite-borne terminal and FPGA software, wherein the FPGA software is embedded in the universal satellite-borne terminal;

[0010] The universal onboard terminal includes an FPGA chip, multiple interface chips and multiple interfaces. The FPGA chip is connected to the interfaces through the interface chips to realize corresponding types of data interaction.

[0011] The interface includes digital interface, power interface and analog interface;

[0012] After the FPGA software is loaded, it initializes each interface and implements dynamic configuration management of the interface according to the configuration of the satellite service software.

[0013] For the digital quantity interface, the FPGA software returns the data of the specified interface to the satellite service software according to the instructions of the satellite service software, or sends the data of the satellite service software to the digital quantity interface;

[0014] For the power interface, the FPGA software drives the power interface through a multi-way switch driving circuit according to the instructions of the satellite service software;

[0015] For the analog interface, the FPGA software outputs the specified voltage and current values ​​to the analog interface through the AD / DA drive circuit according to the instructions of the satellite service software, or collects the voltage and current values ​​of the analog interface.

[0016] Preferably, the digital quantity interface includes a high-speed 422 interface and a LVDS interface, the power interface includes a valve interface, an OC gate interface and a heater interface, and the analog quantity interface includes an AD / DA interface;

[0017] Interface chips include high-speed digital serial interface driver chips, LVDS interface driver chips, heater driver chips, multi-way switch driver chips, OC driver chips and AD / DA conversion chips.

[0018] The high-speed 422 interface is connected to the high-speed digital serial port interface driver chip, the LVDS interface is connected to the LVDS interface driver chip, the valve interface is connected to the multi-way switch driver chip, the OC gate interface is connected to the OC driver chip, the heater interface is connected to the heater driver chip, and the AD / DA interface is connected to the AD / DA conversion chip.

[0019] Preferably, the universal satellite terminal further comprises a Flash chip, an anti-fuse PROM chip and an MRAM chip, wherein the Flash chip is used to store the injection program, the anti-fuse PROM chip is used to store the initial version program of the FPGA software, and the MRAM chip is used to store the configuration files, parameters and programs in the process of running the FPGA software. The Flash chip, the anti-fuse PROM chip and the MRAM chip are all arranged on the periphery of the FPGA chip, and perform data exchange with the FPGA chip through a circuit.

[0020] The Flash chip and the anti-fuse PROM chip provide the FPGA chip with an injection program and an initial version program respectively according to the instructions of the satellite service software.

[0021] In the case of high requirements for single-particle resistance, when the FPGA chip is reset and reloaded on-orbit, the FPGA chip will re-read the program from the anti-fuse PROM chip, the FPGA chip will use the Flash chip on-orbit to achieve on-orbit reconstruction, and achieve functional updates through on-orbit injection, the FPGA software will update the interface processing data type through on-orbit update, the FPGA chip will receive the injection program through the high-speed 422 interface, and after receiving the injection program, the FPGA chip will update the corresponding interface according to the set injection program update method.

[0022] Preferably, the high-speed digital serial port interface driver chip is a high-speed 422 interface driver chip, and the FPGA chip manages the high-speed 422 interface to communicate with the satellite service software through the high-speed 422 interface driver chip. The high-speed 422 interface includes a synchronous 422 interface and an asynchronous 422 interface.

[0023] For the synchronous 422 interface and the asynchronous 422 interface, the FPGA chip exchanges data with the external interface through the 26C31 chip and the 26C32 chip. The FPGA chip exchanges data with the external interface through the high-speed 422 interface. The data includes telemetry data and reconstruction data. For telemetry data, the FPGA chip transmits the 422 telemetry data of the external serial port to the satellite service software by responding to the telemetry group acquisition instructions of the satellite service software; for reconstruction data, the FPGA chip receives the reconstruction program forwarded by the satellite service software, and makes judgments based on the application software identifier, and then selects the corresponding interface output.

[0024] Preferably, the FPGA chip manages the LVDS interface through an LVDS interface driver chip, and the LVDS interface driver chip includes an LVDS31 driver chip and an LVDS32 driver chip.

[0025] When the FPGA chip acts as a receiver, the LVDS interface is configured as one transmit and one receive or one transmit and two receive according to actual needs; when the FPGA chip acts as a transmitter, the FPGA chip can only be configured as one receive and one transmit, and the transmit and receive bandwidth of the LVDS single-channel interface is configured as needed, with a minimum of 1 bit and a maximum of 4 bits.

[0026] Preferably, the FPGA chip realizes the acquisition and output of the AD / DA interface respectively through the AD / DA conversion chip, and the AD / DA interface includes 126-channel AD analog quantity acquisition interface and 3-channel magnetic control drive current output interface.

[0027] The 126-channel AD analog quantity acquisition interface includes 8 voltage quantities, 46 temperature quantities and 56 voltage / temperature configurable acquisition interfaces. The FPGA chip collects analog quantities from external interfaces through the AD conversion chip. The collected analog quantities include voltage values ​​and current values. After the AD conversion chip collects and converts the collected digital quantity telemetry, it sends it to the FPGA chip for encoding. The FPGA chip packages the digital quantity telemetry and returns it to the telemetry management module of the satellite service software through the internal bus according to the acquisition instruction beat of the satellite service software.

[0028] The FPGA chip outputs analog quantities to the three-way magnetic control drive current output interface through the DA conversion chip. The output analog quantities include voltage and current. The FPGA chip converts the digital data sent by the satellite service software through the DA conversion chip, and then sends it to the corresponding three-way magnetic control drive current output interface through the back-end drive circuit for driving the external interface.

[0029] Preferably, the FPGA chip realizes the driving heater interface through the power MOS tube. The FPGA chip selects a certain heater according to the instructions received from the satellite service software. The analog quantities output by the power MOS are voltage and current. The output voltage is consistent with the primary power supply voltage, and the output current is adjusted according to the thermal control processing method pre-stored in the satellite service software.

[0030] Preferably, the FPGA chip drives the valve interface through the power MOS tube to realize the switching of the AD acquisition source. The FPGA chip selects a certain switch according to the instructions of the receiving satellite service software, and drives the switch of the valve interface through the voltage output by the power MOS.

[0031] Preferably, the FPGA chip drives the OC gate interface through the OC driver chip. The FPGA chip selects a certain OC driver according to the instruction received from the star service software, and pulls down the negative line according to the pulse width specified in the instruction, thereby outputting a drive signal. The OC gate interface includes 64 OC gate output interfaces.

[0032] The present invention also provides a multi-interface universal integration method based on FPGA, which uses the above-mentioned multi-interface universal integration system based on FPGA, including the following steps:

[0033] S1: After power-on, the FPGA software moves the program in ROM to RAM according to the program settings and loads the program;

[0034] S2: After the FPGA software loads the program, it initializes the settings of each interface;

[0035] S3: FPGA software starts to receive, process and respond to data from each interface in parallel;

[0036] S4: For the digital interface, the FPGA software returns the data of the specified interface to the satellite service software according to the instructions of the satellite service software, or sends the data of the satellite service software to the digital interface;

[0037] S5: For the power interface, the FPGA software drives the power interface through the multi-way switch driving circuit according to the instruction requirements of the satellite service software;

[0038] S6: For the analog interface, the FPGA software outputs the specified voltage and current values ​​to the analog interface through the AD / DA driving circuit according to the instructions of the satellite service software, or collects the voltage and current values ​​of the analog interface;

[0039] S7: FPGA software implements dynamic configuration management of the interface based on the configuration of the satellite service software.

[0040] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0041] 1. The present invention is aimed at micro-satellite application scenarios and solves the integration problem of complex interface management.

[0042] 2. The present invention is aimed at the physical interface integration of the satellite service system, solving the problem of controlling the numerous interfaces onboard micro-satellites and the integration requirements as well as the weight, power consumption and other indicators.

[0043] 3. The invention uses the operating system to perform refined management of multiple data interfaces. The operating system software is highly flexible and can configure the FPGA management interface according to the needs of different APPs to meet the needs of diverse tasks and successfully realize a universal satellite terminal with efficient transmission and high integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0045] Figure 1 is a general schematic diagram of a general satellite-borne terminal based on FPGA in an embodiment of the present invention;

[0046] Figure 2 Schematic diagram of a FPGA-based universal multi-interface integration method in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The present invention includes a universal satellite terminal based on FPGA and its FPGA software. The interfaces contained in the universal satellite terminal are a series of standard interface types, including digital interface, analog interface and power interface, and each interface is uniformly managed by FPGA software. The digital interface includes a high-speed synchronous RS422 interface, an asynchronous RS422 interface, and a high-speed LVDS interface. The analog interface includes an AD / DA interface. The power interface includes a valve interface, an OC gate interface, and a heater interface. The input and output interface types of the universal satellite terminal with multiple interfaces are standardized. Under the protocol processing of the FPGA software, standardized information interaction is performed with each interface including the operating system of the satellite service software. The present invention utilizes the operating system to realize the refined management of multiple data interfaces, and adopts the operating system software with higher flexibility to manage each interface, so as to realize a universal satellite terminal with efficient transmission, high integration and high flexibility.

[0048] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0049] This embodiment provides a FPGA-based multi-interface universal integrated system, including: an FPGA-based universal onboard terminal and FPGA software, wherein the FPGA software is embedded in the universal onboard terminal.

[0050] Figure 1 It is a general schematic diagram of a general satellite-borne terminal based on FPGA in an embodiment of the present invention.

[0051] like Figure 1 As shown, the universal satellite terminal is based on a universal integrated terminal, including an FPGA chip, multiple interface chips and multiple interfaces. The FPGA chip is connected to the interfaces through the interface chips to achieve corresponding types of data interaction.

[0052] In this embodiment, the interface includes a digital quantity interface, a power interface and an analog quantity interface, and each interface is uniformly managed by the FPGA software. Among them, the digital quantity interface includes a high-speed 422 interface and a LVDS interface, the power interface includes a valve interface, an OC gate interface and a heater interface, and the analog quantity interface includes an AD / DA interface. Correspondingly, the interface chip includes a high-speed digital serial port interface driver chip, an LVDS interface driver chip, a heater driver chip, a multi-way switch driver chip, an OC driver chip and an AD / DA conversion chip. The high-speed 422 interface is connected to the high-speed digital serial port interface driver chip, the LVDS interface is connected to the LVDS interface driver chip, the valve interface is connected to the multi-way switch driver chip, the OC gate interface is connected to the OC driver chip, the heater interface is connected to the heater driver chip, and the AD / DA interface is connected to the AD / DA conversion chip.

[0053] The FPGA chip is an interface management chip, and the universal satellite terminal also includes a Flash chip, an anti-fuse PROM chip and an MRAM chip. According to the actual requirements for the ability to resist single-particle flips, the FPGA software is stored in the Flash and anti-fuse PROM. Specifically, the Flash chip is used to store the injection program, and the anti-fuse PROM chip is used to store the initial version of the FPGA software, referred to as the golden version, to ensure the stable operation of the FPGA chip on-orbit software. The MRAM chip is used to store configuration files, parameters and programs during the operation of the FPGA software. The Flash chip, the anti-fuse PROM chip and the MRAM chip are all arranged on the periphery of the FPGA chip, and exchange data with the FPGA chip through circuits.

[0054] The Flash chip and the anti-fuse PROM chip provide the FPGA chip with an injection program and an initial version program respectively according to the instructions of the satellite service software.

[0055] In the case of high requirements for single-particle resistance, when the FPGA chip is reset and reloaded on-orbit, the FPGA chip will re-read the program from the anti-fuse PROM chip, the FPGA chip will use the Flash chip on-orbit to achieve on-orbit reconstruction, and achieve functional updates through on-orbit injection, the FPGA software will update the interface processing data type through on-orbit update, the FPGA chip will receive the injection program through the high-speed 422 interface, and after receiving the injection program, the FPGA chip will update the corresponding interface according to the set injection program update method.

[0056] In this embodiment, the high-speed digital serial port interface driver chip is a high-speed 422 interface driver chip. The FPGA chip communicates with the satellite service software through the high-speed 422 interface managed by the high-speed 422 interface driver chip. The high-speed 422 interface includes a synchronous 422 interface and an asynchronous 422 interface.

[0057] Specifically, for the synchronous 422 interface and the asynchronous 422 interface, the FPGA chip exchanges data with the external interface through the 26C31 chip and the 26C32 chip. According to the actual requirements for transmission efficiency and reliability, for the same external interface, the FPGA chip can realize single reception, single transmission, dual reception and dual transmission, and the interface rate can be configured as 115200bps or 921600bps as required. The data exchange between the FPGA chip and the external interface through the high-speed 422 interface mainly includes telemetry data and reconstruction and other business data. Among them, for telemetry data, the FPGA chip transmits the 422 telemetry data of the external serial port to the satellite service software by responding to the telemetry group acquisition instruction of the satellite service software. For reconstruction data, the FPGA chip receives the reconstruction program forwarded by the satellite service software, and makes a judgment based on the application software identifier, and then selects the corresponding interface output.

[0058] In this embodiment, the FPGA chip manages the LVDS interface through the LVDS interface driver chip, and the LVDS interface driver chip includes an LVDS31 driver chip and an LVDS32 driver chip.

[0059] Specifically, when the FPGA chip is used as a receiver, the LVDS interface is configured as one transmit and one receive or one transmit and two receive according to actual needs; when the FPGA chip is used as a transmitter, the FPGA chip can only be configured as one receive and one transmit. The transmit and receive bandwidth of the LVDS single-channel interface is configured as needed, with a minimum of 1 bit and a maximum of 4 bits.

[0060] In this embodiment, the FPGA chip realizes the acquisition and output of the AD / DA interface through the AD / DA conversion chip, and the AD / DA interface includes 126 AD analog acquisition interfaces and 3 magnetic control drive current output interfaces.

[0061] Specifically, the 126-channel AD analog quantity acquisition interface includes 8 channels of voltage quantity, 46 channels of temperature quantity and 56 channels of voltage / temperature configurable acquisition interface.

[0062] To be more specific, the FPGA chip collects analog quantities from the external interface through the AD conversion chip. The collected analog quantities include voltage values ​​and current values. After collection, the AD conversion chip sends the collected and converted digital telemetry to the FPGA chip for encoding. The FPGA chip packages the digital telemetry and returns it to the telemetry management module of the satellite service software through the internal bus according to the collection instruction rhythm of the satellite service software.

[0063] To be more specific, the FPGA chip outputs analog quantities to the three-way magnetic control drive current output interface through the DA conversion chip. The output analog quantities include voltage and current. The FPGA chip converts the digital data sent by the satellite service software through the DA conversion chip, and then sends it to the corresponding three-way magnetic control drive current output interface through the back-end drive circuit for driving the external interface.

[0064] In this embodiment, the FPGA chip drives the heater interface through the power MOS tube. The FPGA chip selects a certain heater according to the instructions received from the satellite service software, that is, it controls the driving interface of 32 28V heaters. The analog quantities output by the power MOS are voltage and current. The output voltage is consistent with the primary power supply voltage, and the output current is adjusted according to the thermal control processing method pre-stored in the satellite service software.

[0065] In this embodiment, the FPGA chip drives the valve interface through the power MOS tube to switch the AD acquisition source, which can save the number of AD / DA conversion chips and reduce the overall power consumption of the module. Specifically, the FPGA chip selects a switch according to the instructions of the satellite service software, and drives the switch of the valve interface through the voltage output by the power MOS.

[0066] In this embodiment, the FPGA chip drives the OC gate interface through the OC driver chip. Specifically, the FPGA chip selects a certain OC driver according to the instruction received from the satellite service software, and pulls the negative line low according to the pulse width specified in the instruction, thereby outputting a drive signal. In this embodiment, the OC gate interface includes 64 OC gate output interfaces.

[0067] Embodiment 2:

[0068] This embodiment applies the FPGA-based multi-interface universal integrated system in the above-mentioned embodiment 1. The FPGA chip implements the corresponding type of data interaction on the corresponding interface through the interface chip. The operating system of the satellite service software accesses data to the universal satellite terminal through the internal bus. The FPGA software returns the data of the specified interface to the satellite service software according to the instructions.

[0069] Figure 2 Schematic diagram of a FPGA-based universal multi-interface integration method in an embodiment of the present invention.

[0070] like Figure 2 As shown, this embodiment provides a general multi-interface integration method based on FPGA, including the following steps:

[0071] S1: After power is turned on, the FPGA software moves the program in ROM to RAM according to the program settings and loads the program.

[0072] S2: After the FPGA software loads the program, it initializes each interface, including parameter configuration.

[0073] S3: The FPGA software starts to receive, process and respond to data from various interfaces in parallel, including data from the satellite service software and other interfaces.

[0074] S4: For the digital interface, the FPGA software returns the data of the specified interface to the satellite service software according to the instructions of the satellite service software, or sends the data of the satellite service software to the digital interface.

[0075] The digital interface includes a high-speed 422 interface and a LVDS interface.

[0076] S5: For the power interface, the FPGA software drives the power interface through the multi-way switch driving circuit according to the instructions of the satellite service software.

[0077] The power interface includes a valve interface, an OC gate interface and a heater interface.

[0078] S6: For the analog interface, the FPGA software outputs the specified voltage and current values ​​to the analog interface through the AD / DA drive circuit according to the instructions of the satellite service software, or collects the voltage and current values ​​of the analog interface.

[0079] S7: FPGA software implements dynamic configuration management of the interface based on the configuration of the satellite service software.

[0080] FPGA software can be updated on-orbit according to design requirements, and the interface processing data type can be updated through on-orbit updates.

[0081] Those skilled in the art know that, in addition to realizing the system and its various devices, modules, and units provided by the present invention in a purely computer-readable program code, it is entirely possible to realize the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered as a hardware component, and the devices, modules, and units included therein for realizing various functions can also be regarded as structures within the hardware component; the devices, modules, and units for realizing various functions can also be regarded as both software modules for realizing the method and structures within the hardware component.

[0082] In the description of the present application, it should be understood that the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0083] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A multi-interface universal integrated system based on FPGA, characterized in that: It includes a universal satellite-borne terminal based on FPGA and FPGA software, wherein the FPGA software is embedded in the universal satellite-borne terminal; The universal onboard terminal includes an FPGA chip, a plurality of interface chips and a plurality of interfaces, and the FPGA chip is connected to the interfaces through the interface chips to realize data interaction of corresponding types; The interface includes a digital quantity interface, a power interface and an analog quantity interface; After the program is loaded, the FPGA software initializes each interface and implements dynamic configuration management of the interface according to the configuration of the satellite service software; For the digital quantity interface, the FPGA software returns the data of the specified interface to the satellite service software according to the instruction requirements of the satellite service software, or sends the data of the satellite service software to the digital quantity interface; For the power interface, the FPGA software drives the power interface through a multi-way switch driving circuit according to the instruction requirements of the satellite service software; For the analog interface, the FPGA software outputs the specified voltage and current values ​​to the analog interface through the AD / DA drive circuit according to the instructions of the satellite service software, or collects the voltage and current values ​​of the analog interface.

2. The FPGA-based multi-interface universal integrated system according to claim 1, characterized in that: The digital quantity interface includes a high-speed 422 interface and a LVDS interface, the power interface includes a valve interface, an OC gate interface and a heater interface, and the analog quantity interface includes an AD / DA interface; The interface chip includes a high-speed digital serial port interface driver chip, an LVDS interface driver chip, a heater driver chip, a multi-way switch driver chip, an OC driver chip and an AD / DA conversion chip. The high-speed 422 interface is connected to the high-speed digital serial port interface driver chip, the LVDS interface is connected to the LVDS interface driver chip, the valve interface is connected to the multi-way switch driver chip, the OC gate interface is connected to the OC driver chip, the heater interface is connected to the heater driver chip, and the AD / DA interface is connected to the AD / DA conversion chip.

3. The FPGA-based multi-interface universal integrated system according to claim 1, characterized in that: The universal satellite terminal also includes a Flash chip, an anti-fuse PROM chip and an MRAM chip. The Flash chip is used to store the injection program, the anti-fuse PROM chip is used to store the initial version program of the FPGA software, and the MRAM chip is used to store the configuration files, parameters and programs in the process of running the FPGA software. The Flash chip, the anti-fuse PROM chip and the MRAM chip are all arranged on the periphery of the FPGA chip and exchange data with the FPGA chip through circuits. The Flash chip and the anti-fuse PROM chip provide the FPGA chip with an injection program and an initial version program respectively according to the instructions of the satellite service software. In the case of high requirements for single-particle resistance, when the FPGA chip is reset and reloaded on-orbit, the FPGA chip will re-read the program from the anti-fuse PROM chip, the FPGA chip will use the Flash chip on-orbit to achieve on-orbit reconstruction, and achieve functional updates through on-orbit injection, the FPGA software will update the interface processing data type through on-orbit update, the FPGA chip will receive the injection program through the high-speed 422 interface, and after receiving the injection program, the FPGA chip will update the corresponding interface according to the set injection program update method.

4. The FPGA-based multi-interface universal integrated system according to claim 2, characterized in that: The high-speed digital serial port interface driver chip is a high-speed 422 interface driver chip. The FPGA chip manages the high-speed 422 interface to communicate with the satellite service software through the high-speed 422 interface driver chip. The high-speed 422 interface includes a synchronous 422 interface and an asynchronous 422 interface. For the synchronous 422 interface and the asynchronous 422 interface, the FPGA chip interacts with the external interface through the 26C31 chip and the 26C32 chip, and the FPGA chip exchanges data with the external interface through the high-speed 422 interface. The data includes telemetry data and reconstruction data. For the telemetry data, the FPGA chip transmits the 422 telemetry data of the external serial port to the satellite service software by responding to the telemetry group acquisition instruction of the satellite service software; for the reconstruction data, the FPGA chip receives the reconstruction program forwarded by the satellite service software, makes a judgment based on the application software identifier, and then selects the corresponding interface output.

5. The FPGA-based multi-interface universal integrated system according to claim 2, characterized in that: The FPGA chip manages the LVDS interface through the LVDS interface driver chip, and the LVDS interface driver chip includes an LVDS31 driver chip and an LVDS32 driver chip. When the FPGA chip acts as a receiver, the LVDS interface is configured as one transmit and one receive or one transmit and two receive according to actual needs; when the FPGA chip acts as a transmitter, the FPGA chip can only be configured as one receive and one transmit, and the transmit and receive bandwidth of the LVDS single-channel interface is configured as needed, with a minimum of 1 bit and a maximum of 4 bits.

6. The FPGA-based multi-interface universal integrated system according to claim 2, characterized in that: The FPGA chip realizes the acquisition and output of the AD / DA interface respectively through the AD / DA conversion chip, and the AD / DA interface includes 126-channel AD analog quantity acquisition interface and 3-channel magnetic control drive current output interface. The 126-channel AD analog quantity acquisition interface includes 8 voltage quantities, 46 temperature quantities and 56 voltage / temperature configurable acquisition interfaces. The FPGA chip realizes the acquisition of external interface analog quantities through the AD conversion chip. The collected analog quantities include voltage values ​​and current values. After the AD conversion chip acquires the acquired and converted digital quantity telemetry, it sends it to the FPGA chip for encoding. The FPGA chip packages the digital quantity telemetry and returns it to the telemetry management module of the satellite service software through the internal bus according to the acquisition instruction beat of the satellite service software. The FPGA chip outputs analog quantities to the three-way magnetic control drive current output interface through the DA conversion chip. The output analog quantities include voltage and current. The FPGA chip converts the digital quantity data sent by the satellite service software through the DA conversion chip, and then sends it to the corresponding three-way magnetic control drive current output interface through the back-end drive circuit for driving the external interface.

7. The FPGA-based multi-interface universal integrated system according to claim 2, characterized in that: The FPGA chip drives the heater interface through a power MOS tube. The FPGA chip selects a certain heater according to the instructions received from the satellite service software. The analog quantities output by the power MOS are voltage and current. The output voltage is consistent with the primary power supply voltage, and the output current is adjusted according to the thermal control processing method pre-stored in the satellite service software.

8. The FPGA-based multi-interface universal integrated system according to claim 2, characterized in that: The FPGA chip drives the valve interface through the power MOS tube to realize the switching of the AD acquisition source. The FPGA chip selects a certain switch according to the instructions received from the satellite service software, and drives the switch of the valve interface through the voltage output by the power MOS.

9. The FPGA-based multi-interface universal integrated system according to claim 2, characterized in that: The FPGA chip drives the OC gate interface through the OC driver chip. The FPGA chip selects a certain OC driver according to the instruction received from the satellite service software, and pulls down the negative line according to the pulse width specified in the instruction, thereby outputting a driving signal. The OC gate interface includes 64 OC gate output interfaces.

10. A FPGA-based multi-interface universal integration method, using the FPGA-based multi-interface universal integration system according to any one of claims 1 to 9, characterized in that: The steps include: S1: After power-on, the FPGA software moves the program in ROM to RAM according to the program settings and loads the program; S2: After the FPGA software loads the program, it initializes the settings of each interface; S3: FPGA software starts to receive, process and respond to data from each interface in parallel; S4: For the digital quantity interface, the FPGA software returns the data of the designated interface to the satellite service software according to the instruction requirements of the satellite service software, or sends the data of the satellite service software to the digital quantity interface; S5: For the power interface, the FPGA software drives the power interface through the multi-way switch driving circuit according to the instruction requirements of the satellite service software; S6: For the analog interface, the FPGA software outputs the specified voltage value and current value to the analog interface through the AD / DA driving circuit according to the instruction requirements of the satellite service software, or collects the voltage value and current value of the analog interface; S7: FPGA software implements dynamic configuration management of the interface based on the configuration of the satellite service software.

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