Method and system for receiving serial port data through DMA

Abstract

The invention provides a method and system for receiving serial port data through DMA, and belongs to the technical field of data transmission, and the method comprises the steps that first data are accessed based on a first position of a DMA data space, and the first position is the position where the DMA data space is used last time; determining an interrupt triggering mode according to a comparison result of the data volume of the first data and a preset data volume; the preset data volume is a data volume determined based on a DMA data space; the first data are sequentially stored in an annular circular queue before interruption triggering; the annular loop queue is a queue for temporarily storing first data; and after the interruption is triggered, storing all data in the annular circular queue into a memory unit. Through optimization of a DMA technology and an interrupt mechanism, efficient transmission and processing of data are realized, and the performance and the response speed of the system are remarkably improved.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of data transmission, and more specifically, to a method and system for receiving serial port data through DMA. Background Art

[0002] In embedded system design, serial communication is highly favored due to its high efficiency and stability, especially in data transmission, where its performance is directly related to the smoothness and efficiency of the overall operation of the system. However, traditional serial communication methods mainly rely on the CPU for real-time data processing and transmission. When the amount of data is large, the CPU needs to frequently interrupt to receive data, which consumes a lot of computing power and reduces the overall performance of the system.

[0003] To address this problem, Direct Memory Access (DMA) technology was introduced, which allows data to be transferred directly between memory and peripherals without CPU intervention, greatly improving the efficiency of data transfer. However, the traditional way of using DMA also has certain limitations. For example, the traditional DMA method also has limitations in data space configuration. Since DMA must receive a specified amount of data before data can be transferred, the size of the DMA data space must be consistent with the length of the data frame, otherwise data loss will occur. This means that for data frames of different lengths, DMA data spaces of different sizes need to be used, which not only increases the complexity of system design, but also limits the flexible use of DMA. Summary of the invention

[0004] The purpose of the present disclosure is to provide a method and system for receiving serial port data through DMA, which can solve the problem that the size of DMA data space must be consistent with the length of data frame, otherwise data loss will occur, and realize efficient transmission and processing of data.

[0005] According to a first aspect of an embodiment of the present disclosure, a method for receiving serial port data through DMA is provided, comprising: Starting to access first data based on a first position of the DMA data space, the first position being the position where the last use of the DMA data space ended; Determine an interrupt trigger mode according to a comparison result between the data volume of the first data and a preset data volume; the preset data volume is a data volume determined based on a DMA data space; Before the interrupt is triggered, the first data is sequentially stored in a circular queue; the circular queue is a queue for temporarily storing the first data; After the interrupt is triggered, all data in the circular queue are stored in the memory unit.

[0006] According to a second aspect of the embodiments of the present disclosure, there is provided a device for receiving serial port data through DMA, comprising: A data access module, used for accessing first data based on a first position of the DMA data space, where the first position is a position where the DMA data space was used to the end of the last time; An interrupt trigger module, configured to determine an interrupt trigger mode according to a comparison result between the data volume of the first data and a preset data volume; the preset data volume is a data volume determined based on a DMA data space; A first data transmission module, used for storing the first data in a circular queue in sequence before the interrupt is triggered; the circular queue is a queue for temporarily storing the first data; The second data transmission module is used to store all the data in the circular queue into the memory unit after an interrupt is triggered.

[0007] According to a third aspect of an embodiment of the present disclosure, a system for receiving serial port data via DMA is provided, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements the steps of the above-mentioned method for receiving serial port data via DMA when executing the computer program.

[0008] According to a fourth aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned method of receiving serial port data through DMA are implemented.

[0009] The method and system for receiving serial port data through DMA provided by the embodiments of the present disclosure have the following beneficial effects: First, the present disclosure optimizes the interrupt mechanism: by introducing a mechanism for dynamically triggering different interrupts based on the data volume of the first data and the preset data volume, an efficient combination of DMA and serial port idle interrupts is achieved. This mechanism can not only dynamically adjust the interrupt trigger frequency according to the data volume of the first data, reduce the CPU occupancy rate, but also realize the flexible configuration and operation of the DMA data space.

[0010] Secondly, the method for receiving serial port data through DMA provided by the present disclosure has diversified application scenarios: Users can flexibly configure the DMA data space size and interrupt trigger conditions according to the size of the DMA data space, the length of the first data, the number of interrupt calls, etc. to optimize data transmission.

[0011] Finally, in order to further improve the efficiency of data transmission, the present disclosure also introduces an advanced cache management mechanism. When DMA performs data transmission, the data is first written into a cache area, and then the data is written into the memory in batches after the cache area reaches the interrupt trigger condition. This ensures the continuity and integrity of the data, while reducing the frequent interrupt requests to the CPU, further improving the response speed of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A flowchart of a method for receiving serial port data through DMA provided by an embodiment of the present disclosure; Figure 2 A schematic diagram of a DMA workflow provided by an embodiment of the present disclosure; Figure 3 A schematic diagram of a specific process of DMA receiving serial port data provided by an embodiment of the present disclosure; Figure 4 A schematic diagram of the use of DMA data space when DMA receives serial port data provided by an embodiment of the present disclosure; Figure 5 A structural block diagram of a device for receiving serial port data through DMA provided in one embodiment of the present disclosure; Figure 6 A schematic block diagram of a system for receiving serial port data through DMA provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] In the following description, specific details such as specific system structures and technologies are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present disclosure. However, it should be clear to those skilled in the art that the present disclosure may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obstructing the description of the present disclosure with unnecessary details.

[0015] In order to make the purpose, technical solutions and advantages of the present disclosure more clear, specific embodiments will be described below in conjunction with the accompanying drawings.

[0016] Please refer to Figure 1 , Figure 1A flow chart of a method for receiving serial port data through DMA provided in one embodiment of the present disclosure includes: S101: Start accessing first data based on a first position of a DMA data space, where the first position is the position where the DMA data space was last used.

[0017] In this embodiment, DMA is a technology that allows data to be directly transferred between peripherals (such as hard disks, network cards, graphics cards, etc.) and memory units. This technology can significantly improve the efficiency and speed of data transfer because the CPU can perform other tasks during the DMA transfer process. DMA data space refers to the memory area involved in DMA operations.

[0018] The data transmission direction in this embodiment is from the peripheral device to the memory unit, and the first position is the starting address or position for accessing data in the DMA data space. For example, the first position can be a memory address, an offset, or a pointer.

[0019] The memory address is the most direct way to represent the first location. In most computer systems, memory is addressed in bytes, so the first location can be a specific byte address that specifies the specific location where data should be read or written when the DMA transfer begins.

[0020] Or in some cases, if the DMA data space is a contiguous region relative to a known base address, the first location can be expressed as an offset from that base address. The offset is a relative value that indicates the distance between the first location and the base address (in bytes, words, or other data units).

[0021] Alternatively, the first position may appear in the form of a pointer. A pointer is a variable used to store memory addresses in a programming language, so it can be used to represent the first position in the DMA data space. By operating the pointer, the program code can dynamically change the starting point of the DMA transfer.

[0022] The first data is the total data of a single DMA transmission. Accessing the first data based on the first position of the DMA data space includes: the DMA starts from the first position of the DMA data space and continuously accesses the data according to the preset data width and transmission length.

[0023] When performing DMA data transmission, the system first determines the first position of the DMA data space as the starting point of the data transmission. The first position is the position when the DMA data space was used last time, which can be a specific memory address. Then the DMA controller starts to perform data access operations from the first position. Because this process does not require direct intervention from the CPU, efficient data transmission is achieved.

[0024] For example, set the DMA data space to a pre-allocated memory area, such as a continuous memory space starting from memory address 0x1000 and ending at 0x2000. Initialize the baud rate, data bits, stop bits and other parameters of the serial port to make it ready to receive data.

[0025] If it is the first time to transfer data, you can set the first position as the starting address of the DMA data space, that is, 0x1000, set the preset data width to 8 bits (i.e., one byte), and the transfer length to 100 bytes. The DMA controller starts from the first position 0x1000 and continuously reads data from the serial port according to the 8-bit data width and 100-byte transfer length. After the first DMA transfer is completed, assume that the first position is updated to the position at the end of the first transfer, for example, 0x1064. Set the data width of the transfer to 8 bits and the transfer length to 80 bytes again. The DMA controller starts from the new first position 0x1064 and reads data from the serial port according to the set data width and transfer length.

[0026] As data is continuously received, each time DMA is transmitted, the first position is always the position where the last DMA data space was used up, thus ensuring that the data is stored sequentially and continuously in the DMA data space, and making full use of the DMA technology's efficient data transmission characteristics, reducing CPU intervention and improving the overall performance of the system.

[0027] S102: Determine an interrupt trigger mode according to a comparison result between the data volume of the first data and the preset data volume; the preset data volume is a data volume determined based on the DMA data space.

[0028] In this embodiment, during the serial port data reception process, the size of the DMA data space is fixed, and reception frames of different lengths can use the same DMA data space. The preset data volume is a data volume determined based on the size, capacity, usage strategy, or system performance requirements (such as the number of interrupt calls) of the DMA data space. It represents a safety threshold of the DMA data space, a capacity limit for triggering an interrupt, or a recommended data volume when a specific condition is triggered. The preset data volume is less than or equal to the total capacity of the DMA data space. For example, the preset data volume can be a value such as 1 / 2 or 1 / 4 of the total capacity of the DMA data space.

[0029] The interrupt trigger mode refers to the way the system responds to specific conditions and triggers an interrupt when specific conditions are met. The interrupt trigger modes include idle interrupt, half-full interrupt, and full interrupt. Idle interrupt refers to an interrupt mode triggered when the amount of the first data is less than the preset amount of data; half-full interrupt refers to an interrupt mode triggered when the amount of the first data is equal to an integer multiple of the preset amount of data; full interrupt refers to an interrupt mode triggered when the amount of the first data is equal to the total capacity of the DMA data space.

[0030] Determining an interrupt trigger mode according to a comparison result between the data amount of the first data and the preset data amount includes: If the data amount of the first data is less than the preset data amount, an idle interrupt is triggered; If the data volume of the first data is equal to an integer multiple of the preset data volume, a half-full interrupt is triggered; If the data volume of the first data is greater than an integral multiple of the preset data volume and is less than the total capacity of the DMA data space, a half-full interrupt and an idle interrupt are triggered; If the data volume of the first data is greater than an integer multiple of the preset data volume and is equal to the total capacity of the DMA data space, a half-full interrupt and a full interrupt are triggered; If the amount of the first data is greater than the total capacity of the DMA data space, a half-full interrupt, a full interrupt and an idle interrupt are triggered.

[0031] Assume that the total capacity of the DMA data space is A, and the preset data volume is A / 2. If the data volume of the first data is less than A / 2, an idle interrupt is triggered; if the data volume of the first data is equal to A / 2, a half-full interrupt is triggered; if the data volume of the first data is greater than A / 2, a half-full interrupt and an idle interrupt are triggered; if the data volume of the first data is equal to A, a half-full interrupt and a full interrupt are triggered; if the data volume of the first data is greater than A, a half-full interrupt, a full interrupt, and an idle interrupt are triggered.

[0032] For example, when A=8 bytes, the preset data volume is A / 2=4 bytes. The first data obtained by a single DMA transfer is 3 bytes. Since 3 bytes < 4 bytes, an idle interrupt will be triggered at this time. If the data volume of the first data is 4 bytes, a half-full interrupt will be triggered. The first data is 6 bytes. 6 bytes is greater than 4 bytes and less than 8 bytes (total capacity of DMA data space). At this time, according to the rules, a half-full interrupt will be triggered first, and then an idle interrupt will be triggered. If the first data is 8 bytes, it satisfies the condition that it is greater than an integer multiple (2 times) of the preset data volume (4 bytes) and is equal to the total capacity of the DMA data space. According to the rules, a half-full interrupt will be triggered first, and then a full interrupt will be triggered. When the data volume of the first data is greater than 8 bytes and is 9 bytes, a half-full interrupt will be triggered first, then a full interrupt will be triggered, and finally an idle interrupt will be triggered.

[0033] Assume that the total capacity of the DMA data space is B, and the preset data volume is B / 4. The data volume of the first data is less than B / 4, triggering an idle interrupt; the data volume of the first data is greater than B / 4 and less than B / 2, triggering a half-full interrupt and an idle interrupt; the data volume of the first data is equal to B / 2, triggering a half-full interrupt; the data volume of the first data is greater than B / 2, triggering a half-full interrupt and an idle interrupt; the data volume of the first data is greater than B / 2 and less than 3B / 4, triggering a half-full interrupt and an idle interrupt; the data volume of the first data is equal to 3B / 4, triggering a half-full interrupt; the data volume of the first data is greater than 3B / 4, triggering a half-full interrupt and an idle interrupt; the data volume of the first data is equal to B, triggering a half-full interrupt and a full interrupt; the data volume of the first data is greater than B and less than 5B / 4, triggering a half-full interrupt, a full interrupt, and an idle interrupt.

[0034] S103: before the interrupt is triggered, the first data is sequentially stored in a circular queue; the circular queue is a queue for temporarily storing the first data.

[0035] In this embodiment, the circular queue is a method of simulating a queue data structure using a limited array space, which forms a closed loop between the end and the beginning of the array. When one end point of the array is filled with data, new data will be stored from the other end point of the array, thereby achieving efficient use of space. The circular queue is used as a queue for temporarily storing the first data read from the DMA data space. Since serial port data reception is a continuous process, and data processing may not be completely synchronized with the receiving speed, a buffer is required to temporarily store the data until all the data is received, and then all the data in the circular queue is transferred to the memory unit.

[0036] This embodiment uses a circular queue as a buffer management method, which not only simplifies the operation process, but also greatly improves data processing efficiency. Users do not need to manually clear the queue after each use, but simply put the data into the queue. When the buffer is full, it automatically re-accesses data from the head of the queue.

[0037] S104: Store all data in the circular queue into the memory unit.

[0038] In this embodiment, all data in the circular queue are stored in the memory unit, including: Determine the memory address of the memory unit, determine the start and end positions of the queue through the head pointer and tail pointer of the circular queue, and traverse each element in the queue in turn. During the traversal process, copy each data element in the queue to the corresponding position of the memory unit.

[0039] In this embodiment, a specific implementation process of receiving serial port data through DMA is as follows: 1. DMA configuration: (1) Configure the device: configure the corresponding channel clock, pin, serial port working mode, receive queue, etc.; (2) Configure the serial port: configure the corresponding serial port properties: baud rate, stop bit, check bit, etc. (3) Enable receiving and enable sending; (4) Enable the serial port and enable serial port interrupt; (5) Configure DMA: Set the DMA trigger source corresponding to the channel; Adopting the cyclic transmission mode, it automatically restores to the initial configuration after one transmission is completed, and continuously transmits data without reconfiguring and enabling DMA; Specifies the direction of data transfer from peripheral to memory; Specify the base address of the memory, that is, the memory address of the DMA transfer data; Specify the base address of the peripheral, that is, the peripheral address of DMA transfer data; Specify the number of channel transfers, that is, the number of data that needs to be transferred, based on the size of the DMA transfer data buffer (that is, the DMA data space); Specifies the memory address increment mode to increment the memory address after each transfer; The incremental mode of specifying the peripheral address is that the peripheral address is fixed after each transmission; Specify the transfer width of memory data, that is, the size of data transferred each time, which is 8 bits; Specify the transmission width of the peripheral data, that is, the data size of each transmission, which is 8 bits; Specify the priority level of the channel and make sure that the DMA channel has the highest priority; (6) Working mode: Set to loop mode, disable the memory-to-memory mode of the DMA channel, and enable DMA interrupt; (7) Enable NVIC (Nested Vectored Interrupt Controller) interrupt request; (8) Interrupt processing: enable receive half-full interrupt and receive full interrupt; (9) Enable DMA interrupt; (10) Create a queue: Create a receiving queue; (11) Receiving direction: Control the data direction to receive; 2. Receive data Allocate a continuous memory area as DMA data space, for example, from memory address 0x2000 to 0x3000, with a total capacity of 512 bytes. Open up a space in the memory to create a circular queue. Assume that the size of this circular queue is 512 bytes, and set the queue head pointer and queue tail pointer to 0 to indicate that the queue is empty. According to the system performance requirements and the size of the DMA data space, we set the preset data volume to 1 / 2 of the total capacity of the DMA data space, that is, 512*1 / 2=256 bytes.

[0040] When receiving data for the first time, we set the first position to the starting address 0x2000 of the DMA data space (regarded as the position where the last DMA data space was used, which is the initialization setting). The DMA controller starts from 0x2000, receives data from the serial port and stores it in the DMA data space according to the preset data width (for example, 8 bits) and transmission length. Assume that the first data received this time is 272 bytes. Since the first data (272 bytes) is larger than the preset data volume (256 bytes), according to the rules, the half-full interrupt and the idle interrupt will be triggered. When the half-full interrupt is triggered, the DMA controller stores each byte of data received into the circular queue. When the idle interrupt is triggered, the DMA controller stores the remaining data into the circular queue, and then takes out the 272 bytes of data in the circular queue and stores them in the specified area of ​​the memory unit in a certain order. In this process, the head pointer moves forward according to the number of bytes taken out, until the head pointer and the tail pointer coincide again, indicating that the circular queue is empty.

[0041] From the above, it can be concluded that, firstly, the present disclosure realizes the optimization of the interrupt mechanism: by introducing a mechanism for dynamically triggering different interrupts based on the data volume of the first data and the preset data volume, an efficient combination of DMA and serial port idle interrupt is realized. This mechanism can not only dynamically adjust the interrupt trigger frequency according to the data volume of the first data and reduce the CPU occupancy, but also realize the flexible configuration and operation of the DMA data space.

[0042] Secondly, the method for receiving serial port data through DMA provided by the present disclosure has diversified application scenarios: Users can flexibly configure the DMA data space size and interrupt trigger conditions according to the size of the DMA data space, the length of the first data, the number of interrupt calls, etc. to optimize data transmission.

[0043] Finally, in order to further improve the efficiency of data transmission, the present disclosure also introduces an advanced cache management mechanism. When DMA performs data transmission, the data is first written into a cache area, and then the data is written into the memory in batches after the cache area reaches the interrupt trigger condition. This ensures the continuity and integrity of the data, while reducing the frequent interrupt requests to the CPU, further improving the response speed of the system.

[0044] In one embodiment of the present disclosure, determining the interrupt trigger mode according to a comparison result between the data amount of the first data and the preset data amount includes: If the data amount of the first data is less than the preset data amount, an idle interrupt is triggered; If the data volume of the first data is equal to an integer multiple of the preset data volume, a half-full interrupt is triggered; If the data volume of the first data is greater than an integral multiple of the preset data volume, a half-full interrupt and an idle interrupt are triggered.

[0045] In this embodiment, if the data volume of the first data is less than the preset data volume, an idle interrupt is triggered. This condition is usually used to indicate that the DMA data space is currently in a relatively idle state, that is, the amount of data received has not yet reached the trigger threshold of the half-full interrupt or the trigger threshold of the full interrupt. When the idle interrupt is triggered, the system will first count the amount of data processed during this idle interrupt, and put the remaining data in the DMA data space (that is, data that does not meet the half-full and full interrupt conditions) into the receiving circular queue; secondly, the end position of the DMA space usage is recorded so that the next data reception can start from this position, thereby realizing the recycling of the DMA data space and avoiding repeated switching of DMA enable.

[0046] Assume that the total capacity of the DMA data space is C, and the preset data volume is C / 2. The first data of the serial port is received through DMA. If the data volume of the first data is less than the preset data volume, an idle interrupt is triggered. If the data volume of the first data is equal to the preset data volume, a half-full interrupt is triggered; if the data volume of the first data is greater than the preset data volume, at least one half-full interrupt is triggered. For example, when the data volume of the first data (the first data volume is 3C / 4) is greater than the preset data volume and less than the total capacity of the DMA data space, a half-full interrupt and an idle interrupt are triggered.

[0047] It can be concluded from the above that when the amount of the first data is greater than or equal to an integer multiple of the preset data amount, a half-full interrupt is triggered. Triggering a half-full interrupt indicates that the DMA data space has been filled to a certain extent, but has not yet reached full saturation. Triggering a half-full interrupt means that the system can start processing data or prepare to receive more data, so that DMA is no longer limited to having to wait for the data space to be fully used before data transmission, thereby greatly improving the flexibility and efficiency of data transmission.

[0048] In an embodiment of the present disclosure, if the data amount of the first data is greater than or equal to an integer multiple of a preset data amount, a half-full interrupt is triggered, including: If the data volume of the first data is equal to an integer multiple of the preset data volume, a half-full interrupt is triggered; If the data size of the first data is greater than an integer multiple of the preset data size, a half-full interrupt and a full interrupt are triggered.

[0049] In this embodiment, it is assumed that the total capacity of the DMA data space is C, and the preset data volume is C / 2. The first data of the serial port is received through DMA. If the data volume of the first data is equal to an integer multiple of the preset data volume, for example, the data volume of the first data is C / 2, a half-full interrupt is triggered; if the data volume of the first data is greater than the preset data volume and equal to the total capacity of the DMA data space, at least one half-full interrupt is triggered. For example, when the data volume of the first data (the first data volume is C) is greater than the preset data volume and equal to the total capacity of the DMA data space, a half-full interrupt and a full interrupt are triggered. For example, when the data volume of the first data is 1.5C, a half-full interrupt, a full interrupt, and a half-full interrupt are triggered in sequence. For example, when the data volume of the first data is 2C, a half-full interrupt, a full interrupt, a half-full interrupt, and a full interrupt are triggered in sequence.

[0050] For example, if C is 512 bytes, the preset data amount is 256 bytes. When the first data received by DMA is 256 bytes, a half-full interrupt is triggered; when the first data received by DMA is 512 bytes, a half-full interrupt and a full interrupt are triggered successively; when the first data received by DMA is 768 bytes, a half-full interrupt, a full interrupt and a half-full interrupt are triggered successively; when the first data received by DMA is 1024 bytes, a half-full interrupt, a full interrupt, a half-full interrupt and a full interrupt are triggered successively.

[0051] In an embodiment of the present disclosure, if the data amount of the first data is greater than or equal to an integer multiple of a preset data amount, a half-full interrupt is triggered, including: If the data volume of the first data is equal to an integer multiple of the preset data volume, a half-full interrupt is triggered; If the data volume of the first data is greater than an integer multiple of the preset data volume, a half-full interrupt, a full interrupt and an idle interrupt are triggered.

[0052] In this embodiment, it is assumed that the total capacity of the DMA data space is D, and the preset data volume is D / 2. The first data of the serial port is received through DMA. If the data volume of the first data is equal to an integer multiple of the preset data volume, for example, the data volume of the first data is D / 2, a half-full interrupt is triggered; if the data volume of the first data is greater than the preset data volume and greater than the total capacity of the DMA data space, at least one half-full interrupt is triggered. For example, when the data volume of the first data (the first data volume is D) is greater than the preset data volume and greater than the total capacity of the DMA data space, a half-full interrupt, a full interrupt, and an idle interrupt are triggered. For example, when the data volume of the first data is 1.2D, a half-full interrupt, a full interrupt, and an idle interrupt are triggered in sequence. For example, when the data volume of the first data is 1.7D, a half-full interrupt, a full interrupt, a half-full interrupt, and an idle interrupt are triggered in sequence.

[0053] For example, if D is 512 bytes, the preset data amount is 256 bytes. When the first data received by DMA is 256 bytes, a half-full interrupt is triggered; when the first data received by DMA is 520 bytes, a half-full interrupt, a full interrupt and an idle interrupt are triggered successively; when the first data received by DMA is 800 bytes, a half-full interrupt, a full interrupt, a half-full interrupt and an idle interrupt are triggered successively; when the first data received by DMA is 1032 bytes, a half-full interrupt, a full interrupt, a half-full interrupt, a full interrupt and an idle interrupt are triggered successively.

[0054] refer to Figure 2 , Figure 2 The workflow for DMA.

[0055] The entire DMA data space is divided into the first half of buf and the second half of buf. When receiving serial port data through DMA, first determine the starting address of DMA access. When the amount of data stored in the DMA data space reaches the trigger condition of the buf half-full interrupt, the CPU transfers the data in the first half of buf to the memory space. Then DMA continues to store data from the last position of the first half of buf. When the amount of data reaches the trigger condition of the buf full interrupt, the CPU transfers the data in the second half of buf to the memory space. Finally, DMA continues to access data from the starting position of the data space until all serial port data is transmitted and stops accessing.

[0056] It can be concluded from the above that this embodiment effectively improves the response efficiency and flexibility of the data processing system by accurately setting the trigger conditions of the data volume. When the data volume reaches the preset data volume threshold or its integer multiple, the half-full interrupt is triggered in time, which helps to allocate resources or process data in advance and avoid performance bottlenecks caused by data accumulation. At the same time, full interrupts and idle interrupts can be triggered for situations that are greater than integer multiples of the preset data volume, which enhances the system's ability to identify and respond to complex data states, and improves the stability of the overall system and the real-time performance of data processing.

[0057] In one embodiment of the present disclosure, storing the first data into the circular queue when the interrupt trigger ends includes: The second position of the DMA data space when the interrupt trigger ends is recorded, and the first data between the first position and the second position is stored in the annular circulation queue.

[0058] In this embodiment, the interrupt trigger mode includes a half-full interrupt trigger, a full interrupt trigger, and an idle interrupt trigger. After each interrupt trigger, it is necessary to record the end position of the DMA data space usage. For example, DMA starts to access data from the first position of the DMA data space. When a half-full interrupt is triggered, the system records the end position of the DMA data space usage when the half-full interrupt is triggered as the second position, and then stores the first data between the first position and the second position into the circular queue. The data between the first position and the second position involved in this embodiment refers to the data including the first position data, the data between the first position and the second position, and does not include the second position data. For example, the data at the first position is k1, the data at the second position is kn, and the data between the first position and the second position is expressed by the mathematical expression: .

[0059] It can be concluded from the above that this embodiment realizes efficient, real-time and accurate processing of valid data in the DMA data space by combining the advantages of the interrupt trigger mechanism and the circular circular queue.

[0060] In one embodiment of the present disclosure, when a full interrupt is triggered, the method further includes: If the data position recorded in the DMA data space during the half-full interrupt is the third position, then the data position recorded in the DMA data space during the full interrupt is the fourth position, and the first data between the third position and the fourth position is stored in the circular queue.

[0061] In this embodiment, when a full interrupt is triggered, it means that a half-full interrupt has been triggered last time. Assuming that the data position recorded in the DMA data space during the half-full interrupt is the third position, when the DMA continues to access data, the amount of data reaches the full interrupt trigger condition, and the position of the data recorded when the DMA data space is full is the fourth position, the first data between the third position and the fourth position is stored in the circular queue. The data between the third position and the fourth position involved in this embodiment refers to the data including the third position data, the data between the third position and the fourth position, and does not include the data at the fourth position. For example, the data at the third position is q1, the data at the fourth position is qn, and the data between the third position and the fourth position is expressed by the mathematical expression: .

[0062] From the above, it can be concluded that, first, by recording the data position during the half-full interrupt and the full interrupt, the system can accurately identify the newly added data transferred by DMA between the two interrupts. This precise data segmentation processing helps to reduce the redundancy of data processing and improve the efficiency and accuracy of data processing. Second, since only the newly added data between the two interrupts is processed instead of the data in the entire DMA data space, this method reduces the usage of memory and avoids unnecessary memory waste. At the same time, due to the characteristics of the circular queue, these newly added data can be efficiently stored and processed in a circular manner. Third, by processing the newly added data in the DMA data space in a timely manner and storing it in the circular queue, the system can avoid the long-term backlog of data in the DMA data space, thereby reducing the risk of data loss or damage and enhancing the stability and reliability of the system.

[0063] In one embodiment of the present disclosure, before starting to access the first data based on the first position of the DMA data space, the method further includes: Set the DMA working mode to circular transfer mode; Set the capacity of the buffer area where the circular queue is located; The data transmission direction of the first data is designated as from the external device to the memory unit.

[0064] DMA has two modes: normal mode and cyclic mode. The present disclosure uses the cyclic mode instead of the normal mode. The characteristics and differences between the normal mode and the cyclic mode are: In normal mode, DMA performs a data transfer task based on pre-set transfer parameters, such as the starting address, the amount of data to be transferred, etc. Once the transfer is started, the DMA controller will transfer data from the source address (such as the data register of the peripheral) to the destination address (such as a certain area in the memory) unit by unit according to the set data width and transfer length. When the preset amount of data is transferred, the transfer process stops.

[0065] Normal mode is suitable for one-time data transmission tasks. For example, in a simple system, a set of fixed-length data is read from a sensor, such as a temperature sensor that collects data every 10 minutes, and the amount of data collected each time is fixed to 50 bytes. The normal mode DMA can be used to transfer the data from the sensor interface to the data buffer in the memory.

[0066] In loop mode, DMA transfer is performed in a loop. After completing a preset amount of data transfer, DMA will not stop, but automatically return to the starting source address and destination address (or according to the preset loop start address) to continue the next round of data transfer. This is like a looping playlist, and data transfer is continuously looped.

[0067] The loop mode is suitable for continuous data acquisition and transmission scenarios. For example, in an audio processing system, audio data is collected from an audio input device (such as a microphone) to a memory buffer. Audio data is a continuous stream of data. Using the DMA in the loop mode can ensure that the data is continuously transferred from the microphone interface to the memory without interruption due to the completion of a single transfer, thereby achieving uninterrupted acquisition and subsequent processing of audio signals.

[0068] In some existing patent applications, the implementation methods of the circular mode are all based on the condition that the hardware peripherals are equipped with FIFO. Some chip peripherals may not have FIFO, which makes these patent methods inapplicable. In the actual application of the present disclosure, FIFO is not used, so it will not be limited to those chips without FIFO, and the application scope is wider. This embodiment effectively solves this problem by allowing users to customize the size of the buffer area. Users can flexibly adjust the buffer area capacity according to actual needs to ensure that the system can run smoothly even when processing large amounts of data, avoiding the occurrence of data congestion. This embodiment uses a circular queue as a buffer area management method, which not only simplifies the operation process, but also greatly improves data processing efficiency. Users do not need to manually clear the queue after each use, but simply put the data into the queue. After the buffer area is full, the data is automatically accessed again from the head of the queue.

[0069] In one embodiment of the present disclosure, reference Figure 3 , the process of DMA receiving serial port data is as follows: (1) During the data receiving process, the system monitors the usage status of the DMA data space in real time (each time an interrupt is triggered and data is received, a variable is used to record the end position of the DMA receiving space): DMA trigger interrupt space size = DMA data space total size - remaining space after DMA interrupt reception; The data size processed by this DMA interrupt = the size of the DMA trigger interrupt space - the end position of the last interrupt; The end position of this interrupt = the end position of the previous interrupt + the size of the data to be processed by this DMA interrupt; (2) Once the DMA data space reaches the half-full threshold, the system will trigger a half-full interrupt and record the amount of data processed. Subsequently, the system extracts data from the first address + offset of the DMA data space (the end position of the last DMA space used) and puts it into the circular receive queue. Finally, the system will update and save the end position of the DMA space used at this interrupt to ensure the continuity and accuracy of data processing; (3) When the DMA space is fully occupied, a full interrupt will be triggered. The system will calculate and count the amount of data involved in this interrupt processing. Then, starting from the first address of the DMA data space, combined with the previously recorded offset (that is, the end point of the last DMA space usage), extract the data and put it into the circular receive queue. In order to ensure the continuity of data reception in subsequent operations, it is necessary to update and record the end position of the DMA space usage after the full interrupt is triggered to ensure the continuity of data reception; (4) The half-full interrupt and the full-full interrupt will be triggered cyclically according to the actual data size, and the end position of the DMA space will be recorded each time it is triggered until the bus is in an idle state; (5) When the bus is idle, an idle interrupt will be triggered. The system will count the amount of data processed during this idle interrupt and put the remaining data in the DMA data space (that is, data that does not meet the half-full and full interrupt conditions) into the receive ring queue; (6) After each data reception, the system records the end position of the DMA space so that the next data reception can start from this position, thereby realizing the recycling of the DMA data space and avoiding repeated switching of DMA enable.

[0070] refer to Figure 4 , Figure 4 It is the usage of DMA data space when receiving data.

[0071] Assume that the size of the DMA data space is 8 bytes and the preset data volume is 4 bytes. When the first frame of data (11 2233 44 55 66 77 88 99) is transmitted, when 44 is first transmitted, a half-full interrupt is triggered, and the system stores 11, 22, 33, and 44 in a circular queue (equivalent to Figure 4 The system then continues to transmit the first frame of data. When the data reaches 88, a full interrupt is triggered. At this time, the system stores 55, 66, 77, and 88 in the circular queue. The system then continues to transmit 99. At this time, there is no data transmission and the bus is idle. An idle interrupt is triggered and the system stores 99 in the circular queue.

[0072] When transmitting the second frame of data (01 02 03 04 05 06 07 08), access starts from the second position where the last DMA data space usage ended. When the third number, 03, is transmitted, the half-full interrupt triggering condition is reached. At this time, the system stores 01, 02, and 03 in the circular queue, and continues to access in this way, triggering the full interrupt and space interrupt in turn, and ending this round of data transmission.

[0073] Corresponding to a method for receiving serial port data via DMA in the above embodiment, Figure 5 A structural block diagram of an apparatus for receiving serial port data via DMA provided by an embodiment of the present disclosure. For ease of explanation, only the parts related to the embodiment of the present disclosure are shown. Figure 5 The device 20 for receiving serial port data through DMA includes: a data access module 21, an interrupt trigger module 22, a first data transmission module 23, and a second data transmission module 24.

[0074] The data access module 21 is used to start accessing the first data based on the first position of the DMA data space, where the first position is the position where the last use of the DMA data space ended; An interrupt trigger module 22, configured to determine an interrupt trigger mode according to a comparison result between the data volume of the first data and a preset data volume; the preset data volume is a data volume determined based on a DMA data space; The first data transmission module 23 is used to store the first data into a circular queue when the interrupt trigger ends; the circular queue is a queue for temporarily storing the first data; The second data transmission module 24 is used to store all the data in the circular queue into the memory unit.

[0075] In one embodiment of the present disclosure, the interrupt triggering module 22 is specifically used for: If the data amount of the first data is less than the preset data amount, an idle interrupt is triggered; If the data volume of the first data is greater than or equal to an integer multiple of the preset data volume, a half-full interrupt is triggered.

[0076] In one embodiment of the present disclosure, the interrupt triggering module 22 is specifically used for: If the data volume of the first data is equal to an integer multiple of the preset data volume, a half-full interrupt is triggered; If the data volume of the first data is greater than an integral multiple of the preset data volume, a half-full interrupt and an idle interrupt are triggered.

[0077] In one embodiment of the present disclosure, the interrupt triggering module 22 is specifically used for: If the data volume of the first data is equal to an integer multiple of the preset data volume, a half-full interrupt is triggered; If the data size of the first data is greater than an integer multiple of the preset data size, a half-full interrupt and a full interrupt are triggered.

[0078] In one embodiment of the present disclosure, the interrupt triggering module 22 is specifically used for: If the data volume of the first data is equal to an integer multiple of the preset data volume, a half-full interrupt is triggered; If the data volume of the first data is greater than an integer multiple of the preset data volume, a half-full interrupt, a full interrupt and an idle interrupt are triggered.

[0079] In one embodiment of the present disclosure, the first data transmission module 23 is specifically used to: The second position of the DMA data space when the interrupt trigger ends is recorded, and the first data between the first position and the second position is stored in the annular circulation queue.

[0080] In one embodiment of the present disclosure, the first data transmission module 23 is further configured to: If the data position recorded in the DMA data space during the half-full interrupt is the third position, then the data position recorded in the DMA data space during the full interrupt is the fourth position, and the first data between the third position and the fourth position is stored in the circular queue.

[0081] See also Figure 6 , Figure 6 The following is a schematic block diagram of a system for receiving serial port data via DMA according to an embodiment of the present disclosure. Figure 6 The system 300 for receiving serial port data via DMA in the embodiment shown may include: one or more processors 301, one or more input devices 302, one or more output devices 303 and one or more memories 304. The processors 301, input devices 302, output devices 303 and memories 304 communicate with each other via a communication bus 305. The memory 304 is used to store computer programs, which include program instructions. The processor 301 is used to execute the program instructions stored in the memory 304. The processor 301 is configured to call the program instructions to execute the functions of each module / unit in the above-mentioned device embodiments, such as Figure 5 The functions of modules 21 to 22 are shown.

[0082] It should be understood that in the embodiment of the present disclosure, the processor 301 may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0083] The input device 302 may include a touch panel, a fingerprint collection sensor (for collecting the user's fingerprint information and fingerprint direction information), a microphone, etc., and the output device 303 may include a display (LCD, etc.), a speaker, etc.

[0084] The memory 304 may include a read-only memory and a random access memory, and provide instructions and data to the processor 301. A portion of the memory 304 may also include a non-volatile random access memory. For example, the memory 304 may also store information about the device type.

[0085] In a specific implementation, the processor 301, input device 302, and output device 303 described in the embodiments of the present disclosure can execute the implementation methods described in the first and second embodiments of a method for receiving serial port data through DMA provided in the embodiments of the present disclosure, and can also execute the implementation methods of the system described in the embodiments of the present disclosure, which will not be repeated here.

[0086] In another embodiment of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by the processor, all or part of the processes in the above-mentioned embodiment method are implemented, and the computer program can also be completed by instructing the relevant hardware through the computer program. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed by the processor, the steps of each of the above-mentioned method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium, etc.

[0087] The computer-readable storage medium may be an internal storage unit of the system of any of the foregoing embodiments, such as a hard disk or memory of the system. The computer-readable storage medium may also be an external storage device of the system, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the system. Further, the computer-readable storage medium may also include both an internal storage unit of the system and an external storage device. The computer-readable storage medium is used to store computer programs and other programs and data required by the system. The computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

[0088] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0089] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0090] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces or units, or it can be an electrical, mechanical or other form of connection.

[0091] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present disclosure.

[0092] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0093] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present disclosure, and these modifications or replacements should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for receiving serial port data via DMA, characterized in that: include: Starting to access first data based on a first position of the DMA data space, the first position being the position where the last use of the DMA data space ended; Determine an interrupt trigger mode according to a comparison result between the data volume of the first data and a preset data volume; the preset data volume is a data volume determined based on a DMA data space; Before the interrupt is triggered, the first data is sequentially stored in a circular queue; The annular circular queue is a queue for temporarily storing the first data; After the interrupt is triggered, all data in the circular queue are stored in the memory unit.

2. A method for receiving serial port data through DMA as claimed in claim 1, characterized in that: The determining the interrupt trigger mode according to the comparison result between the data amount of the first data and the preset data amount includes: If the data amount of the first data is less than the preset data amount, an idle interrupt is triggered; If the data volume of the first data is greater than or equal to an integer multiple of the preset data volume, a half-full interrupt is triggered.

3. A method for receiving serial port data through DMA as claimed in claim 2, characterized in that: If the amount of the first data is greater than or equal to an integer multiple of the preset data amount, triggering a half-full interrupt includes: If the data amount of the first data is equal to an integer multiple of the preset data amount, a half-full interrupt is triggered; If the data volume of the first data is greater than an integer multiple of the preset data volume, a half-full interrupt and an idle interrupt are triggered.

4. A method for receiving serial port data through DMA as claimed in claim 2, characterized in that: If the amount of the first data is greater than or equal to an integer multiple of the preset amount of data, triggering a half-full interrupt includes: If the data amount of the first data is equal to an integer multiple of the preset data amount, a half-full interrupt is triggered; If the data size of the first data is greater than an integer multiple of the preset data size, a half-full interrupt and a full interrupt are triggered.

5. A method for receiving serial port data through DMA as claimed in claim 2, characterized in that: If the amount of the first data is greater than or equal to an integer multiple of the preset amount of data, triggering a half-full interrupt includes: If the data amount of the first data is equal to an integer multiple of the preset data amount, a half-full interrupt is triggered; If the data volume of the first data is greater than an integer multiple of the preset data volume, a half-full interrupt, a full interrupt and an idle interrupt are triggered.

6. A method for receiving serial port data through DMA as claimed in claim 1, characterized in that: When the interrupt is triggered, storing the first data into a circular queue comprises: The second position of the DMA data space when the interrupt trigger ends is recorded, and the first data between the first position and the second position is stored in the annular circulation queue.

7. A method for receiving serial port data via DMA as claimed in claim 4 or 5, characterized in that: When a full interrupt is triggered, it also includes: If the data position recorded in the DMA data space during the half-full interrupt is the third position, then the data position recorded in the DMA data space during the full interrupt is the fourth position, and the first data between the third position and the fourth position is stored in the circular queue.

8. A device for receiving serial port data via DMA, characterized in that: include: A data access module, used for accessing first data based on a first position of the DMA data space, where the first position is a position where the DMA data space was used to the end of the last time; An interrupt trigger module, configured to determine an interrupt trigger mode according to a comparison result between the data volume of the first data and a preset data volume; the preset data volume is a data volume determined based on a DMA data space; A first data transmission module, used for storing the first data into a circular queue when the interrupt trigger ends; The annular circular queue is a queue for temporarily storing the first data; The second data transmission module is used to store all the data in the circular queue into a memory unit.

9. A system for receiving serial port data via DMA, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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