Method and device for reconstructing a link after PCIe link equalization failure

Abstract

The present invention relates to the field of computer communication technology, and discloses a method and device for reconstructing a link after a PCIe link equalization failure. The method comprises: determining the current state of a state machine and the previous state of the current state; generating an initial reset request signal when the current state is a speed recovery state and the previous state is a balance recovery state; after generating the initial reset request signal, assigning a preset non-zero count value to a predefined counter and starting a self-decrement count; and generating a target reset pulse signal when the count value is not zero, the target reset pulse signal being used to cause the state machine to jump to a reset state. The present invention adopts direct hardware control, does not require a central processing unit for scheduling, and thus does not consume central processing unit and memory resources, has a smaller impact on overall system performance, and achieves faster and more efficient link reconstruction.

Description

Technical Field

[0001] The present invention relates to the field of computer communication technology, and in particular to a method and device for reconstructing a PCIe link after link equalization fails. Background Art

[0002] PCIe (Peripheral Component Interconnect Express, or PCIe for short), as a high-speed serial computer expansion bus standard, provides a high-bandwidth, low-latency data transmission channel, enabling various peripheral devices such as storage devices, network cards, and graphics cards to effectively exchange data with the central processing unit (CPU). The PCIe design utilizes full-duplex transmission, packet-based transmission, and differential signal transmission mechanisms, significantly improving data transmission efficiency and signal anti-interference capabilities, ensuring data transmission stability. To achieve high-speed and stable data communication, it is necessary to establish a reliable PCIe link between the two communicating devices through link training in accordance with the procedures specified by the protocol.

[0003] The establishment and stable operation of PCIe links are crucial for ensuring efficient and reliable data transmission. This process is typically automated by the Link Training and Status State Machine (LTSSM). During PCIe link establishment, signals on the link must be balanced to ensure stable and reliable data transmission. However, during this equalization process, PCIe links may experience equalization failures due to the bit error rate consistently failing to meet requirements, resulting in data transmission on the link failing to meet expected performance standards.

[0004] To address the issue of balancing failure during PCIe link establishment, the current common method is to use software intervention to schedule and control the link to re-speed up and re-balance after balancing fails. However, to implement software configuration, it is necessary to monitor balancing failure events and send a signal to the central processing unit (CPU) when balancing fails. The CPU then configures register-related signals after detecting balancing failure. This is inefficient and consumes CPU and memory resources, affecting overall system performance. Summary of the Invention

[0005] In view of this, the present invention provides a method and apparatus for reconstructing a link after a PCIe link equalization failure, so as to solve the problem of low efficiency of the method for reconstructing a link by a central processing unit in the prior art.

[0006] In a first aspect, the present invention provides a method for reconstructing a PCIe link after link equalization fails, the method comprising:

[0007] Determine the current state of the state machine and the previous state of the current state;

[0008] generating an initial reset request signal when the current state is a speed recovery state and the previous state is a balance recovery state;

[0009] After the initial reset request signal is generated, the predefined counter is assigned a preset non-zero count value and starts to count down;

[0010] When the count value is not zero, a target reset pulse signal is generated, and the target reset pulse signal is used to make the state machine jump to the reset state.

[0011] In response to the problem of equalization failure when establishing a PCIe link, this method uses hardware to continuously obtain the current and previous operating states of the LTSSM during equalization to determine whether the equalization is successful. After determining that the equalization has failed, a reset request signal with a configurable pulse width is generated, thereby generating a reset pulse signal to control the reset of the LTSSM and the corresponding module. The method provided in this embodiment operates directly at the physical layer and adopts direct hardware control. It does not require CPU scheduling, so it does not consume CPU and memory resources and has little impact on the overall system performance. Compared with traditional methods, the re-establishment of the link and equalization are directly controlled according to the status of the LTSSM. There is no need for software intervention to detect the link status and configure related registers. It is faster and more efficient than methods that require software intervention when handling equalization failure scenarios. Traditional methods require software to participate in execution and will be affected by the CPU status and other processes. Therefore, hardware control is usually more stable and reliable.

[0012] In an optional embodiment, the preset non-zero count value is set according to the reset pulse width. When the count value decreases to zero, the target reset pulse signal is invalid. In this way, the duration of the reset pulse can be configured to meet different startup or reset requirements.

[0013] In an optional embodiment, the initial reset request signal includes: a PCIe controller initial reset request signal and a PCIe physical layer initial reset request signal; the counter includes: a PCIe controller counter and a PCIe physical layer counter; the target reset pulse signal includes: a PCIe controller target reset pulse signal and a PCIe physical layer target reset pulse signal;

[0014] After the initial reset request signal is generated, a predefined counter is assigned a preset non-zero count value, including:

[0015] After generating a PCIe controller initial reset request signal, assigning a preset non-zero count value to a PCIe controller counter;

[0016] After generating a PCIe physical layer initial reset request signal, assigning a preset non-zero count value to the PCIe physical layer counter;

[0017] When the count value of the PCIe controller counter is not zero, a PCIe controller target reset pulse signal is generated, where the PCIe controller target reset pulse signal is used to cause the state machine to jump back to the link connection detection state;

[0018] When the count value of the PCIe physical layer counter is not zero, a PCIe physical layer target reset pulse signal is generated. The PCIe physical layer target reset pulse signal is used to reset each physical layer channel.

[0019] In this embodiment, operations are performed directly at the physical layer, and link re-establishment and balancing are directly controlled according to the status of the LTSSM. No software intervention is required to detect the link status and configure related registers. When handling balancing failure scenarios, it is faster and more efficient than methods that require software intervention.

[0020] In an optional embodiment, when link balancing fails, the state machine automatically switches from the balance recovery state to the speed recovery state, thereby achieving rebalancing and improving the probability of successful balancing.

[0021] In an optional implementation, the balancing recovery state includes multiple balancing sub-stages. When balancing is successful in one of the balancing sub-stages, the state machine directly jumps to the next balancing sub-stage.

[0022] In an optional implementation, when the balancing sub-stage is the last balancing sub-stage, the state machine jumps to the next preset state.

[0023] This method leverages the low probability of balancing failure, allowing successful balancing after multiple attempts. Compared to related technologies, this method controls link reestablishment without sending hardware information to the CPU or requiring the CPU to configure registers based on hardware status to control state machine transitions. Instead, it directly determines whether balancing is successful and whether a reset signal is needed based on state machine transitions, thereby achieving rebalancing after balancing failures. Without requiring CPU scheduling, this method consumes no CPU and memory resources, minimizing the impact on overall system performance.

[0024] In a second aspect, the present invention provides a device for reconstructing a PCIe link after a PCIe link equalization failure, the device comprising:

[0025] A determination module is used to determine the current state of the state machine and the previous state of the current state;

[0026] A request generating module, configured to generate an initial reset request signal when the current state is a speed recovery state and the previous state is a balance recovery state;

[0027] A counting module, configured to assign a preset non-zero count value to a predefined counter and start self-counting after generating an initial reset request signal;

[0028] The reset generation module is used to generate a target reset pulse signal when the count value is not zero. The target reset pulse signal is used to make the state machine jump to the reset state.

[0029] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to execute the method for reconstructing the chain after PCIe link equalization failure of the above-mentioned first aspect or any corresponding embodiment thereof.

[0030] In a fourth aspect, the present invention provides a computer-readable storage medium storing computer instructions, which are used to enable a computer to execute the method for rebuilding a chain after a PCIe link equalization failure according to the first aspect or any corresponding embodiment thereof.

[0031] In a fifth aspect, the present invention provides a computer program product comprising computer instructions, the computer instructions being used to cause a computer to execute the method for reconstructing a chain after a PCIe link equalization failure according to the first aspect or any corresponding embodiment thereof.

[0032] It should be noted that the apparatus, computer device, and computer-readable storage medium for reestablishing a link after a PCIe link equalization failure provided by the present invention correspond to the aforementioned method for reestablishing a link after a PCIe link equalization failure. Therefore, for the beneficial effects of the apparatus, computer device, and computer-readable storage medium for reestablishing a link after a PCIe link equalization failure, please refer to the description of the corresponding beneficial effects of the method for reestablishing a link after a PCIe link equalization failure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 This is a schematic diagram of LTSSM state transition in related technology;

[0035] Figure 21 is a flow chart of a method for reconstructing a PCIe link after link equalization fails according to an embodiment of the present invention;

[0036] Figure 3 is a schematic diagram of the principle of a chain reconstruction method according to an embodiment of the present invention;

[0037] Figure 4 is a timing diagram of link reestablishment after recovery.eq0 fails according to an embodiment of the present invention;

[0038] Figure 5 is a timing diagram of link reestablishment after recovery.eq1 fails according to an embodiment of the present invention;

[0039] Figure 6 is a structural block diagram of a device for reconstructing a link after a PCIe link equalization failure according to an embodiment of the present invention;

[0040] Figure 7 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0042] The establishment of PCIe link is generally completed automatically by LTSSM. The status of LTSSM consists of eleven states: Detect, Polling, Configuration, Recovery, L0, L0s, L1, L2, Disabled, Loopback, and Hot Reset. The specific meaning of each state is as follows: Detect: Detect link connection, Polling: Wait for the link to be ready, Configuration: Configure link parameters, Recovery: Link recovery state, L0: Link working state, L0s: Link low power state, L1: Link low power mode, L2: Link further low power mode, Disabled: Link is disabled, Loopback: Link loopback test, Hot Reset: Link hot reset state. These states are as follows Figure 1Link training is completed by jumping through the sequence shown. When link training is complete, the following objectives are achieved: bit lock, symbol lock, block lock, link width determination, lane reversal, polarity inversion, data rate negotiation, and lane-to-lane de-skew. Successfully completing data rate negotiation is the primary objective of the present invention.

[0043] After the initial power-on reset, PCIe performs link training at a data rate of 2.5GT / s to the L0 state. If both devices on the link support higher rates, it is necessary to transition to the Recovery state to train the link to the maximum supported rate before returning to the L0 state. During the transition to higher rates, signal distortion becomes increasingly severe, increasing the bit error rate. Therefore, in addition to speed increases, the Recovery state also includes the Recovery.Equalization substate, which performs equalization operations to improve data transmission and reception, minimizing the impact of signal distortion on communication performance.

[0044] However, during the equalization process, a PCIe link may experience equalization failure due to a persistent failure in the bit error rate to meet the required level. This is a very rare occurrence, but if this equalization failure is not addressed, data transmission on the link may not meet the expected performance standards, such as being unable to transmit and receive data at the highest rate. In this case, the PCIe link will not be able to operate at its most efficient state.

[0045] To address the issue of balancing failure during PCIe link establishment, existing methods use software intervention for scheduling after a balancing failure, controlling the link to re-enter the Recovery state for speed increase and balancing. This method works because the probability of a single balancing failure is extremely low, making multiple balancing failures almost impossible. However, there are some problems with the way this method controls re-balancing.

[0046] According to the PCIe protocol, the LTSSM state transition sequence for a successful speed increase and balancing is as follows: L0-Recovery.Rcvrlock-Recovery.Rcvrcfg-Recovery.Speed-Recovery.Equalization (EQ0)-Recovery.Equalization (EQ1)-Recovery.Equalization (EQ2)-Recovery.Equalization (EQ3)-Recovery.Rcvrlock-Recovery.Rcvrcfg-Recovery.Idle-L0. In this process, the link speed is increased in the Recovery.Speed ​​state. After entering the Recovery.Equalization state, balancing is performed at the new speed. After successful balancing, the link transitions from the Recovery state to the L0 state to operate at the new speed.

[0047] The current implementation scheme is as follows: After power-on reset, if the maximum speed supported by both ends of the link is not Gen1 (meaning Generation 1, referring to the first generation standard of PCIe), the link establishment process will follow the above-mentioned LTSSM state jump sequence to control the LTSSM from L0 to the Recovery state for speed increase and balancing. If balancing fails, it will no longer jump from Recovery.equalization to Recovery.Rcvrlock, but from Recovery.equalization state to Recovery.speed state, and then drop back to the original speed in Recovery.speed state, and then return to L0 through Recovery.lock, Recovery.cfg, and Recovery.idle to run at the original speed. At this time, because the link has not been established to run at the highest speed, but it is impossible to jump to Recovery for speed increase through hardware, it is necessary to control it through software, that is, the register configuration related signals to control the LTSSM from L0 to Recovery again for rate negotiation and link establishment. However, software configuration requires monitoring for balancing failures and sending a signal to the CPU when a balancing failure occurs. Upon detecting a balancing failure, the CPU then configures register-related signals to control the LTSSM to re-enter the Recovery state from L0 and re-perform speed-up and balancing operations. This method requires software intervention. Upon detecting a balancing failure, register configuration is used to control the state machine jump, re-performing speed-up and balancing to complete link establishment. This is inefficient and consumes CPU and memory resources, impacting overall system performance.

[0048] In view of this, according to an embodiment of the present invention, an embodiment of a method for rebuilding a chain after a PCIe link equalization failure is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a state machine such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0049] In this embodiment, a method for reconstructing a link after a PCIe link equalization failure is provided, which can be executed by a state machine. Figure 2 FIG. 1 is a flowchart of a method for reconstructing a link after a PCIe link equalization failure according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0050] Step S101, determine the current state of the state machine and the previous state of the current state. As mentioned above, the establishment of the PCIe link is generally completed automatically by the LTSSM. The LTSSM state consists of eleven states: Detect, Polling, Configuration, Recovery, L0, L0s, L1, L2, Disabled, Loopback, and Hot Reset. Among them, the balancing process usually occurs in the Recovery state to perform link balancing operations, optimize signal quality and ensure stable link performance. The LTSSM is in the physical layer of the PCIe bus, that is, the above states are all completed in the physical layer of the PCIe bus.

[0051] For example, in the following link balancing transition sequence: L0-Recovery.Rcvrlock-Recovery.Rcvrcfg-Recovery.Speed-Recovery.Equalization(EQ0)-Recovery.Equalization(EQ1)-Recovery.Equalization(EQ2)-Recovery.Equalization(EQ3)-Recovery.Rcvrlock-Recovery.Rcvrcfg-Recovery.Idle-L0, except for the L0 state, all other states occur in the Recovery state. Therefore, the state machine state determined in this embodiment prioritizes determining the balancing transition state in the Recovery state.

[0052] Step S102: When the current state is the speed recovery state and the previous state is the balance recovery state, an initial reset request signal is generated. The speed recovery state in this embodiment refers to the state in the state machine used to increase the link rate, such as "Recovery.Speed" in the above jump sequence. The balance recovery state refers to the process of performing gradual equalization at the new rate, attempting different equalization stages to optimize signal quality, such as Equalization (EQ0), Recovery.Equalization (EQ1), Recovery.Equalization (EQ2), and Recovery.Equalization (EQ3) in the above jump sequence.

[0053] In this embodiment, it is possible to define that if the balancing phase fails, the state will be directly entered into the Recovery.Speed ​​state. This differs from the state transition sequence of the LTSSM state machine when balancing is successful. Based on this state transition characteristic, the success of balancing can be determined by judging the state transition sequence. If balancing is successful, no action is taken; if balancing fails, an initial reset request signal is generated for a certain period of time. In this embodiment, when the current state is "Recovery.Speed" and the previous state is Equalization (EQ0), an initial reset request signal is generated. This initial reset request signal is used to issue a reset request.

[0054] Step S103 : after generating the initial reset request signal, assigning a preset non-zero count value to a predefined counter and starting to count down.

[0055] In this embodiment, after the initial reset request signal is generated, a non-zero count value may be assigned to the counter based on the desired reset pulse width. This count value affects the final reset request duration and, in turn, controls the reset pulse width. After the preset non-zero count value is assigned, the counter count value is not zero and begins to count down.

[0056] Step S104, when the count value is not zero, generates a target reset pulse signal, which is used to make the state machine jump to the reset state. In this embodiment, when the count value is not zero, the target reset pulse signal is continuously generated until the count value reaches zero, and the generation of the target reset pulse signal stops. The target reset pulse signal can make the link jump to the Detect state, thereby resetting the state machine. That is, after detecting the initial reset request signal, a target reset pulse signal is generated to reset the LTSSM and related modules. After the LTSSM returns to the Detect state, it restarts the link establishment, thereby achieving rebalancing and increasing the probability of successful balancing.

[0057] In response to the problem of equalization failure when establishing a PCIe link, this method uses hardware to continuously obtain the current and previous operating states of the LTSSM during equalization to determine whether the equalization is successful. After determining that the equalization has failed, a reset request signal with a configurable pulse width is generated, thereby generating a reset pulse signal to control the reset of the LTSSM and the corresponding module. The method provided in this embodiment operates directly at the physical layer and adopts direct hardware control. It does not require CPU scheduling, so it does not consume CPU and memory resources and has little impact on the overall system performance. Compared with traditional methods, the re-establishment of the link and equalization are directly controlled according to the status of the LTSSM. There is no need for software intervention to detect the link status and configure related registers. It is faster and more efficient than methods that require software intervention when handling equalization failure scenarios. Traditional methods require software to participate in execution and will be affected by the CPU status and other processes. Therefore, hardware control is usually more stable and reliable.

[0058] In some optional implementations, the preset non-zero count value is set according to the reset pulse width. When the count value decreases to zero, the target reset pulse signal becomes invalid, and the link begins to be re-established.

[0059] In this embodiment, the initial value of the counter can be set as required to implement a reset request signal with a configurable pulse width. Based on the reset request signal, a reset pulse signal with a configurable pulse width can be generated. This allows the duration of the reset pulse to be configured to meet different startup or reset requirements.

[0060] In some optional embodiments, the initial reset request signal includes: a PCIe controller initial reset request signal and a PCIe physical layer initial reset request signal; the counter includes: a PCIe controller counter and a PCIe physical layer counter; the target reset pulse signal includes: a PCIe controller target reset pulse signal and a PCIe physical layer target reset pulse signal;

[0061] After the initial reset request signal is generated, a predefined counter is assigned a preset non-zero count value, including:

[0062] After generating a PCIe controller initial reset request signal, assigning a preset non-zero count value to a PCIe controller counter;

[0063] After generating a PCIe physical layer initial reset request signal, assigning a preset non-zero count value to the PCIe physical layer counter;

[0064] When the count value of the PCIe controller counter is not zero, a PCIe controller target reset pulse signal is generated, where the PCIe controller target reset pulse signal is used to cause the state machine to jump back to the link connection detection state;

[0065] When the count value of the PCIe physical layer counter is not zero, a PCIe physical layer target reset pulse signal is generated. The PCIe physical layer target reset pulse signal is used to reset each physical layer channel.

[0066] In this embodiment, when the current state is speed recovery and the previous state is balance recovery, two reset request signals are simultaneously generated: a PCIe controller initial reset request signal and a PCIe physical layer initial reset request signal. The PCIe controller initial reset request signal is for the PCIe controller, while the PCIe physical layer initial reset request signal is for the PCIe PHY, or the PCIe physical layer. A PCIe controller is typically integrated into the motherboard chipset or as a standalone chip on an expansion card. It connects the PCIe protocol to other computer system components, such as the CPU and memory. The PCIe PHY, or physical layer, is typically integrated into a chip that accompanies the PCIe controller or exists as a standalone physical layer chip. It directly connects to the electrical connection of the PCIe link and is responsible for converting digital data into electrical signals for transmission over physical media. The PCIe controller and the PCIe physical layer work together to ensure stable and fast data transmission within the PCIe system.

[0067] Reference Figure 3 As shown, this method is controlled by the enable signal. If this method is enabled, the equalization failure reset request enable signal must be enabled. Once enabled, this method continuously checks the current and previous LTSSM states. If both the previous LTSSM state is Recovery.Equalization.EQ0 and the current state is Recovery.Speed, or the previous LTSSM state is Recovery.Equalization.EQ1 and the current state is Recovery.Speed, a valid PCIe controller initial reset request signal and PCIe_PHY initial reset request signal are generated. Otherwise, the PCIe controller initial reset request signal and PCIe_PHY initial reset request signal are invalid.

[0068] Then, two counters are defined: the PCIe controller counter and the PCIe physical layer counter. These counters are used to generate the final PCIe controller reset request signal and the PCIe_PHY reset request signal, respectively. The generation principle is as follows: When the initial reset request signal of the PCIe controller and the initial reset request signal of the PCIe_PHY are valid, a non-zero initial value is assigned to each of the two counters (this initial value affects the final reset request duration and thus controls the reset pulse width). Otherwise, if both initial reset request signals are invalid and the counter count value is not 0, the two counters start to count down.

[0069] The count values ​​of the two counters are judged. When the count values ​​of the two counters are not equal to 0, a valid PCIe controller reset pulse signal and PCIe_PHY reset pulse signal are generated respectively. Otherwise, when the two counters are decremented to 0, the two reset pulse signals become invalid. In this way, the initial value of the counter can be set according to the needs, and a reset request signal with configurable pulse width is realized. According to the reset request signal, a reset pulse signal with configurable pulse width can be generated. For the timing diagram of the above process, see Figure 4 and Figure 5 , Figure 4 This is the timing diagram of rebuilding the chain after recovery.eq0 fails. Figure 5 This is the timing diagram for reestablishing the link after recovery.eq1 fails. ltssm_state is the current state of the LTSSM, ltssm_state_d is the previous state of the LTSSM, ini_reset_req_phy is the initial reset request signal for the PCIe_PHY, ini_reset_req_ctrl is the initial reset request signal for the PCIe controller, cnt_phy is the PCIe controller counter used to generate the final PCIe_PHY reset pulse signal, cnt_ctrl is the PCIe physical layer counter used to generate the final PCIe controller reset pulse signal, final_reset_req_phy is the final PCIe_PHY target reset pulse signal, and final_reset_req_ctrl is the final PCIe controller target reset pulse signal.

[0070] When the final PCIe controller target reset pulse signal is valid, a valid PCIe controller reset pulse signal is generated, causing the state machine to jump back to the Detect.Quiet state after reset. When the PCIe_PHY reset request pulse signal is valid, a valid PCIe_PHY reset pulse signal is generated, which in turn resets each PCIe_PHY lane. This allows the link to be reestablished from the Detect state after a balancing failure.

[0071] In this embodiment, operations are performed directly at the physical layer, and link re-establishment and balancing are directly controlled according to the status of the LTSSM. No software intervention is required to detect the link status and configure related registers. When handling balancing failure scenarios, it is faster and more efficient than methods that require software intervention.

[0072] In some optional embodiments, the state machine automatically transitions from the balance recovery state to the speed recovery state in the event of a link balancing failure. The automatic transition from the balance recovery state to the speed recovery state in the event of a link balancing failure can be configured before determining the current state of the state machine and the previous state of the current state.

[0073] If balancing fails during link establishment, the system enters the Recovery.Speed ​​state. Based on these state transition characteristics, the success of balancing can be determined by examining the state transition sequence. If balancing succeeds, no action is taken. If balancing fails, a reset request signal is generated for a certain period of time. After detecting the reset request signal, a reset pulse signal is generated to reset the LTSSM and related modules. After the LTSSM returns to the Detect state, link establishment is restarted, achieving rebalancing and increasing the probability of balancing success.

[0074] In some optional implementations, the balancing recovery state includes multiple balancing sub-stages. When balancing is successful in one of the balancing sub-stages, the state machine directly jumps to the next balancing sub-stage.

[0075] In some optional implementations, when the balancing sub-stage is the last balancing sub-stage, the state machine jumps to the next preset state.

[0076] As shown above, balancing can include different stages. If balancing fails during link establishment, failure can be classified as either EQ0 or EQ1, depending on the time of failure. If EQ0 fails, the process does not enter EQ1 but instead enters the Recovery.Speed ​​state. If EQ1 fails, the process does not enter EQ2 but also enters the Recovery.Speed ​​state, and so on. This differs from the state transition sequence of the traditional LTSSM state machine when balancing succeeds. This state transition sequence allows the success of balancing to be determined by evaluating the state transition sequence. If balancing succeeds, no action is taken and the process proceeds to the next state. If balancing fails, a reset request is generated for a certain period of time. Upon detecting the reset request, a reset pulse signal is generated, resetting the LTSSM and related modules. After the LTSSM returns to the Detect state, link establishment is restarted, achieving rebalancing and increasing the probability of successful balancing.

[0077] This method leverages the low probability of balancing failure, allowing successful balancing after multiple attempts. Compared to related technologies, this method controls link reestablishment without sending hardware information to the CPU or requiring the CPU to configure registers based on hardware status to control state machine transitions. Instead, it directly determines whether balancing is successful and whether a reset signal is needed based on state machine transitions, thereby achieving rebalancing after balancing failures. Without requiring CPU scheduling, this method consumes no CPU and memory resources, minimizing the impact on overall system performance.

[0078] This embodiment also provides a device for reestablishing a link after a PCIe link equalization failure. This device is used to implement the above-mentioned embodiments and preferred implementations, and details already described will not be repeated. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0079] This embodiment provides a device for reconstructing a link after a PCIe link equalization failure. Figure 6 As shown, the device includes:

[0080] Determination module 201, used to determine the current state of the state machine and the previous state of the current state;

[0081] The request generating module 202 is configured to generate an initial reset request signal when the current state is the speed recovery state and the previous state is the balance recovery state;

[0082] The counting module 203 is configured to assign a preset non-zero count value to a predefined counter and start counting down after generating an initial reset request signal;

[0083] The reset generation module 204 is used to generate a target reset pulse signal when the count value is not zero. The target reset pulse signal is used to make the state machine jump to the reset state.

[0084] The device for reconstructing a link after a PCIe link equalization failure in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0085] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0086] The embodiment of the present invention also provides a computer device having the above Figure 6 FIG. 1 shows a device that rebuilds a PCIe link after link equalization fails.

[0087] See also Figure 7 , Figure 7 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 7 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0088] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0089] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0090] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0091] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0092] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0093] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0094] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0095] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for reconstructing a PCIe link after link equalization failure, characterized in that: The jump sequence of the state machine for a successful speed increase and balancing is: link working state, lock recovery state, configuration recovery state, speed recovery state, balance recovery state, lock recovery state, configuration recovery state, idle recovery state, link working state; the method includes: Determine a current state of a state machine and a previous state of the current state; generate an initial reset request signal when the current state is a speed recovery state and the previous state is a balance recovery state; wherein the state machine automatically jumps from the balance recovery state to the speed recovery state when link balancing fails; After the initial reset request signal is generated, a predefined counter is assigned a preset non-zero count value and starts to count down; When the count value is not zero, a target reset pulse signal is generated, wherein the target reset pulse signal is used to cause the state machine to jump to a reset state.

2. The method according to claim 1, characterized in that The preset non-zero count value is set according to the reset pulse width, and when the count value is decremented to zero, the target reset pulse signal is invalid.

3. The method according to claim 1, characterized in that The initial reset request signal includes: a PCIe controller initial reset request signal and a PCIe physical layer initial reset request signal; the counter includes: a PCIe controller counter and a PCIe physical layer counter; the target reset pulse signal includes: a PCIe controller target reset pulse signal and a PCIe physical layer target reset pulse signal; After generating the initial reset request signal, assigning a preset non-zero count value to a predefined counter includes: After generating the PCIe controller initial reset request signal, assigning the PCIe controller counter the preset non-zero count value; After generating the PCIe physical layer initial reset request signal, assigning the PCIe physical layer counter the preset non-zero count value; generating a PCIe controller target reset pulse signal when the count value of the PCIe controller counter is not zero, wherein the PCIe controller target reset pulse signal is used to cause the state machine to jump back to the detection link connection state; When the count value of the PCIe physical layer counter is not zero, the PCIe physical layer target reset pulse signal is generated, and the PCIe physical layer target reset pulse signal is used to reset each physical layer channel.

4. The method according to claim 1, wherein The balance recovery state includes multiple balance sub-stages. When the balance in one of the balance sub-stages is successful, the state machine directly jumps to the next balance sub-stage.

5. The method according to claim 4, characterized in that In the case that the balancing sub-stage is the last balancing sub-stage, the state machine jumps to the next preset state.

6. A device for reconstructing a PCIe link after a PCIe link equalization failure, characterized in that: The device comprises: A determination module is used to determine the current state of the state machine and the previous state of the current state; wherein the jump sequence of the state machine for a successful speed increase and balancing is: link working state, lock recovery state, configuration recovery state, speed recovery state, balance recovery state, lock recovery state, configuration recovery state, idle recovery state, link working state; A request generation module, configured to generate an initial reset request signal when the current state is a speed recovery state and the previous state is a balance recovery state; wherein the state machine automatically jumps from the balance recovery state to the speed recovery state when link balancing fails; a counting module, configured to assign a preset non-zero count value to a predefined counter and start self-counting after generating the initial reset request signal; The reset generation module is used to generate a target reset pulse signal when the count value is not zero, and the target reset pulse signal is used to make the state machine jump to the reset state.

7. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method for reconstructing a chain after a PCIe link equalization failure as described in any one of claims 1 to 5 by executing the computer instructions.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the method for reconstructing a link after a PCIe link equalization failure according to any one of claims 1 to 5.

9. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute the method for reconstructing a link after a PCIe link equalization failure according to any one of claims 1 to 5.

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