Synchronous channel switching method in large-scale matrix switch based on asynchronous bus

Abstract

The invention relates to a channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus, and the method comprises the steps: adding a NOR gate in a control circuit of a matrix board card, and constructing an RS422 bus and SPI hardware bus circuit containing synchronous switching control enabling; the matrix device sends I / O data to the matrix board card through the RS422 bus, and the matrix board card receives the I / O data; and the matrix equipment sends a'switching preparation ' / 'synchronous switching' instruction through the RS422 bus, and the matrix board card opens the synchronous switching control enabling or closes the synchronous switching control enabling. By adding special logic control and utilizing rising edge of a data start bit of a serial RS422 bus and synchronous switching control to enable cooperative control, switch synchronous switching of a plurality of matrix board cards under a plurality of non-synchronous microprocessors is realized, the routing switching time of a large-scale matrix is improved to an ns level from a us level, and the routing switching efficiency of the large-scale matrix is improved. When a large-scale matrix switch carries out channel routing switching, signal receiving and demodulation are not affected, and the channel is lossless and non-inductive.

Description

Technical Field

[0001] The invention belongs to the technical field of large-scale radio frequency signal branch exchange and synchronous control of microwave switch circuits, and in particular relates to a channel synchronous switching method in a large-scale matrix switch based on an asynchronous bus. Background Art

[0002] Large-scale RF switch matrix is ​​composed of dozens of small and medium-sized matrix boards, and each matrix board includes multiple switches and power division units that can absorb and shut down, which contains a large number of switch circuits. Each switch requires one or more I / O controls. For M×N matrix boards, at least 2*M×N I / O controls are required. If 16×16 boards are used to build the matrix, the number of boards and I / Os is as shown in the following table:

[0003] Serial number Matrix size Number of boards Number of I / Os 1 64×64 12 3072 2 128×128 24 6144 3 256×256 48 9216

[0004] Since the I / O of the microcontroller is limited, the serial-to-parallel chip used in the prior art needs to be expanded. SPI serial control only requires three control lines, namely data DATA, clock CLK and enable EN. After the data is input through the serial data, the enable is flipped and latched at the same time.

[0005] Inside the matrix board, the I / O data is shifted to the memory of all serial-to-parallel chips through serial data DATA and clock CLK, and the enable EN is controlled to be high level. At the same time, the I / O data in the memory is flipped and output to achieve synchronous switching of each switch. For large-scale matrices, multiple matrix boards are required, and their control adopts RS422 bus. The whole machine microprocessor sends the I / O data of all boards to each board through RS422 bus. The board microprocessor sends the I / O data of the board to the serial-to-parallel memory through SPI in turn, but does not flip it immediately. After receiving the synchronous switching instruction sent by the matrix master microprocessor, it controls the enable EN to flip, and realizes the synchronous switching of all switches of the whole machine.

[0006] In the above synchronous switching mode, due to the asynchronous clock of the microprocessor of each board, the timing of receiving the interrupt of the serial port RX and executing the interrupt is different, and the synchronization error is about 5 us ~10 us The complete channel of the plug-in RF matrix involves multiple boards when the routing is changed, and the switching synchronization time error causes signal interruption 5 us ~10 us , which will cause the channel to lose one or more code elements or even lose signal lock when receiving high-speed modulated signals.

[0007] Therefore, how to improve the large-scale RF signal branch exchange and the synchronous switching method of the microwave switch circuit in the existing technology, realize the synchronous switching of multiple matrix boards under multiple asynchronous microprocessors, and increase the routing switching time of the large-scale matrix from the us level to the ns level, thereby realizing the routing switching of the established channels and making the signal reception and demodulation channels lossless and insensitive, is a technical problem that needs to be solved urgently. Summary of the invention

[0008] The purpose of the present invention is to provide a channel synchronous switching method based on an asynchronous bus in a large-scale matrix switch, to improve the large-scale RF signal branch exchange and the synchronous switching method of the microwave switch circuit in the prior art, to realize the synchronous switching of multiple matrix boards under multiple asynchronous microprocessors, to improve the routing switching time of the large-scale matrix from the us level to the ns level, thereby realizing the routing switching of the established channels, and the signal receiving and demodulating channels are lossless and insensitive.

[0009] In order to solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0010] A method for synchronously switching channels in a large-scale matrix switch based on an asynchronous bus comprises the following steps:

[0011] S1: Add an NOR gate logic control unit to the control circuit of the matrix board to build an RS422 bus and SPI hardware bus circuit including synchronous switching control enable;

[0012] S2: The matrix device sends I / O data to the matrix board through the RS422 bus. The matrix board receives the I / O data and forwards it to the serial-to-parallel chip for storage through SPI.

[0013] S3: The matrix device sends a "switching preparation" command through the RS422 bus. After receiving the command, the matrix board turns on the synchronous switching control enable switch;

[0014] S4: The matrix device sends a "synchronous switching" command through the RS422 bus, and uses the rising edge of the start bit of the serial RS422 bus data to achieve synchronous flipping of the I / Os of all HC595 chips on all boards. After receiving the command, the matrix board turns off the synchronous switching control enable switch.

[0015] Preferably, the control circuit of the matrix board with an added NOR gate in step S1 includes a board microprocessor, a serial-to-parallel chip, a serial port chip and an RS422 bus, wherein a plurality of the serial-to-parallel chips are provided, the board microprocessor is connected to the plurality of serial-to-parallel chips, the board microprocessor is also connected to the serial port chip, the NOR gate is respectively connected to the board microprocessor, the serial-to-parallel chip and the serial port chip, the RS422 bus is connected to the serial port chip, and the model of the serial-to-parallel chip is HC595.

[0016] Preferably, in the control circuit of the matrix board, when EN'=1, the RX generated by the RS422 bus data changes, and EN is always 0, which will not allow the storage data of the HC595 chip to be flipped to the output; when EN'=0, the RX generated by the RS422 bus data, as long as RX=0, EN=1, the storage data of the serial-to-parallel chip HC595 chip is flipped to the output.

[0017] Preferably, when the matrix is ​​a large-scale matrix, its plug-in matrix bus control circuit includes a matrix board, a serial port chip, a whole machine microprocessor, and a network port chip. The network port chip is connected to the whole machine microprocessor, and the whole machine microprocessor is connected to the serial port chip. There are several matrix boards, and the serial port chips are respectively connected to several matrix boards through RS422 buses.

[0018] Preferably, the specific process of step S2 is as follows:

[0019] S21: When the matrix needs to switch routes, the matrix board that needs to change I / O is screened and searched, and I / O control data is sent to the matrix board that needs to change I / O in turn through the RS422 bus, and it is determined whether the I / O control data is sent to all matrix boards. If so, step S22 is executed, if not, the I / O control data is continued to be sent to the remaining matrix boards that need to change I / O in turn through the RS422 bus;

[0020] S22: Send a "switch preparation" command to all matrix boards, and after a specified delay, send a "synchronous switch" command to all matrix boards again.

[0021] Preferably, step S3 includes the following specific process:

[0022] S31: Start the matrix board program, set enable EN'=1, cyclically receive the command of RS422 bus, judge the command type received by the matrix board, if the command type received by the matrix board is "I / O data" command, execute step S32, if the command type received by the matrix board is "switch preparation" command, execute step S33; if the command type received by the matrix board is "synchronous switching" command, execute step S34;

[0023] S32: Send I / O data to the serial-to-parallel conversion chip via SPI;

[0024] S33: Set enable EN' to 0;

[0025] S34: Set enable EN' to 1.

[0026] Preferably, during the period when the enable EN' of the matrix card is 0, when the first 0 of RX appears, that is, the start bit in the serial protocol, the I / O data stored in the serial-to-parallel chip HC595 is immediately flipped and output, and when the I / O data does not change, the switch does not switch, and the signal is not interrupted;

[0027] When the I / O data changes and the switch is switched, all switches on all matrix boards that need to be switched will be switched synchronously, and the channel signal will gradually disappear and then gradually reappear. The time of this process depends on the switching time of the RF switch chip, which is 50 to 150ns.

[0028] Preferably, the NOR gate logic control unit is a multi-input NOR gate logic control unit, including multiple input terminals and one output terminal.

[0029] Preferably, when all inputs of the multiple input terminals are at a low level, the output terminal outputs a high level 1; when the input of one of the multiple input terminals is at a high level, the output terminal outputs a low level 0.

[0030] The beneficial effects of the present invention include:

[0031] The invention provides a channel synchronous switching method based on an asynchronous bus in a large-scale matrix switch. Firstly, an NOR gate logic control unit is added to the control circuit of a matrix board to construct an RS422 bus and an SPI hardware bus circuit containing synchronous switching control enable; a matrix device sends I / O data to the matrix board through the RS422 bus, the matrix board receives the I / O data and forwards the data to a serial-to-parallel chip through the SPI for storage; the matrix device sends a "switching preparation" instruction through the RS422 bus, and the matrix board turns on the synchronous switching control enable switch after receiving the command; the matrix device sends a "synchronous switching" instruction through the RS422 bus, and uses the rising edge of the start bit of the serial RS422 bus data to realize the synchronous flipping of the I / Os of all HC595 chips of all boards, and the matrix board turns off the synchronous switching control enable switch after receiving the command.

[0032] By adding special logic control, using the rising edge of the start bit of the serial RS422 bus data and the synchronous switching instruction to enable coordinated control, the synchronous switching of multiple matrix boards under multiple asynchronous microprocessors can be achieved, and the routing switching time of large-scale matrices can be improved from the us level to the ns level, thereby realizing the routing switching of established channels, and the signal reception and demodulation channels are lossless and insensitive. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 The present invention is a schematic diagram of the internal I / O expansion control circuit of the matrix board in the prior art.

[0034] Figure 2 The present invention is a schematic diagram of the composition of the card matrix bus control circuit in the prior art.

[0035] Figure 3 The present invention is a schematic diagram of the internal I / O expansion control circuit of the matrix board card with added NOR gate logic control.

[0036] Figure 4 It is a schematic diagram of the synchronous switching process of the card matrix of the present invention.

[0037] Figure 5 The figure is a schematic diagram of the synchronous switching process of the matrix boards of the present invention. DETAILED DESCRIPTION

[0038] The following is combined with Figure 1 to Figure 5 The present invention is further described in detail:

[0039] Example 1

[0040] A method for synchronously switching channels in a large-scale matrix switch based on an asynchronous bus, characterized in that it comprises the following steps:

[0041] S1: Add an NOR gate logic control unit in the control circuit of the matrix board, that is, add special logic control in the control circuit of the matrix board, build a serial RS422 bus and SPI hardware bus circuit including synchronous switching control enable, and use the rising edge of the start bit of the serial RS422 bus data and the synchronous switching instruction to enable coordinated control;

[0042] S2: When the matrix device needs to switch routes, it screens and searches for the matrix boards that need to change I / O data. The matrix device sends I / O data to all matrix boards in sequence through the RS422 bus. The matrix boards receive the I / O data and forward it to the serial-to-parallel chip for storage through SPI.

[0043] S3: After the I / O data is sent, the matrix device sends a "switching preparation" command through the RS422 bus. After receiving the command, the matrix board turns on the synchronous switching control enable switch;

[0044] S4: The matrix device sends a "synchronous switching" command through the RS422 bus, and uses the rising edge of the start bit of the serial RS422 bus data to achieve synchronous flipping of the I / O of all HC595 chips on all boards, and realize the synchronous switching of multiple matrix boards under multiple asynchronous microprocessors, which increases the routing switching time of large-scale matrices from the us level to the ns level, thereby achieving routing switching of established channels, and signal reception and demodulation channels are lossless and insensitive. After receiving the command, the matrix board turns off the synchronous switching control enable switch.

[0045] Since in the prior art, see Figure 1 , inside the matrix board, through the serial data DATA and the clock CLK, the I / O data is shifted to the memory of all serial-to-parallel chips one by one, and the enable EN is controlled to be high level, and the I / O data in the memory is flipped and output at the same time, so as to realize the synchronous switching of each switch. The whole machine microprocessor sends the I / O data of all boards to each board through the RS422 bus. The board microprocessor sends the I / O data of the board to the serial-to-parallel memory through SPI in sequence, but does not flip it immediately. After receiving the synchronous switching instruction sent by the matrix master microprocessor, the enable EN is controlled to flip, so as to realize the synchronous switching of all switches of the whole machine. This synchronous switching mode has a synchronization error of about 5us to 10us because the clocks of the microprocessors of each board are not synchronized, and the timing of receiving the interrupt of the serial port RX and executing the interrupt is different. When the routing of the complete channel of the plug-in RF matrix is ​​changed, multiple boards are involved. The switching synchronization time error causes the signal to be interrupted by 5us to 10us, which will cause the channel to lose one or more code elements when receiving high-speed modulation signals, or even signal lock. For example, when the signal modulation rate is R(Bd), the symbol time T(s) is:

[0046]

[0047] The symbol time of different modulation rates is as follows:

[0048] Modulation rate (MBd) 0.1 1 10 20 Symbol time T(ns) 10000 1000 100 50 Symbol time T(us) 10 1 0.1 0.05

[0049] The number of lost symbols due to signal interruption time at different modulation rates is shown in the following table:

[0050]

[0051] It can be seen from the above table that for signals with a rate above 1MBd, hundreds of code elements are lost, which may even cause demodulation lock loss.

[0052] Therefore, in this embodiment, by adding a special NOR gate logic control in the control circuit of the matrix board, the rising edge of the start bit of the serial RS422 bus data and the synchronous switching instruction are used to enable coordinated control, so as to realize the synchronous switching of the switches of multiple matrix boards under multiple asynchronous microprocessors, and improve the routing switching time of large-scale matrices from the us level to the ns level. When the routing switching of large-scale matrices is realized, the signal interruption time is about 50ns to 150ns, and the specific time depends on the switching time of the RF switch chip, which is improved by about 100 times, so as to realize the routing switching for receiving and demodulating the modulation signal below 10M baud with 0 code element loss, and realize the routing switching of the established channel, and the signal receiving and demodulating channel is lossless and insensitive.

[0053] The NOR gate logic control unit is a multi-input NOR gate logic control unit, including multiple input terminals and one output terminal. When all inputs of the multiple input terminals are at a low level, the output terminal outputs a high level 1; when the input of one of the multiple input terminals is at a high level, the output terminal outputs a low level 0.

[0054] Example 2

[0055] See also Figure 3 On the basis of Example 1, the control circuit of the matrix board in step S1 is increased by a logic control of a matrix board, which includes a board microprocessor, a serial-to-parallel chip, a serial port chip and an RS422 bus. The serial-to-parallel chip is provided in a plurality and the model of the serial-to-parallel chip is HC595. The board microprocessor is connected to the plurality of serial-to-parallel chips through serial data DATA and clock CLK, the signal input end of the board microprocessor is connected to the signal output end of the serial port chip, the logic control unit of the NOR gate is respectively connected to the board microprocessor, the serial-to-parallel chip and the serial port chip, and the RS422 bus is connected to the serial port chip. Inside the matrix board, the I / O data is shifted successively to the memory of all serial-to-parallel chips through the serial data DATA and the clock CLK, and the enable EN is controlled to be high level. At the same time, the I / O data in the memory is flipped and output. Special logic control is added to the control circuit of the matrix board. The rising edge of the start bit of the serial RS422 bus data and the synchronous switching instruction are used to enable coordinated control, so as to realize the synchronous switching of the switches of multiple matrix boards under multiple asynchronous microprocessors and realize the synchronous switching of each switch.

[0056] In the control circuit of the matrix board, when EN'=1, the RX generated by the RS422 bus data changes, and EN is always 0, which will not allow the storage data of the HC595 chip to be flipped to the output; when EN'=0, the RX generated by the RS422 bus data, as long as RX=0, EN=1, the storage data of the serial-to-parallel chip HC595 chip is flipped to the output.

[0057] The logical relationship of the control circuit of the matrix board is shown in the following table:

[0058] Serial number EN' RX EN 1 1 x 0 2 0 1 0 3 0 0 1

[0059] It can be seen from the above table that when EN'=1, no matter RX is 0 or 1, the EN value is 0. When EN'=0, EN= / RX. The function realized by the control circuit of the matrix board is: when EN'=1, the RX generated by the RS422 bus data changes, EN is always 0, and the storage data of the HC595 chip will not be flipped to the output; when EN'=0, the RX generated by the RS422 bus data, as long as RX=0, then EN=1, the storage data of the HC595 chip is flipped to the output.

[0060] When the matrix is ​​large, see Figure 2 The card matrix bus control circuit includes a matrix board, a serial port chip, a whole machine microprocessor, and a network port chip. The network port chip is connected to the whole machine microprocessor, and the whole machine microprocessor is connected to the serial port chip. There are several matrix boards, and the serial port chips are connected to several matrix boards through RS422 buses.

[0061] Example 3

[0062] See also Figure 4 Based on Example 1, the specific process of step S2 is as follows:

[0063] S21: When the matrix needs to switch routes, the matrix board that needs to change I / O is screened and searched, and I / O control data is sent to the matrix board that needs to change I / O in turn through the RS422 bus, and it is determined whether the I / O control data is sent to all matrix boards. If so, step S22 is executed, if not, the I / O control data is continued to be sent to the remaining matrix boards that need to change I / O in turn through the RS422 bus;

[0064] S22: Send a "switch preparation" instruction to all matrix boards, and then, after a specified delay time, further send a "synchronous switching" preparation instruction to all matrix boards.

[0065] Example 4

[0066] See also Figure 5Based on Example 1, step S3 includes the following specific process:

[0067] S31: Start the matrix board program, set enable EN'=1, cyclically receive the command of RS422 bus, judge the command type received by the matrix board, if the command type received by the matrix board is "I / O data" command, execute step S32, if the command type received by the matrix board is "switch preparation" command, execute step S33; if the command type received by the matrix board is "synchronous switching" command, execute step S34;

[0068] S32: Send I / O data to the serial-to-parallel conversion chip via SPI;

[0069] S33: Set enable EN' to 0;

[0070] S34: Set enable EN' to 1.

[0071] In the above scheme, after the matrix board program is started, the enable EN' is set to 1, the bus instructions are received cyclically, and the type of instruction received by the board is determined. If it is an "I / O data" instruction, the I / O data is sent to the serial-to-parallel conversion chip through SPI. If it is a "switch preparation" instruction, the enable EN' is set to 0. If it is a "synchronous switching" instruction, the enable EN' is set to 1.

[0072] During the period when the matrix card enable EN' is 0, when the first 0 of RX appears, that is, the start bit in the serial protocol, the I / O data stored in the serial-to-parallel chip HC595 is immediately flipped and output. When the I / O data does not change, the switch does not switch, and the signal is not interrupted. When the I / O data changes, the switch switches, all the switches that need to be switched on all matrix cards act synchronously, and the channel signal gradually disappears and then gradually reappears. The time of this process depends on the switching time of the RF switch chip, which is 50 to 150ns.

[0073] In this embodiment, the number of lost symbols of signals with different modulation rates caused by signal interruption time is as follows:

[0074]

[0075] From the above table, it can be seen that for signals with a rate below 1MBd, less than 1 code element is lost, and for signals with a rate below 20MBd, only 3 code elements are lost at most, and the signal will not be unlocked. The lost code elements can also be restored through the signal error correction mechanism, thus solving the technical problem in the prior art that for signals with a rate above 1MBd, hundreds of code elements are lost, and even demodulation is unlocked. By adding special logic control, using the rising edge of the start bit of the serial RS422 bus data and the synchronous switching instruction to enable collaborative control, the switch synchronization of multiple matrix boards under multiple asynchronous microprocessors is realized, and the routing switching time of large-scale matrices is improved from the us level to the ns level, thereby realizing the routing switching of the established channels, and the signal receiving and demodulation channels are lossless and insensitive.

[0076] In summary, the channel synchronous switching method based on asynchronous bus in large-scale matrix switch provided by the present invention firstly adds an NOR gate logic control unit in the control circuit of the matrix board, constructs the RS422 bus and SPI hardware bus circuit including synchronous switching control enable; the matrix device sends I / O data to the matrix board through the RS422 bus, the matrix board receives the I / O data, and forwards it to the serial-to-parallel chip through SPI for storage; the matrix device sends a synchronous switching preparation instruction through the RS422 bus, and the matrix board turns on the synchronous switching control enable switch; the matrix device sends a synchronous switching instruction through the RS422 bus, and the matrix board turns off the synchronous switching control enable switch. By adding special logic control, the rising edge of the start bit of the serial RS422 bus data and the synchronous switching instruction enable collaborative control are used to realize the synchronous switching of the switches of multiple matrix boards under multiple asynchronous microprocessors, and the routing switching time of the large-scale matrix is ​​increased from the us level to the ns level, thereby realizing the routing switching of the established channels, and the signal receiving and demodulating channels are lossless and insensitive.

[0077] The above-mentioned embodiments only express the specific implementation method of the present application, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the protection scope of the present application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the technical solution concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A method for synchronous channel switching in a large-scale matrix switch based on an asynchronous bus, characterized in that: The following steps are involved: S1: Add an NOR gate logic control unit to the control circuit of the matrix board to build an RS422 bus and SPI hardware bus circuit including synchronous switching control enable; S2: When the matrix device needs routing switching, the matrix device sends I / O data to the matrix board through the RS422 bus. The matrix board receives the I / O data and forwards it to the serial-to-parallel chip for storage through SPI. S3: The matrix device sends a "switching preparation" command through the RS422 bus. The matrix board receives the command and turns on the synchronous switching control enable switch. S4: The matrix device sends a "synchronous switching" command through the RS422 bus, and uses the rising edge of the start bit of the serial RS422 bus data to achieve synchronous flipping of the I / Os of all 595 chips on all boards. The matrix board receives the command and turns off the synchronous switching control enable switch.

2. A method for synchronous channel switching in a large-scale matrix switch based on an asynchronous bus according to claim 1, characterized in that: The control circuit of the matrix board with an added NOR gate in step S1 includes a board microprocessor, a serial-to-parallel chip, a serial port chip and an RS422 bus. The serial-to-parallel chips are provided in a plurality, the board microprocessor is connected to the plurality of serial-to-parallel chips, the board microprocessor is also connected to the serial port chip, the NOR gate is respectively connected to the board microprocessor, the serial-to-parallel chip and the serial port chip, the RS422 bus is connected to the serial port chip, and the model of the serial-to-parallel chip is HC595.

3. A method for synchronous channel switching in a large-scale matrix switch based on an asynchronous bus according to claim 2, characterized in that: In the control circuit of the matrix board, when EN'=1, the RX generated by the RS422 bus data changes, and EN is always 0, which will not allow the storage data of the HC595 chip to be flipped to the output; when EN'=0, the RX generated by the RS422 bus data, as long as RX=0, EN=1, the storage data of the serial-to-parallel chip HC595 chip is flipped to the output.

4. The method for synchronous channel switching in a large-scale matrix switch based on an asynchronous bus according to claim 2, characterized in that: When the matrix is ​​a large-scale matrix, its card-insertion matrix bus control circuit includes a matrix board, a serial port chip, a whole machine microprocessor, and a network port chip. The network port chip is connected to the whole machine microprocessor, and the whole machine microprocessor is connected to the serial port chip. There are several matrix boards, and the serial port chips are respectively connected to several matrix boards through RS422 buses.

5. The method for synchronous channel switching in a large-scale matrix switch based on an asynchronous bus according to claim 1, characterized in that: The specific process of step S2 is as follows: S21: When the matrix needs to switch routes, the matrix board that needs to change I / O is screened and searched, and I / O control data is sent to the matrix board that needs to change I / O in turn through the RS422 bus, and it is determined whether the I / O control data is sent to all matrix boards. If so, step S22 is executed, if not, the I / O control data is continued to be sent to the remaining matrix boards that need to change I / O in turn through the RS422 bus; S22: Send a "switch preparation" command to all matrix boards, and after a specified delay, send a "synchronous switch" command to all matrix boards again. S23: forwarding to the serial-to-parallel chip via SPI for storage.

6. The method for synchronous channel switching in a large-scale matrix switch based on an asynchronous bus according to claim 5, characterized in that: Step S3 includes the following specific processes: S31: Start the matrix board program, set enable EN'=1, cyclically receive the command of RS422 bus, determine the command type received by the matrix board, if the command type received by the matrix board is "I / O data" command, execute step S32, if the command type received by the matrix board is "switch preparation" command, execute step S33; if the command type received by the matrix board is "synchronous switching" command, execute step S34; S32: Send I / O data to the serial-to-parallel conversion chip via SPI; S33: Set enable EN' to 0; S34: Set enable EN' to 1.

7. The method for synchronous channel switching in a large-scale matrix switch based on an asynchronous bus according to claim 1, characterized in that: During the period when the enable EN' of the matrix card is 0, when the first 0 of RX appears, that is, the start bit in the serial protocol, the I / O data stored in the serial-to-parallel chip HC595 is immediately flipped and output. When the I / O data does not change, the switch does not switch, and the signal is not interrupted; When the I / O data changes and the switch is switched, all switches on all matrix boards that need to be switched will be switched synchronously, and the channel signal will gradually disappear and then gradually reappear. The time of this process depends on the switching time of the RF switch chip, which is 50 to 150ns.

8. The method for synchronous channel switching in a large-scale matrix switch based on an asynchronous bus according to claim 1, characterized in that: The NOR gate logic control unit is a multi-input NOR gate logic control unit, including multiple input terminals and one output terminal.

9. The method for synchronous channel switching in a large-scale matrix switch based on an asynchronous bus according to claim 8, characterized in that: When all inputs of the multiple input terminals are at a low level, the output terminal outputs a high level 1; when the input of one of the multiple input terminals is at a high level, the output terminal outputs a low level 0.

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