Network card management method and device, storage medium and program product

Abstract

The embodiment of the invention provides a network card management method and device, a storage medium and a program product, and relates to the field of computers.The method comprises the steps that an arbitration chip of a serial communication bus I2C is configured, and a logic chip is configured; sending the first management information and the second management information to a target network card according to an arbitration chip sorting sequence; under the condition that the logic chip on the second adapter plate receives a first power-on management signal sent by a complex programmable logic device (CPLD) of the first mainboard or a second power-on management signal sent by a CPLD of the second mainboard, the first power-on management signal or the second power-on management signal is sent to a target network card; under the condition that the logic chip receives a first power-off management signal sent by the CPLD of the first mainboard and a second power-off management signal sent by the CPLD of the second mainboard, sending a target power-off management signal to a target network card; by adopting the scheme, the problem that the network card cannot be effectively managed is solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the computer field, and specifically to a network card management method and device, a storage medium, and a program product. Background Art

[0002] A network card is a device inside or outside a computer that connects the computer to a local area network (LAN) or wide area network (WAN) and enables data transmission via Ethernet or wireless network connections. Network card management is very important because it directly affects the computer's network connection and communication performance. Network connection is the key part of data exchange between a computer and an external network, and a network card is a hardware device that implements this connection.

[0003] At present, the management of network cards is usually carried out by using the embedded manager (Baseboard Management Controller, BMC) on the motherboard of the device where the network card is located to transmit network card information (such as temperature, operating status, etc.) to the network card through the serial communication bus I2C, so as to achieve control over the network card, and use the complex programmable logic device (Complex Programmable Logic Device, CPLD) on the motherboard to manage the power on and off of the network card through the power on and off signal transmission channels.

[0004] However, when adopting the network card management method provided in the above-mentioned related technology, when there are multiple mainboards in the device, multiple mainboards need to monitor the network card through I2C, and need to manage the power on and off of the network card through the power on and off signal transmission channels, which may cause conflicts between the management of the network card by multiple mainboards, and may lead to technical problems such as the inability to effectively manage the network card. Summary of the invention

[0005] The embodiments of the present application provide a network card management method and device, a storage medium, and a program product to at least solve the technical problem of being unable to effectively manage the network card.

[0006] According to an embodiment of the present application, a network card management method is provided, comprising: configuring an arbitration chip of a serial communication bus I2C on a first adapter board, and configuring a logic chip on a second adapter board; when the arbitration chip on the first adapter board receives first management information sent by an embedded manager BMC on a first mainboard and second management information sent by a BMC on a second mainboard through I2C, the arbitration chip is used to sort the first management information and the second management information, and the first management information and the second management information are sent to a target network card in the sorting order between the first management information and the second management information, wherein, when the target network card receives the first management information, the management operation matching the first management information is executed, and when the target network card receives the second management information, the management operation matching the second management information is executed. The matched management operation; when the logic chip on the second adapter board receives the first power-on management signal sent by the complex programmable logic device CPLD of the first main board or the second power-on management signal sent by the CPLD of the second main board through the up and down power signal transmission channel, the first power-on management signal or the second power-on management signal is sent to the target network card by using the logic chip, wherein the target network card will perform a power-on operation when receiving the first power-on management signal or the second power-on management signal; when the logic chip receives the first power-off management signal sent by the CPLD of the first main board and the second power-off management signal sent by the CPLD of the second main board through the up and down power signal transmission channel, the target power-off management signal is sent to the target network card by using the logic chip, wherein the target network card will perform a power-off operation when receiving the target power-off management signal.

[0007] According to another embodiment of the present application, a network card management device is provided, including: a configuration unit, configured on a first adapter board, for configuring an arbitration chip of a serial communication bus I2C, and configuring a logic chip on a second adapter board; a first sending unit, used to, when the arbitration chip on the first adapter board receives first management information sent by an embedded manager BMC on a first mainboard and second management information sent by a BMC on a second mainboard through I2C, use the arbitration chip to sort the first management information and the second management information, and send the first management information and the second management information to a target network card in the sorting order between the first management information and the second management information, wherein, when the target network card receives the first management information, it will execute a management operation matching the first management information, and when the target network card receives the second management information, it will execute an operation matching the second management information. A management operation matched by the management information; a second sending unit, used for, when the logic chip on the second adapter board receives a first power-on management signal sent by the complex programmable logic device CPLD of the first main board or a second power-on management signal sent by the CPLD of the second main board through the up and down power signal transmission channel, using the logic chip to send the first power-on management signal or the second power-on management signal to the target network card, wherein the target network card will perform a power-on operation when receiving the first power-on management signal or the second power-on management signal; when the logic chip receives a first power-off management signal sent by the CPLD of the first main board and a second power-off management signal sent by the CPLD of the second main board through the up and down power signal transmission channel, using the logic chip to send the target power-off management signal to the target network card, wherein the target network card will perform a power-off operation when receiving the target power-off management signal.

[0008] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0009] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0010] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0011] Through the embodiment provided by the present application, an arbitration chip of the serial communication bus I2C is configured on the first adapter board, and a logic chip is configured on the second adapter board; when the arbitration chip on the first adapter board receives the first management information sent by the embedded manager BMC on the first mainboard and the second management information sent by the BMC on the second mainboard through I2C, the arbitration chip is used to sort the first management information and the second management information, and the first management information and the second management information are sent to the target network card according to the sorting order between the first management information and the second management information, wherein, when the target network card receives the first management information, it will execute the management operation matching the first management information, and when the target network card receives the second management information, it will execute the management operation matching the second management information. Management operations matched by the information; when the logic chip on the second adapter board receives the first power-on signal sent by the complex programmable logic device CPLD of the first main board or the second power-on signal sent by the CPLD of the second main board through the up and down power signal transmission channels, the first power-on signal or the second power-on signal is sent to the target network card by using the logic chip, wherein the target network card will perform a power-on operation when receiving the first power-on signal or the second power-on signal; when the logic chip receives the first power-off signal sent by the CPLD of the first main board and the second power-off signal sent by the CPLD of the second main board through the up and down power signal transmission channels, the target power-off signal is sent to the target network card by using the logic chip, wherein the target network card will perform a power-off operation when receiving the target power-off signal. In other words, by using the embodiment of the present application, on the one hand, a first adapter board is configured between the mainboard and the network card, and an I2C arbitration chip is configured on the first adapter board, so that the I2C arbitration chip is used to coordinate the management information sent by the first mainboard and the second mainboard, so that the management information sent by the first mainboard and the second mainboard can be transmitted to the target network card in an orderly manner; on the other hand, a second adapter board is configured between the mainboard and the network card, and a logic chip is configured on the second adapter board, so that the logic chip is used to determine whether to control the target network card to perform power-on and power-off operations according to the power-on and power-off signals sent by the first mainboard and the second mainboard and the predetermined processing logic, thereby avoiding the problem of conflicts between power-on and power-off signals sent by different mainboards. In other words, by using the embodiment of the present application, the above two aspects avoid the conflict between the management of the network card by multiple mainboards, solve the technical problem that the network card management method provided by the related technology cannot effectively manage the network card, and achieve the technical effect of improving the management effect of the network card. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a flow chart of a method for managing a network card according to an embodiment of the present application;

[0013] Figure 2is a flow chart of a method for managing a network card according to an embodiment of the present application;

[0014] Figure 3 is a flow chart of another network card management method according to an embodiment of the present application;

[0015] Figure 4 is a schematic diagram of a network card management method according to an embodiment of the present application;

[0016] Figure 5 A structural block diagram of a network card management device according to an embodiment of the present application. DETAILED DESCRIPTION

[0017] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0018] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0019] As an optional solution, the specific steps of the above network card management method are as follows: Figure 1 Shown include:

[0020] S102, configuring an arbitration chip of the serial communication bus I2C on the first adapter board, and configuring a logic chip on the second adapter board;

[0021] S104, when the arbitration chip on the first adapter board receives the first management information sent by the embedded manager BMC on the first mainboard and the second management information sent by the BMC on the second mainboard through the I2C, the arbitration chip is used to sort the first management information and the second management information, and the first management information and the second management information are sent to the target network card according to the sorting order between the first management information and the second management information, wherein when the target network card receives the first management information, the management operation matching the first management information is executed, and when the target network card receives the second management information, the management operation matching the second management information is executed;

[0022] S106, when the logic chip on the second adapter board receives the first power-on signal sent by the complex programmable logic device CPLD of the first main board or the second power-on signal sent by the CPLD of the second main board through the up and down electrical signal transmission channels, the logic chip is used to send the first power-on signal or the second power-on signal to the target network card, wherein the target network card will perform a power-on operation when receiving the first power-on signal or the second power-on signal; when the logic chip receives the first power-off signal sent by the CPLD of the first main board and the second power-off signal sent by the CPLD of the second main board through the up and down electrical signal transmission channels, the logic chip is used to send the target power-off signal to the target network card, wherein the target network card will perform a power-off operation when receiving the target power-off signal.

[0023] It should be noted that the above network card management method can be applied to, but not limited to, network card management scenarios. The above first adapter board and the above second adapter board can be configured between the target network card and the first mainboard and the second mainboard, but not limited to.

[0024] Optionally, in this embodiment, the above-mentioned I2C can be but not limited to a data path for instructing the BMC to obtain network card information. The BMC requests the target network card's network card information through the I2C, such as the manufacturer of the target network card, the operating time of the target network card, the temperature of the target network card, etc., to realize monitoring and management of the target network card.

[0025] Further, in this embodiment, the above-mentioned up and down electrical signal transmission channel can be but is not limited to being used to transmit up and down electrical signals, wherein the above-mentioned power-up signal is used to control the target network card to start up, and the above-mentioned power-down signal is used to control the target network card to stop running.

[0026] It should be noted that the complex programmable logic device CPLD can realize various digital logic functions, including combinational logic and sequential logic. It can be used to build digital circuits, such as counters, registers, state machines, and microprocessors. The logic chip can be, but is not limited to, CPLD and can also be other chips with similar functions, which is not limited in this embodiment.

[0027] Optionally, the arbitration chip of the above-mentioned serial communication bus I2C can be but not limited to a 9641 chip or other chips with an I2C arbitration function. This is not limited in the present embodiment. The above-mentioned 9641 chip is a dedicated I2C arbitration chip, and the two groups of I2Cs can arbitrate the bus control right by themselves. The motherboard BMC that wins the bus control right first accesses the network card. After completion, when the bus is idle, the other motherboard BMC obtains the bus control right and then accesses the network card I2C device.

[0028] Furthermore, the above logic chip can be but is not limited to being used to indicate a chip that has been pre-written with power-on and power-off logic. Specifically, the power-on signal performs an OR logic, that is, if a mainboard wants to power on the network card, the network card performs the power-on action, and after the power-on is completed, the power-on success signal is returned and transmitted to both mainboards at the same time. Based on this, if a mainboard wants to power on, the smart network card will follow the power-on and realize the function of a normal network card; the power-off signal performs an AND logic, and when the mainboard is shut down, the smart network card will follow the shutdown function only when both mainboards are shut down. This not only ensures that both mainboards can connect and manage the network card function, but also avoids conflicts in network card control caused by different power-on and power-off states between them.

[0029] It should be noted that the above-mentioned use of the arbitration chip to sort the first management information and the second management information, and sending the first management information and the second management information to the target network card according to the sorting order between the first management information and the second management information can be but is not limited to: using the arbitration chip to sort the first management information and the second management information according to the receiving time when the first management information is received and the receiving time when the second management information is received to obtain the sorted first management information and the second management information, wherein the management information with an earlier receiving time in the sorted first management information and the second management information has a higher sorting order; sending the first management information and the second management information to the target network card according to the sorting order between the first management information and the second management information.

[0030] In addition, in addition to determining the order in which the first management information and the second management information are sent to the target network card according to the time when the management information is received, other strategies can also be used to determine the order in which the first management information and the second management information are sent to the target network card, such as the type of management information, the priority of the management information, the priority of the motherboard, etc., among which management information with a higher priority will be sent first, and management information sent by a motherboard with a higher motherboard priority will be sent first.

[0031] It should be noted that, in the present embodiment, before the above-mentioned use of the logic chip to send the first power-on signal or the second power-on signal to the target network card, it may include but is not limited to: when the CPLD of the first mainboard receives a startup instruction for the first mainboard, the first power-on management signal is sent to the logic chip through the up and down power signal transmission channels; when the CPLD of the second mainboard receives a startup instruction for the second mainboard, the second power-on management signal is sent to the logic chip through the up and down power signal transmission channels.

[0032] Optionally, in the present embodiment, in the case where the logic chip receives the first power-off signal sent by the CPLD of the first mainboard and the second power-off signal sent by the CPLD of the second mainboard through the up and down power signal transmission channels, before using the logic chip to send the target power-off signal to the target network card, it may include but is not limited to: when the CPLD of the first mainboard receives a shutdown command for the first mainboard, the first power-off management signal is sent to the logic chip through the up and down power signal transmission channels; when the CPLD of the second mainboard receives a shutdown command for the second mainboard, the second power-off management signal is sent to the logic chip through the up and down power signal transmission channels.

[0033] Through the embodiment provided by the present application, an arbitration chip of the serial communication bus I2C is configured on the first adapter board, and a logic chip is configured on the second adapter board; when the arbitration chip on the first adapter board receives the first management information sent by the embedded manager BMC on the first mainboard and the second management information sent by the BMC on the second mainboard through I2C, the arbitration chip is used to sort the first management information and the second management information, and the first management information and the second management information are sent to the target network card according to the sorting order between the first management information and the second management information, wherein, when the target network card receives the first management information, it will execute the management operation matching the first management information, and when the target network card receives the second management information, it will execute the management operation matching the second management information. Management operations matched by the information; when the logic chip on the second adapter board receives the first power-on signal sent by the complex programmable logic device CPLD of the first main board or the second power-on signal sent by the CPLD of the second main board through the up and down power signal transmission channels, the first power-on signal or the second power-on signal is sent to the target network card by using the logic chip, wherein the target network card will perform a power-on operation when receiving the first power-on signal or the second power-on signal; when the logic chip receives the first power-off signal sent by the CPLD of the first main board and the second power-off signal sent by the CPLD of the second main board through the up and down power signal transmission channels, the target power-off signal is sent to the target network card by using the logic chip, wherein the target network card will perform a power-off operation when receiving the target power-off signal. In other words, by using the embodiment of the present application, on the one hand, a first adapter board is configured between the mainboard and the network card, and an I2C arbitration chip is configured on the first adapter board, so that the I2C arbitration chip is used to coordinate the management information sent by the first mainboard and the second mainboard, so that the management information sent by the first mainboard and the second mainboard can be transmitted to the target network card in an orderly manner; on the other hand, a second adapter board is configured between the mainboard and the network card, and a logic chip is configured on the second adapter board, so that the logic chip is used to determine whether to control the target network card to perform power-on and power-off operations according to the power-on and power-off signals sent by the first mainboard and the second mainboard and the predetermined processing logic, thereby avoiding the problem of conflicts between power-on and power-off signals sent by different mainboards. In other words, by using the embodiment of the present application, the above two aspects avoid the conflict between the management of the network card by multiple mainboards, solve the technical problem that the network card management method provided by the related technology cannot effectively manage the network card, and achieve the technical effect of improving the management effect of the network card.

[0034] As an optional solution, using an arbitration chip to sort the first management information and the second management information, and sending the first management information and the second management information to the target network card according to the sorting order between the first management information and the second management information includes:

[0035] S1, using the arbitration chip to sort the first management information and the second management information according to the receiving time of the first management information and the receiving time of the second management information, to obtain the sorted first management information and the second management information, wherein the management information corresponding to the earlier receiving time in the sorted first management information and the second management information has a higher sorting order;

[0036] S2, sending the first management information and the second management information to the target network card according to the sorting order between the first management information and the second management information.

[0037] For example, assuming that the arbitration chip receives the first management information at 12:00 and receives the second management information at 12:00:01, the arbitration chip will sort the first management information and the second management information, and give priority to sending the first management information. After the target network card processes the first management information, the second management information will be sent to the target network card so that the target network card processes the second management information.

[0038] It should be noted that the above example is an optional example provided to facilitate explanation of the above network card management method, and there is no limitation on the specific implementation of the above network card management method.

[0039] According to the embodiment of the present application, the arbitration chip is used to sort the first management information and the second management information according to the receiving time of the first management information and the receiving time of the second management information, so as to obtain the sorted first management information and the second management information, wherein the sorted first management information and the second management information have the earlier corresponding receiving time and the higher the sorting order. Then, according to the sorting order between the first management information and the second management information, the first management information and the second management information are sent to the target network card. In other words, according to the embodiment of the present application, by configuring the first adapter board between the mainboard and the network card, and using the arbitration chip configured on the first adapter board, the management information sent earlier is sent to the target network card for processing first, so that the information can be processed in the original sending order, thereby avoiding the problems caused by the wrong order. In addition, this sorting mechanism can optimize the information processing flow, avoid delaying the operation of the entire system due to processing the information that arrives later, and thus improve the overall efficiency of the system. Further, the sorting function of the arbitration chip can reduce the information processing burden of the target network card, because it can receive the information sequence that has been sorted in the correct order, without the need for complex sorting algorithm processing inside the network card. This not only simplifies the design and implementation of the network card, but also may improve its processing efficiency and response speed.

[0040] As an optional solution, the network card management method further includes:

[0041] When the CPLD of the first mainboard receives a startup instruction for the first mainboard, the first power-on signal is sent to the logic chip through the up and down power signal transmission channel; when the target network card successfully performs a power-on operation according to the received first power-on signal, the first power-on prompt information for prompting a successful power-on is sent to the logic chip; when the logic chip receives the first power-on prompt information, the first power-on prompt information is sent to the CPLD of the first mainboard through the up and down power signal transmission channel; when the CPLD of the first mainboard receives the first power-on prompt information, the first mainboard is started;

[0042] When the CPLD of the second mainboard receives a startup instruction for the second mainboard, the second power-on signal is sent to the logic chip through the up and down power signal transmission channel; when the target network card successfully performs a power-on operation according to the received second power-on signal, the second power-on prompt information for prompting the successful power-on is sent to the logic chip; when the logic chip receives the second power-on prompt information, the second power-on prompt information is sent to the CPLD of the second mainboard through the up and down power signal transmission channel; when the CPLD of the second mainboard receives the second power-on prompt information, the second mainboard is started.

[0043] In an embodiment of the present application, when the CPLD of the first mainboard receives a startup instruction for the first mainboard, the first power-on signal is sent to the logic chip through the up and down power signal transmission channel; when the target network card successfully performs a power-on operation according to the received first power-on signal, the first power-on prompt information for prompting a successful power-on is sent to the logic chip; when the logic chip receives the first power-on prompt information, the first power-on prompt information is sent to the CPLD of the first mainboard through the up and down power signal transmission channel; when the CPLD of the first mainboard receives the first power-on prompt information, the first mainboard is started; when the CPLD of the second mainboard receives a startup instruction for the second mainboard, the second power-on signal is sent to the logic chip through the up and down power signal transmission channel; when the target network card successfully performs a power-on operation according to the received second power-on signal, the second power-on prompt information for prompting a successful power-on is sent to the logic chip; when the logic chip receives the second power-on prompt information, the second power-on prompt information is sent to the CPLD of the second mainboard through the up and down power signal transmission channel; when the CPLD of the second mainboard receives the second power-on prompt information, the second mainboard is started. In other words, by adopting the embodiment of the present application, the logic chip is used as an intermediate controller to accurately control the startup process of the first main board, the second main board and the target network card, ensuring the accurate transmission and reception of signals between the logic chip and the main board, thereby achieving precise control of the power-on operation of the main board and the target network card.

[0044] As an optional solution, the network card management method further includes:

[0045] When the CPLD of the first mainboard receives a shutdown command for the first mainboard, the first power-off signal is sent to the logic chip through the up and down electrical signal transmission channel; when the CPLD of the second mainboard receives a shutdown command for the second mainboard, the second power-off signal is sent to the logic chip through the up and down electrical signal transmission channel;

[0046] When the target network card successfully performs the power-off operation according to the received target power-off signal, power-off prompt information for prompting the success of the power-off is sent to the logic chip; when the logic chip receives the power-off prompt information, the power-off prompt information is sent to the CPLD of the first mainboard and the CPLD of the second mainboard through the power-on and power-off signal transmission channel;

[0047] When the CPLD of the first mainboard receives the power-off prompt information, the first mainboard is shut down; when the CPLD of the second mainboard receives the power-off prompt information, the second mainboard is shut down.

[0048] In the embodiment of the present application, when the CPLD of the first mainboard receives the shutdown command for the first mainboard, the first power-off signal is sent to the logic chip through the up and down power signal transmission channel; when the CPLD of the second mainboard receives the shutdown command for the second mainboard, the second power-off signal is sent to the logic chip through the up and down power signal transmission channel; when the target network card successfully performs the power-off operation according to the received target power-off signal, the power-off prompt information for prompting the successful power-off is sent to the logic chip; when the logic chip receives the power-off prompt information, the power-off prompt information is sent to the CPLD of the first mainboard and the CPLD of the second mainboard through the up and down power signal transmission channel; when the CPLD of the first mainboard receives the power-off prompt information, the first mainboard is shut down; when the CPLD of the second mainboard receives the power-off prompt information, the second mainboard is shut down. In other words, by using the embodiment of the present application, the shutdown process of the first mainboard, the second mainboard and the target network card can be accurately controlled by using the logic chip as the intermediate controller, ensuring the accurate transmission and reception of signals between the logic chip and the mainboard, thereby realizing accurate control of the power-off operation of the mainboard and the target network card.

[0049] As an optional solution, the network card management method further includes:

[0050] Configure the LAN switch chip on the third adapter board.

[0051] When the LAN switch chip on the third adapter board receives the first request information sent by the BMC of the first mainboard through the first interface connected to the out-of-band management network channel, the first request information is sent to the target network card using the LAN switch chip.

[0052] When the target network card receives the first request information, the first network card information requested by the first request information is sent to the LAN switch chip, so that the LAN switch chip sends the first network card information to the BMC of the first mainboard through the out-of-band management network channel.

[0053] When the LAN switch chip on the third adapter board receives the second request information sent by the BMC of the second mainboard through the second interface connected to the out-of-band management network channel, the second request information is sent to the target network card using the LAN switch chip.

[0054] When the target network card receives the second request information, the second network card information requested by the second request information is sent to the LAN switch chip, so that the LAN switch chip sends the second network card information to the BMC of the second mainboard through the out-of-band management network channel.

[0055] Optionally, the above-mentioned LAN switch chip is used to manage and control the transmission of data in the network, wherein the LAN switch chip can be configured with but not limited to multiple interfaces connected to the mainboard, and one or more interfaces connected to the target network card to ensure that the request information sent by multiple mainboards can be sent to the target network card through the LAN switch chip.

[0056] It should be noted that, in some embodiments, the first adapter board, the second adapter board, and the third adapter board may be, but are not limited to, the same adapter board, or may be different adapter boards, and this is not limited in the present embodiment.

[0057] Furthermore, in this embodiment, the above-mentioned out-of-band management network channel can be but is not limited to being used to indicate the transmission of Network signals, wherein Network signals are a synonym for various network signals, and can include but are not limited to: NCSI, RGMII, MDI, etc. The network signals output by the LAN switch chip can be directly interconnected with the network card, such as NCSI, MDI, thereby realizing the function of the two motherboard BMCs managing the network card out-of-band through network signals.

[0058] It should be noted that, in this embodiment, the first request information may be, but is not limited to, a Network signal for indicating the network information for obtaining the network card, such as the network card health status information. The second request information may be, but is not limited to, a Network signal for indicating the network information for obtaining the network card, such as the network card health status information. This is not limited in this embodiment.

[0059] According to the embodiment of the present application, a local area network switch LAN switch chip is configured on the third adapter board. When the LAN switch chip on the third adapter board receives the first request information sent by the BMC of the first mainboard through the first interface connected to the out-of-band management network channel, the first request information is sent to the target network card by using the LAN switch chip. When the target network card receives the first request information, the first network card information requested by the first request information is sent to the LAN switch chip, so that the LAN switch chip sends the first network card information to the BMC of the first mainboard through the out-of-band management network channel. When the LAN switch chip on the third adapter board receives the second request information sent by the BMC of the second mainboard through the second interface connected to the out-of-band management network channel, the second request information is sent to the target network card by using the LAN switch chip. When the target network card receives the second request information, the second network card information requested by the second request information is sent to the LAN switch chip, so that the LAN switch chip sends the second network card information to the BMC of the second mainboard through the out-of-band management network channel. In other words, by using the embodiment of the present application, the LAN switch chip can receive and forward request information issued by the BMC (baseboard management controller). Regardless of whether the information comes from the first mainboard or the second mainboard, it can accurately send the information to the target network card, and then the target network card returns the response information to the corresponding BMC, thereby realizing efficient and accurate transmission of information.

[0060] As an optional solution, the network card management method further includes:

[0061] The processor CPU of the first mainboard sends the first data sending request to the target network card through the first network card data channel. When the target network card receives the first data sending request, it will encapsulate the first data carried in the first data sending request and transmit the encapsulated first data to the first address carried in the first data sending request.

[0062] It should be noted that the above-mentioned first network card data channel can be but is not limited to being used to indicate a PClex8, which is used to provide an information transmission channel between the CPU and the network card, so as to successfully send the data to be sent by the mainboard, or successfully transmit the data received by other devices through the network card to the mainboard.

[0063] The CPU of the second mainboard sends the second data sending request to the target network card through the second network card data channel. When the target network card receives the second data sending request, it encapsulates the second data carried in the second data sending request and transmits the encapsulated second data to the second address carried in the second data sending request.

[0064] It should be noted that the above-mentioned first network card data channel can be but is not limited to being used to indicate another PCIex8, which is used to provide an information transmission channel between the CPU and the network card, so as to successfully send the data to be sent by the motherboard, or successfully transmit the data received by other devices through the network card to the motherboard.

[0065] The CPU of the first mainboard sends the first clock signal to the target network card through the first clock signal channel. When the target network card receives the first clock signal, the clock information of the target network card is synchronized based on the clock information carried in the first clock signal.

[0066] Optionally, in this embodiment, the first clock signal channel may be, but is not limited to, used to indicate a link for transmitting a clock signal between the CPU of the first mainboard and the target network card. The first clock signal is a synchronization signal for controlling timing operations inside the network card chip. The clock signal is usually generated by the CPU. This signal is a periodic pulse wave with a very high frequency (e.g., hundreds of megahertz or gigahertz) to ensure the correct transmission and processing of data. Furthermore, the clock information may be, but is not limited to, used to indicate the pulse wave, which is not limited to any limitation in this embodiment.

[0067] The CPU of the second mainboard sends the second clock signal to the target network card through the second clock signal channel. When the target network card receives the second clock signal, the clock information of the target network card is synchronized based on the clock information carried in the second clock signal.

[0068] It should be noted that, in this embodiment, the second clock signal channel may be, but is not limited to, used to indicate a link for transmitting a clock signal between the CPU of the second mainboard and the target network card. The second clock signal is also a synchronization signal for controlling the timing operation inside the network card chip. The clock signal is usually generated by the CPU. This signal is a periodic pulse wave with a very high frequency (e.g., hundreds of megahertz or gigahertz) to ensure the correct transmission and processing of data.

[0069] The CPU of the first mainboard sends a first reset signal to the target network card through a first reset signal channel, wherein when the target network card receives the first reset signal, the target network card will be reset to an initial state based on the first reset signal.

[0070] Optionally, in this embodiment, the above-mentioned first reset signal channel can be but is not limited to being used to indicate a link for transmitting a reset signal between the CPU of the first mainboard and the target network card, and the above-mentioned first reset signal is a control signal for resetting the network card device to an initial state.

[0071] The CPU of the second mainboard sends the second reset signal to the target network card through the second reset signal channel, wherein when the target network card receives the second reset signal, the target network card will be reset to an initial state based on the second reset signal.

[0072] Optionally, in this embodiment, the second reset signal channel may be, but is not limited to, used to indicate a link for transmitting a reset signal between the CPU of the second mainboard and the target network card. The second reset signal is also a control signal for resetting the network card device to an initial state.

[0073] Optionally, in some embodiments, in addition to the first mainboard and the second mainboard, more mainboards may be configured, but not limited to, to implement multiple mainboards for the target network card. Taking three mainboards as an example, the network card management method may include, but not limited to, the following:

[0074] An arbitration chip of the serial communication bus I2C is configured on the first adapter board, a logic chip is configured on the second adapter board, and a local area network switch LAN switch chip is configured on the third adapter board;

[0075] When the arbitration chip on the first adapter board receives the first management information sent by the embedded manager BMC on the first mainboard, the second management information sent by the BMC on the second mainboard, and the third management information sent by the BMC on the third mainboard through I2C, the arbitration chip is used to sort the first management information, the second management information, and the third management information, and the first management information, the second management information, and the third management information are sent to the target network card according to the sorting order between the first management information, the second management information, and the third management information, wherein, when the target network card receives the first management information, the management operation matching the first management information is executed, when the target network card receives the second management information, the management operation matching the second management information is executed, and when the target network card receives the third management information, the management operation matching the third management information is executed;

[0076] When the logic chip on the second adapter board receives the first power-on management signal sent by the complex programmable logic device CPLD of the first main board, the second power-on management signal sent by the CPLD of the second main board, or the third power-on management signal sent by the CPLD of the third main board through the up and down power signal transmission channels, the first power-on management signal or the second power-on management signal is sent to the target network card by using the logic chip, wherein the target network card will perform a power-on operation when receiving the first power-on management signal or the second power-on management signal; when the logic chip receives the first power-off management signal sent by the CPLD of the first main board, the second power-off management signal sent by the CPLD of the second main board, and the third power-off management signal sent by the CPLD of the third main board through the up and down power signal transmission channels, the target power-off management signal is sent to the target network card by using the logic chip, wherein the target network card will perform a power-off operation when receiving the target power-off management signal;

[0077] When the LAN switch chip on the third adapter board receives the first request information sent by the BMC of the first mainboard through the first interface connected to the out-of-band management network channel, the first request information is sent to the target network card using the LAN switch chip;

[0078] When the target network card receives the first request information, the target network card sends the first network card information requested by the first request information to the LAN switch chip, so that the LAN switch chip sends the first network card information to the BMC of the first mainboard through the out-of-band management network channel;

[0079] When the LAN switch chip on the third adapter board receives the second request information sent by the BMC of the second mainboard through the second interface connected to the out-of-band management network channel, the LAN switch chip is used to send the second request information to the target network card;

[0080] When the target network card receives the second request information, the second network card information requested by the second request information is sent to the LAN switch chip, so that the LAN switch chip sends the second network card information to the BMC of the second mainboard through the out-of-band management network channel.

[0081] When the LAN switch chip on the third adapter board receives the third request information sent by the BMC of the third mainboard through the third interface connected to the out-of-band management network channel, the LAN switch chip is used to send the third request information to the target network card;

[0082] When the target network card receives the third request information, the second network card information requested by the third request information is sent to the LAN switch chip, so that the LAN switch chip sends the third network card information to the BMC of the third mainboard through the out-of-band management network channel.

[0083] Optionally, as an optional example, it is possible but not limited to Figure 2 The following steps are used to illustrate the power-on control of the target network card:

[0084] Execute step S202 to step S204: Step S202, after the server mainboard is powered on, the user issues a power-on command to a mainboard, and at this time, the mainboard CPLD first sends a PWREN signal to the smart network card, wherein the PWREN signal is used to indicate a power-on enable indication signal; Step S204, the OR gate or CPLD on the adapter board pulls up the PWREN signal output to the network card;

[0085] Then, step S206 is executed, the mainboard CPLD determines whether the PWRON signal output by the network card is high;

[0086] If it is high, execute step S208 to determine that the network card has completed the startup; then execute steps S210 to S212: Step S210, the mainboard executes the startup; Step S212, after the mainboard is started, access through the I2C or network interface of the BMC to manage the smart network card;

[0087] If it is low, continue to wait;

[0088] Alternatively, as another optional example, it is possible but not limited to: Figure 3The following steps are used to illustrate the power-off control of the target network card:

[0089] Execute step S302, at a certain moment, a certain mainboard executes a shutdown action, and pulls down the PWREN signal to the network card;

[0090] Then, step S304 is executed, the adapter board CPLD or the OR gate determines the level of the PWREN signal output to the network card according to the level of the PWREN signal output by another mainboard;

[0091] If the output of the other mainboard is high, then execute step S306-1 to keep the output to the network card at a high level;

[0092] If the output of another motherboard is low, step S306-2 is executed to pull down the PWREN signal to the network card; then step S308 is executed, and the network card executes the shutdown action.

[0093] The method embodiments provided in the embodiments of the present application can be but are not limited to the following Figure 4 The architecture shown is executed as Figure 4 As shown, the architecture includes: MB0 (i.e., the first mainboard mentioned above), MB1 (i.e., the second mainboard mentioned above), SmartNIC (i.e., the target network card mentioned above), adapter board 402, 9641 / MUX chip (i.e., the arbitration chip mentioned above) configured on the adapter board, logic chip / CPLD, and LAN switch chip.

[0094] Specifically, if Figure 4 As shown, the PCle signal of the Smart NIC comes from a group of ×8 signals sent by the CPU on MB0 and a group of ×8 signals sent by the CPU on MB1; the clock signal of the Smart NIC comes from a group of CLK_0 signals sent by the CPU on MB0 and a group of CLK_1 signals sent by the CPU on MB1; the reset signal of the Smart NIC comes from a group of Reset_0 signals sent by the CPU on MB0 and a group of Reset_1 signals sent by the CPU on MB1;

[0095] Furthermore, the I2C signal can achieve the function of non-conflict between two groups of I2C access to the network card by adding a 9641 chip or a MUX chip on the adapter board. The 9641 chip is a dedicated I2C arbitration chip. The two groups of I2C can arbitrate the bus control right by themselves. The motherboard BMC that wins the bus control right accesses the network card first. After completion, when the bus is idle, the other motherboard BMC obtains the bus control right and then accesses the network card I2C device.

[0096] The above Network signals are used to indicate the aliases of various network signals, including but not limited to NCSI, RGMII, MDI, etc. The NCSI / Network_0 signal of MB0 and the NCSI / Network_1 signal of MB1 are uniformly connected to the LAN switch chip of the third adapter board, and the LAN switch chip outputs network signals that can be directly interconnected with the network card, such as NCSI and MDI, so that the function of the two motherboard BMCs managing the network card out-of-band through network signals is realized.

[0097] PWREN / PWROK (i.e., the power-on enable indication signal and the power-on completion indication signal), after being connected to the second adapter board, can be connected to the logic chip or CPLD. The PWREN signal performs the OR logic, that is, if a mainboard wants to power on the network card, the network card will perform the power-on action, and after the power-on is completed, the PWROK signal will be returned and transmitted to the two mainboards at the same time, which is the AND logic. Based on this, if a mainboard wants to start up, the smart network card will start up with it, realizing the function of a normal network card; when the mainboard is shut down, only when both mainboards are shut down, the smart network card will follow the shutdown function. It not only ensures that the two mainboards can connect, access, and manage the network card functions, but also avoids the conflict of network card control caused by different power-on and power-off states between each other. Among them, the BMC of MB0 sends the PWRPN_0 and PWROK_0 signals, and the BMC of MB1 sends the PWRPN_1 and PWROK_1 signals.

[0098] In this embodiment, a network card management device is also provided, which is used to implement the above embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0099] Figure 5 is a structural block diagram of a network card management device according to an embodiment of the present application, such as Figure 5 As shown, the device comprises:

[0100] A configuration unit 502, configured to configure an arbitration chip of the serial communication bus I2C on the first adapter board, and to configure a logic chip on the second adapter board;

[0101] The first sending unit 504 is used for, when the arbitration chip on the first adapter board receives the first management information sent by the embedded manager BMC on the first mainboard and the second management information sent by the BMC on the second mainboard through the I2C, to sort the first management information and the second management information by using the arbitration chip, and to send the first management information and the second management information to the target network card according to the sorting order between the first management information and the second management information, wherein, when the target network card receives the first management information, it will execute the management operation matched with the first management information, and when the target network card receives the second management information, it will execute the management operation matched with the second management information;

[0102] The second sending unit 506 is used for sending the first power-on management signal or the second power-on management signal to the target network card using the logic chip when the logic chip on the second adapter board receives the first power-on management signal sent by the complex programmable logic device CPLD of the first main board or the second power-on management signal sent by the CPLD of the second main board through the up and down power signal transmission channels, wherein the target network card will perform a power-on operation when receiving the first power-on management signal or the second power-on management signal; and sending the target power-off management signal to the target network card using the logic chip when the logic chip receives the first power-off management signal sent by the CPLD of the first main board and the second power-off management signal sent by the CPLD of the second main board through the up and down power signal transmission channels, wherein the target network card will perform a power-off operation when receiving the target power-off management signal.

[0103] As an optional scheme, the above-mentioned first sending unit includes: a sorting processing module, which is used to use the arbitration chip to sort the first management information and the second management information according to the receiving time of the first management information and the receiving time of the second management information, so as to obtain the sorted first management information and the second management information, wherein the management information with an earlier receiving time in the sorted first management information and the second management information has a higher sorting order; a sending module, which is used to send the first management information and the second management information to the target network card according to the sorting order between the first management information and the second management information.

[0104] As an optional solution, the above-mentioned device also includes: a first starting unit, which is used to send a first power-on management signal to the logic chip through the up and down power signal transmission channel when the CPLD of the first mainboard receives the starting instruction for the first mainboard; when the target network card successfully performs the power-on operation according to the received first power-on management signal, send the first power-on prompt information used to prompt the power-on success to the logic chip; when the logic chip receives the first power-on prompt information, the logic chip sends the first power-on prompt information to the CPLD of the first mainboard through the up and down power signal transmission channel; when the CPLD of the first mainboard receives the first power-on prompt information, the first mainboard is started; a second starting unit, which is used to send a second power-on management signal to the logic chip through the up and down power signal transmission channel when the CPLD of the second mainboard receives the starting instruction for the second mainboard; when the target network card successfully performs the power-on operation according to the received second power-on management signal, send the second power-on prompt information used to prompt the power-on success to the logic chip; when the logic chip receives the second power-on prompt information, the logic chip sends the second power-on prompt information to the CPLD of the second mainboard through the up and down power signal transmission channel; when the CPLD of the second mainboard receives the second power-on prompt information, the second mainboard is started.

[0105] As an optional solution, the above-mentioned device also includes: a third sending unit, which is used to send the first power-off management signal to the logic chip through the up and down power signal transmission channel when the CPLD of the first mainboard receives a shutdown instruction for the first mainboard; and send the second power-off management signal to the logic chip through the up and down power signal transmission channel when the CPLD of the second mainboard receives a shutdown instruction for the second mainboard; a fourth sending unit, which is used to send power-off prompt information for prompting successful power-off to the logic chip when the target network card successfully performs the power-off operation according to the received target power-off management signal; when the logic chip receives the power-off prompt information, the power-off prompt information is sent to the CPLD of the first mainboard and the CPLD of the second mainboard through the up and down power signal transmission channel; a shutdown processing unit, which is used to shut down the first mainboard when the CPLD of the first mainboard receives the power-off prompt information; and shut down the second mainboard when the CPLD of the second mainboard receives the power-off prompt information.

[0106] As an optional solution, the above-mentioned device also includes: a first configuration unit, which is used to configure a local area network switch LAN switch chip on the third adapter board; a fifth sending unit, which is used to send the first request information to the target network card by using the LAN switch chip when the LAN switch chip on the third adapter board receives the first request information sent by the BMC of the first mainboard through the first interface connected to the out-of-band management network channel; a sixth sending unit, which is used to send the first network card information requested by the first request information to the LAN switch chip when the target network card receives the first request information, so that the LAN switch chip sends the first network card information to the BMC of the first mainboard through the out-of-band management network channel; a seventh sending unit, which is used to send the second request information to the target network card by using the LAN switch chip when the LAN switch chip on the third adapter board receives the second request information sent by the BMC of the second mainboard through the second interface connected to the out-of-band management network channel; and an eighth sending unit, which is used to send the second network card information requested by the second request information to the LAN switch chip when the target network card receives the second request information, so that the LAN switch chip sends the second network card information to the BMC of the second mainboard through the out-of-band management network channel.

[0107] As an optional solution, the above-mentioned device also includes: a ninth sending unit, used to send a first data sending request to a target network card through a first network card data channel, wherein, when the target network card receives the first data sending request, the first data carried in the first data sending request will be encapsulated, and the encapsulated first data will be transmitted to the first address carried in the first data sending request; a tenth sending unit, used to send a second data sending request to the target network card through a second network card data channel, wherein, when the target network card receives the second data sending request, the second data carried in the second data sending request will be encapsulated, and the encapsulated second data will be transmitted to the second address carried in the second data sending request; an eleventh sending unit, used to send a first clock signal to the target network card through a first clock signal channel, wherein, when the target network card receives the second data sending request, the second data carried in the second data sending request will be encapsulated, and the encapsulated second data will be transmitted to the second address carried in the second data sending request. When a first clock signal is received, the clock information of the target network card will be synchronized based on the clock information carried in the first clock signal; a twelfth sending unit is used to send the second clock signal to the target network card through a second clock signal channel, wherein, when the target network card receives the second clock signal, the clock information of the target network card will be synchronized based on the clock information carried in the second clock signal; a thirteenth sending unit is used to send the first reset signal to the target network card through a first reset signal channel, wherein, when the target network card receives the first reset signal, the target network card will be reset to an initial state based on the first reset signal; a fourteenth sending unit is used to send the second reset signal to the target network card through a second reset signal channel, wherein, when the target network card receives the second reset signal, the target network card will be reset to an initial state based on the second reset signal.

[0108] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0109] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0110] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0111] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0112] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0113] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0114] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0115] An embodiment of the present application further provides a computer program product, comprising a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program product, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0116] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0117] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0118] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for managing a network card, characterized in that: include: An arbitration chip of the serial communication bus I2C is configured on the first adapter board, and a logic chip is configured on the second adapter board; In the case where the arbitration chip on the first adapter board receives the first management information sent by the embedded manager BMC on the first mainboard and the second management information sent by the BMC on the second mainboard through I2C, the arbitration chip is used to sort the first management information and the second management information, and the first management information and the second management information are sent to the target network card according to the sorting order between the first management information and the second management information, wherein the target network card will execute the management operation matched with the first management information when receiving the first management information, and will execute the management operation matched with the second management information when receiving the second management information; When the logic chip on the second adapter board receives a first power-on signal sent by the complex programmable logic device CPLD of the first mainboard or a second power-on signal sent by the CPLD of the second mainboard through the up and down electrical signal transmission channels, the logic chip is used to send the first power-on signal or the second power-on signal to the target network card, wherein the target network card will perform a power-on operation when receiving the first power-on signal or the second power-on signal; when the logic chip receives a first power-off signal sent by the CPLD of the first mainboard and a second power-off signal sent by the CPLD of the second mainboard through the up and down electrical signal transmission channels, the logic chip is used to send a target power-off signal to the target network card, wherein the target network card will perform a power-off operation when receiving the target power-off signal.

2. The network card management method according to claim 1, characterized in that: The using the arbitration chip to sort the first management information and the second management information, and sending the first management information and the second management information to the target network card according to the sorting order between the first management information and the second management information includes: Using the arbitration chip to sort the first management information and the second management information according to the receiving time of the first management information and the receiving time of the second management information, to obtain the sorted first management information and the second management information, wherein the management information with an earlier receiving time in the sorted first management information and the second management information has a higher sorting order; The first management information and the second management information are sent to the target network card according to the sorting order between the first management information and the second management information.

3. The network card management method according to claim 1, characterized in that: The method further comprises: When the CPLD of the first mainboard receives a startup instruction for the first mainboard, the first power-on signal is sent to the logic chip through the up-and-down power signal transmission channel; when the target network card successfully performs the power-on operation according to the received first power-on signal, the first power-on prompt information for prompting the success of the power-on is sent to the logic chip; when the logic chip receives the first power-on prompt information, the first power-on prompt information is sent to the CPLD of the first mainboard through the up-and-down power signal transmission channel; when the CPLD of the first mainboard receives the first power-on prompt information, the first mainboard is started; When the CPLD of the second mainboard receives a startup instruction for the second mainboard, the second power-on signal is sent to the logic chip through the up and down power signal transmission channel; when the target network card successfully performs the power-on operation according to the received second power-on signal, second power-on prompt information for prompting a successful power-on is sent to the logic chip; when the logic chip receives the second power-on prompt information, the logic chip sends the second power-on prompt information to the CPLD of the second mainboard through the up and down power signal transmission channel; when the CPLD of the second mainboard receives the second power-on prompt information, the second mainboard is started.

4. The method for managing a network card according to any one of claims 1 to 3, characterized in that: The method further comprises: When the CPLD of the first mainboard receives a shutdown instruction for the first mainboard, the first power-off signal is sent to the logic chip through the up / down electrical signal transmission channel; when the CPLD of the second mainboard receives a shutdown instruction for the second mainboard, the second power-off signal is sent to the logic chip through the up / down electrical signal transmission channel; When the target network card successfully performs the power-off operation according to the received target power-off signal, power-off prompt information for prompting the success of the power-off is sent to the logic chip; when the logic chip receives the power-off prompt information, the power-off prompt information is sent to the CPLD of the first mainboard and the CPLD of the second mainboard through the power-on and power-off signal transmission channel; When the CPLD of the first mainboard receives the power-off prompt information, the first mainboard is shut down; when the CPLD of the second mainboard receives the power-off prompt information, the second mainboard is shut down.

5. The method for managing a network card according to any one of claims 1 to 3, characterized in that: The method further comprises: Configure the LAN switch chip on the third adapter board; When the LAN switch chip on the third adapter board receives the first request information sent by the BMC of the first mainboard through the first interface connected to the out-of-band management network channel, the LAN switch chip is used to send the first request information to the target network card; When the target network card receives the first request information, the target network card sends the first network card information requested by the first request information to the LAN switch chip, so that the LAN switch chip sends the first network card information to the BMC of the first mainboard through the out-of-band management network channel; When the LAN switch chip on the third adapter board receives the second request information sent by the BMC of the second mainboard through the second interface connected to the out-of-band management network channel, the LAN switch chip is used to send the second request information to the target network card; When the target network card receives the second request information, the second network card information requested by the second request information is sent to the LAN switch chip, so that the LAN switch chip sends the second network card information to the BMC of the second mainboard through the out-of-band management network channel.

6. The method for managing a network card according to any one of claims 1 to 3, characterized in that: The method further comprises: The processor CPU of the first mainboard sends a first data sending request to the target network card through the first network card data channel, wherein, when the target network card receives the first data sending request, it will encapsulate the first data carried in the first data sending request and transmit the encapsulated first data to the first address carried in the first data sending request; The CPU of the second mainboard sends the second data sending request to the target network card through the second network card data channel, wherein, when the target network card receives the second data sending request, the target network card encapsulates the second data carried in the second data sending request and transmits the encapsulated second data to the second address carried in the second data sending request; The CPU of the first mainboard sends the first clock signal to the target network card through the first clock signal channel, wherein, when the target network card receives the first clock signal, the clock information of the target network card is synchronized based on the clock information carried in the first clock signal; The CPU of the second mainboard sends the second clock signal to the target network card through the second clock signal channel, wherein, when the target network card receives the second clock signal, the clock information of the target network card is synchronized based on the clock information carried in the second clock signal; The CPU of the first mainboard sends a first reset signal to the target network card through a first reset signal channel, wherein when the target network card receives the first reset signal, the target network card will be reset to an initial state based on the first reset signal; The CPU of the second mainboard sends a second reset signal to the target network card through a second reset signal channel, wherein when the target network card receives the second reset signal, the target network card will be reset to an initial state based on the second reset signal.

7. A network card management device, characterized in that: include: A configuration unit, used to configure an arbitration chip of the serial communication bus I2C on the first adapter board, and to configure a logic chip on the second adapter board; a first sending unit, configured to, when the arbitration chip on the first adapter board receives first management information sent by the embedded manager BMC on the first mainboard and second management information sent by the BMC on the second mainboard through I2C, use the arbitration chip to sort the first management information and the second management information, and send the first management information and the second management information to a target network card according to the sorting order between the first management information and the second management information, wherein, when the target network card receives the first management information, it will execute a management operation matched with the first management information, and when the target network card receives the second management information, it will execute a management operation matched with the second management information; The second sending unit is used for, when the logic chip on the second adapter board receives a first power-on signal sent by the complex programmable logic device CPLD of the first main board or a second power-on signal sent by the CPLD of the second main board through the up and down electrical signal transmission channels, using the logic chip to send the first power-on signal or the second power-on signal to the target network card, wherein the target network card will perform a power-on operation when receiving the first power-on signal or the second power-on signal; when the logic chip receives a first power-off signal sent by the CPLD of the first main board and a second power-off signal sent by the CPLD of the second main board through the up and down electrical signal transmission channels, using the logic chip to send a target power-off signal to the target network card, wherein the target network card will perform a power-off operation when receiving the target power-off signal.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method according to any one of claims 1 to 6 when executed by a processor.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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