Space-based intelligent load calculation system

Abstract

The invention provides a space-based intelligent load calculation system. The space-based intelligent load calculation system comprises a backboard, a power supply and external transition module, a main calculation module, a reconfigurable processing module, an intelligent monitoring storage module and a general calculation graphic processing module, the computing module, the reconfigurable processing module, the intelligent monitoring storage module and the general computing graphic processing module all adopt a VNX single-board computer SBC architecture and all comprise a carrier plate and a module SOM arranged on the carrier plate. According to the system, a heterogeneous computing architecture of SOC (CPU + AI) + FPGA + GPGPU is constructed by adopting a VNX standard, the functions of in-orbit reconstruction, dynamic refreshing and the like under the constraints of space application volume, weight and power consumption SWaP are realized, the system adapts to dynamic tasks, the irradiation influence is reduced, and a solution is provided for high-performance, high-reliability and intelligent computing load requirements of microsatellites.

Description

Technical Field

[0001] The present application belongs to the field of aerospace payload computing technology and relates to a space-based intelligent computing payload system. Background Art

[0002] The continuous development of space exploration missions has made spacecraft missions and working environments increasingly complex, and has put forward higher requirements for the intelligence, high performance, and high reliability of spacecraft. Whether it is deep space exploration, manned lunar landing, or space bases and Mars programs, the application and support of artificial intelligence technology are required. For example, in the lunar and Mars exploration missions, due to the long distance between the moon and Mars and the earth, ground operators cannot operate in time, requiring lunar rovers, Mars rovers and other probes to be able to autonomously complete tasks in unknown environments. Deploying artificial intelligence algorithms on spacecraft to enhance the intelligence capabilities of spacecraft has become an important development trend of spacecraft.

[0003] Future spacecraft missions are facing a sharp increase in the required payload processing performance. In space mission applications such as space control, earth observation, space debris identification and capture, lunar and Mars rovers, etc., the payload needs to have higher image resolution, faster data acquisition and transmission rate, and the ability to achieve real-time control, autonomous operation and reduce ground intervention. There is an urgent need for intelligent computing payloads that meet application performance requirements while meeting size, weight and power requirements, and have more flexibility, lower cost, and more powerful computing power to provide powerful solutions for various missions and scientific instrument payloads.

[0004] Space-based computing equipment is constrained by size, weight, and power consumption, but the data that needs to be processed is very large. For example, in extraterrestrial control and intelligent navigation, it is necessary to integrate high-resolution visible light, infrared cameras, lidar, SRA radar and other multi-sensor complex scenes and intelligently process massive data. In the space environment, it is necessary to face environmental adaptability issues such as the huge temperature difference under polar day and night conditions, the huge impact and vibration of launch and landing, and the difficulty of heat dissipation in a vacuum environment; the space environment has high-energy particles, the radiation resistance of electronic devices, and the reliability issues of the system's on-orbit fault tolerance method.

[0005] Existing space-based intelligent computing technologies are mainly divided into two approaches: one is to directly use ground-based COTS (commercial off-the-shelf) intelligent computing chips in low-orbit space environments. The main advantage of this approach is that it relies on mature civilian software and hardware technologies to realize the deployment of aerospace intelligent applications in a short period of time, but there are problems such as insufficient radiation resistance and difficulty in ensuring reliability. In addition, under the constraints of spacecraft space size, weight, and power consumption, it is difficult to achieve light and small application requirements using the existing CPCI and VPX architectures; the other is to develop aerospace-specific intelligent computing chips, but the development cycle and cost of aerospace-specific chips are long and high. At the same time, they are limited by radiation resistance requirements and cannot further improve the process technology, making the computing performance still difficult to match that of ground-based civilian intelligent computing chips. Summary of the invention

[0006] In order to address the deficiencies of the above-mentioned prior art, the present application provides a space-based intelligent computing payload system, which adopts the VNX standard to build a heterogeneous computing architecture of SOC (CPU+AI)+FPGA+GPGPU, and realizes on-orbit reconstruction, dynamic refresh and other functions under the constraints of space application volume, weight, and power consumption SWaP, adapts to dynamic tasks and reduces the impact of radiation, and provides a solution for the high-performance, high-reliability, and intelligent computing payload requirements of microsatellites.

[0007] In order to achieve the above object, the present invention adopts the following technologies: A space-based intelligent computing payload system, comprising a backplane and a power supply and external transition module plugged and connected to the backplane, a main computing module, a reconfigurable processing module, an intelligent monitoring storage module, and a general computing graphics processing module; The power supply and external transition module includes a transition board with an external electrical connector and a power supply module arranged on the transition board. The external electrical connector is used to realize the interconnection between the system and external signals. The power supply module is used to convert the external primary power input into a secondary power supply to provide to the main computing module, the reconfigurable processing module, the intelligent monitoring storage module, and the general computing graphics processing module; The main computing module includes an embedded on-chip SOC that integrates a multi-core CPU and an AI processor, which is used to complete the normal power-on processing tasks, perform scientific data calculations, complete the communication task scheduling and time management of the satellite platform, and provide payload-specific AI computing power and data storage; The reconfigurable processing module includes a radiation-resistant SRAM FPGA, which is used to adapt to the satellite platform's payload interface, communicate with the payload to achieve payload data preprocessing, and load payload AI calculations; The intelligent monitoring storage module includes RT FPGA and the monitoring circuit connected to it, which is used to monitor the healthy working status, working voltage and temperature of each module in the system and report them. It controls the power on / off and restart of each module according to the satellite platform instructions, and realizes the startup, reload and dynamic refresh of SRAM FPGA through the SMAP interface. It receives the injection update instructions through the CAN / RS422 bus, realizes the program reading, writing and erasing of SRAM FPGA, and completes the program update on orbit. The general computing graphics processing module includes the NX GPU module, which is used to complete short-term startup processing tasks and machine learning-based imaging processing tasks, and communicate with the main computing module to realize on-orbit algorithm updates and parameter updates.

[0008] Furthermore, the transition board is plugged into the backplane through an inter-board connector, and the primary power input connected to the power supply module outputs the secondary power through an isolated power supply after passing through a current protection circuit and a surge suppression protection circuit. The output secondary power is provided to other modules through the inter-board connector and the backplane of the transition board.

[0009] Furthermore, the isolated power supply includes a main isolated power supply and an auxiliary isolated power supply. The main isolated power supply is used to convert out +12V5A and provide it to the main computing module, the reconfigurable processing module, and the general computing graphics processing module. The auxiliary isolated power supply is used to convert out +5V1A and provide it to the intelligent monitoring storage module.

[0010] Furthermore, the main computing module, reconfigurable processing module, intelligent monitoring storage module, and general computing graphics processing module all adopt the VNX single-board computer SBC architecture, and all include a carrier board and a module SOM arranged on the carrier board, and each carrier board is connected to the backplane via an inter-board connector; the SOC is integrated in the module SOM of the main computing module; the SRAM FPGA is integrated in the module SOM of the reconfigurable processing module; the RT FPGA and monitoring circuit are integrated in the module SOM of the intelligent monitoring storage module; and the NX GPU module is integrated in the module SOM of the general computing graphics processing module.

[0011] The beneficial effects of the present invention are: The VNX standard is used to build a heterogeneous computing architecture of SOC (CPU+AI)+FPGA+GPGPU, realizing on-orbit reconstruction, dynamic refresh and other functions under the constraints of space application volume, weight and power consumption SWaP, adapting to dynamic tasks and reducing the impact of radiation, providing a solution for the high-performance, high-reliability and intelligent computing payload requirements of micro-satellites. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a block diagram of the overall structure of an embodiment of the present application.

[0013] Figure 2This is a signal block diagram of each module in an embodiment of the present application.

[0014] Figure 3 This is a schematic diagram of the composition of the main computing module of an embodiment of the present application.

[0015] Figure 4 This is a schematic diagram of the composition of a reconfigurable processing module according to an embodiment of the present application.

[0016] Figure 5 This is a schematic diagram of the composition of the intelligent monitoring storage module of an embodiment of the present application.

[0017] Figure 6 Schematic diagram of the composition of a general graphics processing module according to an embodiment of the present application.

[0018] Figure 7 This is a backplane signal interconnection block diagram of an embodiment of the present application. DETAILED DESCRIPTION

[0019] To make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, the implementation modes of the present invention are described in detail below with reference to the accompanying drawings. However, the embodiments described in the present invention are only part of the embodiments of the present invention, rather than all the embodiments.

[0020] The present application embodiment provides a space-based intelligent computing payload system, such as Figure 1 , Figure 2 , Figure 7 As shown, it includes a backplane and a power supply and external transition module plugged into the backplane, a main computing module, a reconfigurable processing module, an intelligent monitoring storage module, and a general computing graphics processing module (GPGPU).

[0021] The power supply and external transition module includes a transition board with an external electrical connector and a power supply module provided on the transition board. The external electrical connector is used to realize the interconnection between the system and external signals, and the power supply module is used to convert the external primary power input into secondary power to provide to the main computing module, the reconfigurable processing module, the intelligent monitoring storage module, and the general computing graphics processing module.

[0022] The main computing module is the core module of the space-based computing payload, including an embedded on-chip SOC that integrates a multi-core CPU and an AI processor. It is used to complete normal power-on processing tasks, perform scientific data calculations, complete communication task scheduling and time management of the satellite platform, and provide payload-specific AI computing power and data storage. It can achieve in-orbit upgrades and algorithm updates through a low-speed bus, and communicate with the satellite platform's computing payload through a high-speed bus to reduce latency and accelerate computing.

[0023] The reconfigurable processing module includes a radiation-resistant SRAM FPGA, which is used to adapt to the satellite platform's payload interface, data routing, and payload communication to achieve payload data preprocessing and load payload AI calculation. FPGA reconfiguration is used to achieve system development flexibility and multi-task adaptability.

[0024] The intelligent monitoring storage module includes RT FPGA and the monitoring circuit connected to it, which is used to monitor the healthy working status, working voltage and temperature of each module in the system and report them. It controls the power on / off and restart of each module according to the satellite platform instructions, and realizes the startup, reload and dynamic refresh of SRAM FPGA through SMAP interface. It receives the injection update instructions through CAN / RS422 bus, realizes the program reading, writing and erasing of SRAM FPGA, and completes the on-orbit program update.

[0025] The general computing graphics processing module includes the NX GPU module, which is used to complete short-term startup processing tasks and machine learning-based imaging processing tasks, and communicate with the main computing module to realize on-orbit algorithm updates and parameter updates.

[0026] The transition board is plugged into the backplane through the inter-board connector. The primary power input connected to the power supply module outputs the secondary power through the isolation power supply after passing through the current protection circuit and the surge suppression protection circuit. The output secondary power is provided to other modules through the inter-board connector and the backplane of the transition board.

[0027] The isolated power supply includes the main isolated power supply and the auxiliary isolated power supply. The main isolated power supply is used to convert +12V5A and provide it to the main computing module, reconfigurable processing module, and general computing graphics processing module. The auxiliary isolated power supply is used to convert +5V1A and provide it to the intelligent monitoring storage module. This isolated power supply method can improve the system's fault tolerance.

[0028] The main computing module, reconfigurable processing module, intelligent monitoring storage module, and general computing graphics processing module all adopt the VNX single-board computer SBC architecture, and all include a carrier board and a module SOM arranged on the carrier board. Each carrier board is connected to the backplane via an inter-board connector.

[0029] SOC is integrated into the module SOM of the main computing module; SRAM FPGA is integrated into the module SOM of the reconfigurable processing module; RT FPGA and monitoring circuit are integrated into the module SOM of the intelligent monitoring storage module; NX GPU module is integrated into the module SOM of the general computing graphics processing module.

[0030] like Figure 3-Figure 6As shown, each carrier board is provided with an interface group and a power management unit connected to the corresponding inter-board connector, and each interface group is configured with an interface power supply; each power management unit is used to convert the secondary power transmitted through the backplane and the inter-board connector into +5V to provide it to the corresponding module SOM.

[0031] The power management unit of the main computing module, reconfigurable processing module, and general computing graphics processing module is also used to provide the converted +5V to the corresponding interface power supply; the interface power supply of the intelligent monitoring storage module is connected to the corresponding inter-board connector, which is used to receive the +5V in the secondary power supply transmitted through the backplane and the inter-board connector; the interface power supply is used to convert +5V to +3.3V to provide it to the corresponding interface group.

[0032] The power management unit of the main computing module, reconfigurable processing module, and general computing graphics processing module is also used to convert the secondary power supply to +5VH, and provide it to the intelligent monitoring storage module for collection through the corresponding inter-board connector and the backplane, and is used to receive the power enable command issued by the intelligent monitoring storage module transmitted by the backplane through the corresponding inter-board connector to power on / off and restart the module.

[0033] Specifically, Figure 3 As shown, the module SOM of the main computing module includes the SOC and the first clock unit, the first memory, the first processor and the storage unit power supply connected thereto. The first processor and the storage unit power supply are used to convert the +5V converted by the power management unit again to power the module SOM of the main computing module. The first clock unit is used to provide the required clock frequency to the SOC; the interface group of the main computing module is connected to the SOC, and the interface group of the main computing module includes a 1553B interface, a CAN interface, an RS422 interface, an I 2 C interface, PCIe interface, GbE Ethernet interface, SRIO interface, GPIO interface, JTAG interface; here, the first memory includes a primary NAND memory, a backup NAND memory, and a DDR memory.

[0034] Specifically, Figure 4 As shown, the module SOM of the reconfigurable processing module includes the SRAM FPGA and the second clock unit, second memory, second processor and storage unit power supply connected thereto. The second processor and storage unit power supply are used to convert the +5V converted by the power management unit again to power the module SOM of the reconfigurable processing module, and the second clock unit is used to provide the required clock frequency to the SRAM FPGA. The interface group of the reconfigurable processing module is connected to the SRAM FPGA, and the interface group of the reconfigurable processing module includes a GTX interface, a LVDS interface, an RS422 interface, an I 2C interface, GPIO interface, SMAP interface. The second memory includes a primary NAND memory, a backup NAND memory, and a DDR memory, which are used to complete data cache processing. Here, the design of the second memory is the same as the first memory design of the main computing module, and both use ECC error correction to improve data reliability. Since SRAM FPGA has poor single-particle upset resistance, the design uses an extended SMAP interface to complete FPGA program loading and dynamic refresh to reduce the single-particle accumulation effect.

[0035] Specifically, Figure 5 As shown, the module SOM of the intelligent monitoring storage module includes the RT FPGA, the monitoring circuit and the third clock unit connected to the RT FPGA, the third memory, the third processor and the storage unit power supply, the third processor and the storage unit power supply are used to convert the +5V converted by the power management unit again to power the module SOM of the intelligent monitoring storage module, and the third clock unit is used to provide the required clock frequency to the RT FPGA; the module SOM of the intelligent monitoring storage module also includes a MiniPCIe NVME solid-state disk, which can provide large-capacity storage for the system, and the interface group of the intelligent monitoring storage module includes a CAN interface connected to the RTFPGA, an ADC interface, an RS422 interface, and an I 2 C interface, JTAG interface, GPIO interface, SMAP interface and PCIe interface connected to MiniPCIe NVME solid state disk. The third memory includes a main NAND memory and a backup NAND memory, which are used as program memory of the reconfigurable processing module.

[0036] Specifically, Figure 6 As shown, the module SOM of the general computing graphics processing module includes the NX GPU module and the fourth memory and power management subunit connected thereto. The NX GPU module can adopt the Jetson Orin NX series. The power management subunit is used to convert the +5V converted by the power management unit again to power the module SOM of the general computing graphics processing module. The interface group of the general computing graphics processing module is connected to the NX GPU module, and the interface group of the general computing graphics processing module includes a GbE Ethernet interface, a DP / HDMI interface, an RS422 interface, an I 2 C interface, DEBUG interface, GPIO interface, PCIe interface, SYSTEM control interface. The fourth memory includes a QSPI NOR FLASH and a LPDDR5.

[0037] Specifically, the backplane is responsible for realizing mechanical interface interconnection and electrical interface interconnection with the functional boards and cards, providing a path for signal interaction inside and outside the system.

[0038] like Figure 7 As shown in the figure, the modules have the following interface connection relationships: The main computing module I 2 C interface and reconfigurable processing module 2 C interface is connected to the backplane through the corresponding inter-board connector, and the I 2 C interface and intelligent monitoring storage module 2 C interface is connected to the backplane through the corresponding inter-board connector, intelligently monitoring the I 2 C interface and general computing graphics processing module's I 2 The C interface is connected to the backplane through the corresponding inter-board connector.

[0039] The RS422 interface of the reconfigurable processing module is connected to the RS422 interfaces of the main computing module, the intelligent monitoring storage module, and the general computing graphics processing module through corresponding inter-board connectors and backplanes respectively; the RS422 interfaces of the reconfigurable processing module and the intelligent monitoring storage module are also connected to the external electrical connector through corresponding inter-board connectors and backplanes respectively; the RS422 interface of the intelligent monitoring storage module is connected to the RS422 interface of the general computing graphics processing module through corresponding inter-board connectors and backplanes.

[0040] The 1553B interface of the main computing module is connected to the external electrical connector through the corresponding inter-board connector and the backplane.

[0041] The LVDS interface of the reconfigurable processing module is connected to the external electrical connector through the corresponding inter-board connector and the backplane.

[0042] The GPIO interface of the intelligent monitoring storage module is connected to the switch enable end of each power management unit on the main computing module, the reconfigurable processing module, and the general computing graphics processing module through the corresponding inter-board connector and the backplane. The ADC interface of the intelligent monitoring storage module is connected to the +5VH telemetry voltage output by the power management unit of the main computing module, the reconfigurable processing module, and the general computing graphics processing module through the corresponding inter-board connector and the backplane.

[0043] The SRIO interface of the main computing module and a PCIe interface of the general computing graphic processing module are connected to the GTX interface of the reconfigurable processing module through corresponding inter-board connectors and a backplane respectively.

[0044] The PCIe interface connected to the MiniPCIe NVME is connected to another PCIe interface of the general computing graphics processing module through a corresponding inter-board connector and a backplane.

[0045] The GbE Ethernet interface of the main computing module is connected to the GbE Ethernet interface of the general computing graphics processing module through a corresponding inter-board connector and a backplane.

[0046] The SMAP interface of the reconfigurable processing module is connected to the SMAP interface of the intelligent monitoring storage module through a corresponding inter-board connector and a backplane.

[0047] The CAN interfaces of the main computing module and the general computing graphics processing module are connected to the CAN interface of the intelligent monitoring storage module through corresponding inter-board connectors and backplanes, and the CAN interface of the intelligent monitoring storage module is connected to the external electrical connector through corresponding inter-board connectors and backplanes.

[0048] Specifically, the backplane is provided with a bus, including an internal system bus and an external system bus, wherein the internal system bus is used to support the above internal interface connection relationship, and the external system bus is used to output to the external system.

[0049] The internal system bus includes secondary power bus, low-speed communication bus, high-speed communication bus, program update bus, etc. Among them, the secondary power bus provides +12V and +5V transmission; the low-speed communication bus RS422 bus adopts a point-to-point full-duplex topology structure to realize the communication between each module and the reconfigurable processing module, and complete the low-speed data instruction interaction within each module; the low-speed communication bus I 2 The C bus adopts a master-slave topology to realize the communication between each module and the intelligent monitoring storage module, and completes the summary of the health status information in each module; the low-speed communication bus CAN bus adopts a bus topology to realize the control data transmission between the main computing module and each module; the high-speed communication bus SRIO×4 bus realizes high-speed data communication between the main computing module and the reconfigurable processing module; the high-speed communication bus PCIe×4 bus realizes high-speed data communication between the general graphics processing module and the reconfigurable processing module; the high-speed communication bus GbE Gigabit Ethernet bus realizes high-speed data communication between the computing module and the graphics processing module; the program update bus is the SMAP bus, which realizes the functions of dynamic refresh and reconstruction of FPGA program between the intelligent monitoring storage module and the reconfigurable processing module.

[0050] The external system bus includes low-speed telemetry bus, low-speed command bus, high-speed communication bus, medium-speed communication bus, etc. Among them, the low-speed telemetry bus is RS422 bus to complete the transmission of system telemetry information; the low-speed command bus is 1553B bus to complete the communication with important satellite service commands, realize the software algorithm update of the main computing module, time management and general graphics processing module algorithm update; the low-speed remote control command bus RS422 / CAN bus receives satellite service remote control commands and data injection to complete the SRAM FPGA online reconstruction of the reconfigurable processing module; the medium-speed communication bus is LVDS bus, which uses a three-wire bus to communicate with the data transmission; the high-speed communication bus is SRIO and LVDS interface to communicate with the payload. The backplane external bus is connected to the transition board through the inter-board connector, and is transferred from the transition board to the system's external electrical connector.

[0051] When applied, the intelligent monitoring storage module is started first, and the power management unit on each module is powered and reset through the GPIO interface; the healthy telemetry of the +5VH power supply voltage of the power management unit of other modules of the system is collected through the ADC interface, and the monitoring circuit in the intelligent monitoring storage module completes the +5VH, +3.3VH, and +1.5VH telemetry voltage collection inside the module; the SRAM FPGA in the reconfigurable processing module is started, reloaded, and dynamically refreshed through the SMAP interface; the satellite platform injection command is received through the CAN bus to realize online reconstruction and other functions; the third memory on the carrier board stores the SRAM FPGA startup and program files, and adopts the main and backup configuration program partition storage combined with ECC error correction and CRC verification to ensure the normal configuration of the SRAM FPGA; after the modules of the system are started normally, the internal I 2 The C bus monitors and aggregates the health information such as the temperature and working status of each module to the intelligent monitoring and storage module. The intelligent monitoring and storage module reports the system health information through the CAN external bus, and can receive the power-on and power-off instructions of the corresponding module through the CAN external bus. The GPIO interface completes the power-on and power-off control of the power management unit on each module.

[0052] In terms of size, weight, and power consumption: This example adopts a functional module design. The module can be quickly iterated through the core board + carrier board to adapt to different application requirements. The main computing processing module, reconfigurable processing module, and general graphics processing module all use the VNX 19mm single-board computer (SBC) architecture. The intelligent monitoring storage module uses the VNX 12.5mm module. The 19mm size is 70% smaller than the 3U VPX. The 5-slot system (4-slot 19mm module and 1-slot 12.5mm module) has a volume of less than 1.2U; at operating temperature, the power dissipation is not less than 90W. It provides a way to realize modularization and miniaturization of space-based computing.

[0053] In terms of dedicated computing power: a heterogeneous high-performance processing architecture based on CPU+AI+FPGA+GPGPU has been built. The main computing module (CPU+AI) and the general-purpose graphics processing module (GPGPU) are used together to greatly increase the AI ​​dedicated computing power to 100TOPs. The main computing module is suitable for regular power-on processing tasks such as scientific data computing, and the general-purpose graphics processing module is suitable for short-term power-on processing tasks such as ground imaging processing tasks. The combination of the two improves the dedicated computing power and makes up for the shortcomings of COTS devices in radiation resistance; the reconfigurable processing module completes data preprocessing and data routing, which can further accelerate AI computing and reduce system latency.

[0054] In terms of fault-tolerant design: a combination of multi-level fault tolerance, system monitoring, and on-orbit updates is adopted to improve the system's fault tolerance capabilities.

[0055] The volatile memory DDR in each module uses an independent memory to store the EDAC error correction code to ensure the normal operation of the system. The non-volatile memory NAND FLASH hardware uses partitioned primary and backup redundant storage to form hardware-level redundant fault tolerance; the software level uses CRC and ECC error correction checks to ensure reliable data storage and reading.

[0056] An intelligent monitoring and storage module based on radiation-resistant FLASH FPGA is designed and powered by an independent power supply. By monitoring and reporting the health status of each module, the module can be reset and powered on and off. At the same time, the intelligent monitoring and storage module dynamically refreshes the reconfigurable processing module to reduce the single-particle cumulative effect and further improve the system's resistance to single-particle effects.

[0057] The system can realize on-orbit software updates. The SOC of the main computing module and the general graphics processing module can realize on-orbit algorithm and important parameter updates through the 1553B bus. The reconfigurable processing module FPGA can complete program updates through the external CAN / RS422 bus by the intelligent monitoring storage module.

[0058] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application.

Claims

1. A space-based intelligent computing payload system, characterized in that: It includes a backplane and a power supply and external transition module plugged into the backplane, a main computing module, a reconfigurable processing module, an intelligent monitoring storage module, and a general computing graphics processing module; The power supply and external transition module includes a transition board with an external electrical connector and a power supply module arranged on the transition board. The external electrical connector is used to realize the interconnection between the system and external signals. The power supply module is used to convert the external primary power input into a secondary power supply to provide to the main computing module, the reconfigurable processing module, the intelligent monitoring storage module, and the general computing graphics processing module; The main computing module includes an embedded on-chip SOC that integrates a multi-core CPU and an AI processor, which is used to complete the normal power-on processing tasks, perform scientific data calculations, complete the communication task scheduling and time management of the satellite platform, and provide payload-specific AI computing power and data storage; The reconfigurable processing module includes a radiation-resistant SRAM FPGA, which is used to adapt to the satellite platform's payload interface, communicate with the payload to achieve payload data preprocessing, and load payload AI calculations; The intelligent monitoring storage module includes RT FPGA and the monitoring circuit connected to it, which is used to monitor the healthy working status, working voltage and temperature of each module in the system and report them. It controls the power on / off and restart of each module according to the satellite platform instructions, and realizes the startup, reload and dynamic refresh of SRAM FPGA through the SMAP interface. It receives the injection update instructions through the CAN / RS422 bus, realizes the program reading, writing and erasing of SRAM FPGA, and completes the program update on orbit. The general computing graphics processing module includes the NX GPU module, which is used to complete short-term startup processing tasks and machine learning-based imaging processing tasks, and communicate with the main computing module to realize on-orbit algorithm updates and parameter updates.

2. The space-based intelligent computing payload system according to claim 1, characterized in that: The transition board is plugged into the backplane through the inter-board connector. The primary power input connected to the power supply module outputs the secondary power through the isolation power supply after passing through the current protection circuit and the surge suppression protection circuit. The output secondary power is provided to other modules through the inter-board connector and the backplane of the transition board.

3. The space-based intelligent computing payload system according to claim 2, characterized in that: The isolated power supply includes a main isolated power supply and an auxiliary isolated power supply. The main isolated power supply is used to convert +12V5A and provide it to the main computing module, reconfigurable processing module, and general computing graphics processing module. The auxiliary isolated power supply is used to convert +5V1A and provide it to the intelligent monitoring storage module.

4. The space-based intelligent computing payload system according to claim 1, characterized in that: The main computing module, reconfigurable processing module, intelligent monitoring storage module, and general computing graphics processing module all adopt the VNX single-board computer SBC architecture, and all include a carrier board and a module SOM disposed on the carrier board. Each carrier board is connected to the backplane through an inter-board connector. The SOC is integrated into the module SOM of the main computing module; The SRAM FPGA is integrated into the modular SOM of the reconfigurable processing module; The RT FPGA and monitoring circuit are integrated into the module SOM of the intelligent monitoring storage module; The NX GPU module is integrated into the SOM module of the general computing graphics processing module.

5. The space-based intelligent computing payload system according to claim 4, characterized in that: Each carrier board is provided with an interface group and a power management unit connected to the corresponding inter-board connector, and each interface group is equipped with an interface power supply; Each power management unit is used to convert the secondary power transmitted through the backplane and the inter-board connector into +5V to provide it to the corresponding module SOM; The power management unit of the main computing module, the reconfigurable processing module, and the general computing graphics processing module is also used to provide the converted +5V to the corresponding interface power supply; The interface power supply of the intelligent monitoring storage module is connected to the corresponding inter-board connector, which is used to receive +5V in the secondary power supply transmitted through the backplane and the inter-board connector; The interface power supply is used to convert +5V to +3.3V to provide to the corresponding interface group; The power management unit of the main computing module, reconfigurable processing module, and general computing graphics processing module is also used to convert the secondary power supply into +5VH, and provide it to the intelligent monitoring storage module for collection through the corresponding inter-board connector and the backplane; and is used to receive the power supply instructions issued by the intelligent monitoring storage module transmitted by the backplane through the corresponding inter-board connector to power on / off and restart the module.

6. The space-based intelligent computing payload system according to claim 5, characterized in that: The module SOM of the main computing module includes the SOC and a first clock unit, a first memory, a first processor and a storage unit power supply connected thereto. The first processor and the storage unit power supply are used to convert the +5V converted by the power management unit again to power the module SOM of the main computing module. The first clock unit is used to provide the required clock frequency to the SOC; The module SOM of the reconfigurable processing module includes the SRAM FPGA and a second clock unit, a second memory, a second processor and a storage unit power supply connected thereto. The second processor and the storage unit power supply are used to reconvert the +5V converted by the power management unit to power the module SOM of the reconfigurable processing module. The second clock unit is used to provide the required clock frequency to the SRAM FPGA. The module SOM of the intelligent monitoring storage module includes the RT FPGA, the monitoring circuit, and a third clock unit connected to the RT FPGA, a third memory, a third processor, and a storage unit power supply. The third processor and the storage unit power supply are used to convert the +5V converted by the power management unit again to power the module SOM of the intelligent monitoring storage module. The third clock unit is used to provide the required clock frequency to the RT FPGA. The module SOM of the general computing graphics processing module includes the NX GPU module and a fourth memory and a power management subunit connected thereto. The power management subunit is used to convert the +5V converted by the power management unit again to power the module SOM of the general computing graphics processing module.

7. The space-based intelligent computing payload system according to claim 6, characterized in that: The interface group of the main computing module is connected to the SOC. The interface group of the main computing module includes a 1553B interface, a CAN interface, an RS422 interface, an I 2 C interface, PCIe interface, GbE Ethernet interface, SRIO interface, GPIO interface, JTAG interface; The interface group of the reconfigurable processing module is connected to the SRAM FPGA. The interface group of the reconfigurable processing module includes a GTX interface, a LVDS interface, an RS422 interface, an I 2 C interface, GPIO interface, SMAP interface; The module SOM of the intelligent monitoring storage module also includes a MiniPCIe NVME solid-state disk. The interface group of the intelligent monitoring storage module includes a CAN interface connected to the RT FPGA, an ADC interface, an RS422 interface, and an I 2 C interface, JTAG interface, GPIO interface, SMAP interface, and PCIe interface connected to MiniPCIe NVME solid state drive; The interface group of the general computing graphics processing module is connected to the NX GPU module. The interface group of the general computing graphics processing module includes a GbE Ethernet interface, a DP / HDMI interface, an RS422 interface, an I 2 C interface, DEBUG interface, GPIO interface, PCIe interface, and SYSTEM control interface.

8. The space-based intelligent computing payload system according to claim 7, characterized in that: The main computing module I 2 C interface and reconfigurable processing module 2 C interface is connected to the backplane through the corresponding inter-board connector, and the I 2 C interface and intelligent monitoring storage module 2 C interface is connected to the backplane through the corresponding inter-board connector, intelligently monitoring the I 2 C interface and general computing graphics processing module's I 2 The C interface is connected to the backplane through the corresponding inter-board connector; The RS422 interface of the reconfigurable processing module is connected to the RS422 interfaces of the main computing module, the intelligent monitoring storage module, and the general computing graphics processing module through corresponding inter-board connectors and backplanes; the RS422 interfaces of the reconfigurable processing module and the intelligent monitoring storage module are also connected to the external electrical connector through corresponding inter-board connectors and backplanes; The RS422 interface of the intelligent monitoring storage module is connected to the RS422 interface of the general computing graphics processing module through a corresponding inter-board connector and a backplane; The 1553B interface of the main computing module is connected to the external electrical connector through the corresponding inter-board connector and the backplane; The LVDS interface of the reconfigurable processing module is connected to the external electrical connector via the corresponding inter-board connector and the backplane; The GPIO interface of the intelligent monitoring storage module is connected to the switch enable end of each power management unit on the main computing module, the reconfigurable processing module, and the general computing graphics processing module through the corresponding inter-board connector and the backplane; The ADC interface of the intelligent monitoring storage module is connected to the +5VH telemetry voltage output by the power management unit of the main computing module, the reconfigurable processing module, and the general computing graphics processing module through the corresponding inter-board connector and the backplane; The SRIO interface of the main computing module and a PCIe interface of the general computing graphics processing module are connected to the GTX interface of the reconfigurable processing module through corresponding inter-board connectors and a backplane respectively; The PCIe interface connected to the MiniPCIe NVME is connected to another PCIe interface of the general computing graphics processing module through a corresponding inter-board connector and a backplane; The GbE Ethernet interface of the main computing module is connected to the GbE Ethernet interface of the general computing graphics processing module through the corresponding inter-board connector and the backplane; The SMAP interface of the reconfigurable processing module is connected to the SMAP interface of the intelligent monitoring storage module through a corresponding inter-board connector and a backplane; The CAN interfaces of the main computing module and the general computing graphics processing module are connected to the CAN interface of the intelligent monitoring storage module through corresponding inter-board connectors and backplanes, and the CAN interface of the intelligent monitoring storage module is connected to the external electrical connector through corresponding inter-board connectors and backplanes.

9. The space-based intelligent computing payload system according to claim 6, characterized in that: The first memory includes a primary NAND memory, a backup NAND memory, and a DDR memory; The second memory includes a primary NAND memory, a backup NAND memory, and a DDR memory; The third memory includes a primary NAND memory and a backup NAND memory; The fourth memory includes a QSPI NOR FLASH and a LPDDR5.

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