Cutting method of digital beam forming chip during FPGA verification
By cutting the digital beamforming chip and replacing the IP core, the problem of insufficient FPGA resources is solved, effective verification of a single FPGA is achieved, the cost is reduced, and the comprehensiveness and accuracy of verification are improved.
Patent Information
- Application Number
- CN202411522160.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-01-24
AI Technical Summary
When digital beam synthesis chips are FPGA verification, the resources of a single FPGA are insufficient and cannot meet all logic and verification needs. The existing solutions are costly, cumbersome and have poor cropping effect.
Reduce the SRAM capacity in the digital beamforming chip and the number of optical fibers in the optical fiber group through at least one trimming, and perform IP core replacement after trimming to achieve verification of a single FPGA.
The use of a single FPGA verification digital beam synthetic chip is realized, reducing the cost, taking into account the comprehensiveness of the verification effect, and replacing the accuracy and effectiveness of the inspection cutting through the IP nuclear replacement.
Smart Images
Figure CN119358481A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of FPGA technology, and in particular to a method for cutting a digital beam synthesis chip during FPGA verification. Background Art
[0002] Digital beamforming is an advanced signal processing technology that forms a directional beam by weighting, phase adjusting and synthesizing the signals of multiple antenna elements, thereby achieving signal aggregation and suppression. The digital beamforming chip has a symmetrical structural design as a whole, which is divided into two optical fiber groups, each group has multiple optical fibers, and the data of each optical fiber is connected to external data through multiple Serdes serial deserializers. The data after serial-to-parallel conversion is unpacked, and each data packet is weighted for initial beam synthesis, and the synthesized data of each optical fiber is transmitted to the mid-end processing module; the mid-end processing module includes functions such as instruction parsing, weight management and data extraction between optical fibers, which can transmit all data of each optical fiber in a single group to the central module. In the central module, the data between the two groups is mainly beamformed again, and the module may also include some auxiliary modules such as instruction and parameter management.
[0003] FPGA, or field programmable gate array, is an integrated circuit chip based on programmable logic units and programmable wiring resources. It is widely used in many fields such as signal processing, hardware design, and network communication. FPGA prototype verification is a verification method based on FPGA before the manufacture of a specific chip. FPGA can be used to verify the various functions of a specific chip. During verification, the design code related to the specific chip, that is, the RTL code, can be transplanted into the FPGA. Before the specific chip is taped out, various functions can be verified as much as possible, thereby checking potential problems in the specific chip and enabling software developers to enter the testing phase of the specific chip in advance. Compared with waveform simulation and accelerator verification, FPGA is closer to the actual usage scenario of a specific chip, and the verification results are more accurate.
[0004] At present, when a digital beamforming chip is verified through FPGA, the resource requirement for the FPGA is the requirement for the FPGA pins and capacity. The internal capacity and number of pins of a single FPGA are limited, and cannot accommodate all the logic and verification requirements of the digital beamforming chip. Generally, two methods are used to solve this problem: first, generate a complete netlist related to the digital beamforming chip, and then divide it into multiple FPGAs respectively, relying on the number of FPGAs to make up for the problem of insufficient resources of a single FPGA; second, trim the original code of the digital beamforming chip, trimming some useless or unimportant logic codes while ensuring the integrity of the verified functions as much as possible.
[0005] However, these measures currently adopted contain at least the following two problems: 1) Simply increasing the number of FPGAs to meet the verification requirements of digital beamforming chips is too costly. In addition, the verification process is very cumbersome and requires continuous debugging of a large number of FPGAs for related operations. 2) When performing code trimming, if the trimming is small, a large number of FPGAs will still be required for verification, and the trimming effect will be poor; if the trimming is too much, the verification effect will be seriously reduced, and a large number of functions may not be verified or the data may be incomplete during verification. Summary of the invention
[0006] In view of the above two problems, the purpose of the present invention is to propose a method for trimming a digital beamforming chip during FPGA verification. By trimming at least once, the verification of the digital beamforming chip can be realized with one FPGA, while taking into account the comprehensiveness of the verification effect to the greatest extent and effectively reducing the cost. In addition, an IP core replacement is designed after at least one trimming, so as to effectively verify the accuracy and effectiveness of the trimming.
[0007] This is achieved through the following technical solutions: A method for cutting a digital beamforming chip during FPGA verification comprises the following steps: S1. Performing the first trimming: performing the first trimming on the digital beam synthesis chip to reduce the capacity of the SRAM in the digital beam synthesis chip and the number of optical fibers in the two optical fiber groups; S2. Perform situation judgment: after the first trimming in step S1, determine whether the verification of the digital beam synthesis chip by the FPGA belongs to the first situation or the second situation; wherein the first situation includes: the FPGA meets the verification requirements for the digital beam synthesis chip; the second situation includes: the FPGA does not meet the verification requirements for the digital beam synthesis chip, and a second trimming is performed to split the two optical fiber groups into inter-optical fiber files and inter-optical fiber group files; S3, performing IP core replacement: when the judgment in step S2 belongs to the first case, obtaining the first resource that cannot be integrated in the digital beam synthesis chip after the first trimming, and replacing the first resource with multiple IP cores that can be recognized by the FPGA; when the judgment in step S2 belongs to the second case, obtaining the second resource that cannot be integrated in the digital beam synthesis chip after the second trimming, and replacing the second resource with multiple IP cores that can be recognized by the FPGA; S4, perform functional verification: after completing the replacement of multiple IP cores in step S3, start the functional verification of the digital beam synthesis chip by PFGA, record the verification results, and determine whether the verification results meet the requirements. If yes, end the operation; if not, return to step S1 to perform the first trimming of the digital beam synthesis chip, and repeat the cycle until the operation ends.
[0008] Through the first trimming, the functions of a large number of units inside the digital beamforming chip can be effectively retained, and only the resources related to the transmission rate can be reduced; through the second trimming, the logic resources related to the optical fiber during verification can be further reduced, so that on the basis of retaining other units inside the digital beamforming chip as much as possible, a single FPGA can be used to verify the chip; in addition, after completing at least one trimming, the IP cores of the resources in the digital beamforming chip that cannot be integrated are replaced, and then functional verification is carried out, so as to accurately obtain the actual effectiveness of the at least one trimming operation.
[0009] Preferably, when the first trimming is performed in step S1, the capacity of the SRAM is at least not less than 4M, and the number of optical fibers in each optical fiber group is not less than 2. When trimming for the first time, the capacity of the SRAM and the number of optical fibers are trimmed and controlled so that the digital beam synthesis chip can maintain certain basic functions and performances and will not lose necessary processing power or communication capabilities due to excessive trimming, and also to ensure the integrity of the internal resources of the digital beam synthesis chip as much as possible.
[0010] Preferably, after the second trimming in step S2, the network port of the digital beam synthesis chip that has undergone the second trimming is replaced with a low-speed serial port. Compared with the network port, the low-speed serial port can further reduce the resource occupation of the FPGA during verification.
[0011] Preferably, when multiple IP cores are replaced in step S3, a PLL phase-locked loop is used to replace a clock module in the first resource or the second resource, a block ram is used to replace a memory in the first resource or the second resource, and a transceiver high-speed transceiver is used to replace a Serdes serial deserializer in the first resource or the second resource.
[0012] Preferably, when a PLL phase-locked loop is used to replace the clock module in the first resource or the second resource, the PLL phase-locked loop is used to at least support the verification of the CPU in the digital beam synthesis chip and the verification of the Serdes serial deserializer interface in the digital beam synthesis chip. The use of the PLL phase-locked loop ensures the quality of the clock signal, which is very important for components such as the CPU and the Serdes serial deserializer interface that have high requirements for clock accuracy, which not only enables the verification to proceed smoothly, but also helps to improve the reliability of the verification.
[0013] Preferably, when a transceiver high-speed transceiver is used to replace a Serdes serial deserializer in the first resource or the second resource, the parameters of the transceiver high-speed transceiver are limited to 1G rate, 20-bit data width and 50MHz parallel data rate. The parameter restrictions here are to ensure that the FPGA can meet the basic communication requirements of the digital beamforming chip during verification.
[0014] Preferably, the functional verification in step S4 includes at least unit testing, interface verification, performance evaluation and physical layer testing. Performing multiple verifications can ensure that the functions of the digital beamforming chip at all levels after at least one trimming can be fully tested, thereby verifying the accuracy and effectiveness of at least one trimming operation.
[0015] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention can realize the verification of the digital beam synthesis chip with one FPGA through at least one trimming, while taking into account the comprehensiveness of the verification effect to the greatest extent and effectively reducing the cost; in addition, an IP core replacement is designed after at least one trimming, so as to effectively verify the accuracy and effectiveness of the trimming. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A flowchart of a method for cutting a digital beam synthesis chip during FPGA verification; Figure 2 The code block diagram of a digital beam synthesis chip after the first trimming; Figure 3 A code block diagram of a digital beam synthesis chip between optical fiber files after the second cutting; Figure 4 A code block diagram of a digital beam synthesis chip after the second cutting of the fiber group file. DETAILED DESCRIPTION
[0017] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.
[0018] like Figure 1 As shown, it is a flow chart of a method for trimming a digital beam synthesis chip during FPGA verification. The digital beam synthesis chip is trimmed at least once and the IP core is replaced according to different situations, and then verification is carried out, so as to effectively obtain the effectiveness and accuracy of the trimming operation.
[0019] The cutting method specifically comprises the following steps: S1. Perform the first trimming: Perform the first trimming of the digital beam synthesis chip to reduce the capacity of the SRAM in the digital beam synthesis chip and the number of optical fibers in the two optical fiber groups. SRAM is a static random access memory inside the digital synthesis chip. When the FPGA and the digital synthesis chip are verified, the SRAM is used to support the fast storage and writing of data between the two. When trimming the SRAM, the capacity of the SRAM can be trimmed to the minimum capacity requirement when the FPGA and the digital synthesis chip are verified, which can reduce the pin and capacity requirements of the SRAM for the FPGA, thereby saving more resources for verification of other units inside the digital beam synthesis chip. The trimming of the two optical fiber groups is also similar for similar reasons and effects. Each optical fiber group will be responsible for its own internal data transmission through multiple optical fibers, and the two optical fiber groups will also use multiple optical fibers for data transmission between groups. Trimming a large number of optical fibers and retaining only the most basic number of optical fibers can also save a large number of pins and capacity required for the digital beam synthesis chip and FPGA to verify.
[0020] like Figure 2 As shown, it is a code block diagram of a digital beam synthesis chip after the first trimming. The digital beam synthesis chip contains multiple units, namely CrossBar cross switch, CPU, SRAM, network port, two fiber groups, center control center and Pro Mid mid-end processing unit. In any fiber group, there are 2 fibers in the group. The fiber group and the corresponding Pro Mid mid-end control unit exchange data through other multiple fibers. The Pro Mid mid-end control unit receives the control of the center control center and can perform inter-fiber beam synthesis on the two fibers at the same time. The two fibers receive the beam packaging data of the center control center with the help of multiple groups of Serdes serial deserializers and complete the time domain change during the data conversion through time domain conversion. The data after time domain conversion is then unpacked and sent to the Pro Mid mid-end control unit for inter-fiber beam synthesis. The center control center can receive external command input, first perform a command judgment to identify the type of command and whether it is valid, then perform a command analysis to identify what specific operation the command is to perform, and then send it to the Pro Mid mid-end processing unit for processing or send it to other peripheral hardware through the APB bus.
[0021] After the Pro Mid mid-end processing unit receives the instruction from the center control center, it also performs an instruction analysis to identify the specific mid-end operation that the Pro Mid mid-end processing unit needs to perform, and uses internal excitation to activate its own operation based on the mid-end operation to be performed, so as to perform operations such as analysis, conversion, and synthesis on the data interacting with the optical fiber group. For example, after parsing out the need to adjust the weight size of data transmission for two optical fibers in an optical fiber group, the Pro Mid mid-end processing unit first performs weight calculation management based on the specific content of the analysis, and transmits the instructions related to the weight calculation operation required by the optical fiber group to the corresponding optical fiber through multiple optical fibers. After the corresponding optical fiber unpacks the data to obtain multiple echo data, it modifies the weight of each echo data based on the weight-related instructions, and then performs beam synthesis to transmit the beam data to the Pro Mid mid-end control unit to wait for inter-optical beam synthesis.
[0022] When two fiber groups interact, multiple echo data of each fiber will be extracted by fiber, that is, converted into photoelectric signals, and transmitted to the corresponding Pro Mid mid-end control unit, and then transmitted to the center control center for a second fiber extraction, and converted into a form that the center control center can recognize and store for storage. In addition, when one fiber in each of the two fiber groups interacts with each other, the two fibers will also send the instruction packets of multiple echo data unpacked from their own data to the center control center through the corresponding Pro Mid mid-end control unit, and then complete the selection of the instruction packets of multiple echo data of each fiber after the corresponding instruction discrimination and instruction parsing. For example, if there are 36 instruction packets, only 1 is selected, and then the instruction packets of the selected 2 fibers are parameterized and adjusted, and then beam synthesis is performed to obtain the beam packaging data between groups. At the same time, all kinds of instructions and data packets generated during the operation of the center control center can be transmitted externally through the APB bus or transmitted to SRAM through the AXI bus of the auxiliary module for storage.
[0023] In this embodiment, when the digital beam synthesis chip needs to be verified by FPGA, the CPU, SRAM, network port, two optical fiber groups, center control center and Pro Mid mid-end processing unit are all connected to multiple pins of FPGA through CrossBar cross switches. These units need to occupy the pins and capacity resources of FPGA when the digital synthesis chip performs a single FPGA verification. Therefore, when the FPGA resources are insufficient, they must be trimmed, but the basic operation of each unit must be guaranteed. Taking the XCVU440 model FPGA as an example, when the FPGA is trimmed for the first time, the capacity of the SRAM after trimming is at least not less than 4M, and the number of optical fibers in each optical fiber group after trimming is not less than 2. This is the minimum requirement for the digital beam synthesis chip to maintain basic transmission functions and performance during verification, so that it will not lose the necessary processing power or communication capacity due to excessive trimming. In addition, after trimming the SRAM and the two optical fiber groups, some pins and capacity resources can be saved in terms of transmission, and other internal units of the digital beam synthesis chip can be effectively verified as much as possible.
[0024] S2, make a situation judgment: after the first trimming in step S1, judge whether the verification of the digital beam synthesis chip by FPGA belongs to the first situation or the second situation; wherein, the first situation includes: FPGA meets the verification requirements of the digital beam synthesis chip; the second situation includes: FPGA does not meet the verification requirements of the digital beam synthesis chip, and a second trimming is performed to split the two optical fiber groups into inter-optical fiber files and inter-optical fiber group files. Through the second trimming, the logic resources related to the optical fiber during the verification can be further reduced, so as to realize the verification of the chip by a single FPGA while retaining other units inside the digital beam synthesis chip as much as possible.
[0025] like Figure 3 The figure shows a code block diagram of the fiber-to-fiber file of a digital beam synthesis chip after the second cutting. The cutting at this time belongs to the standard cutting method. Figure 2 This method cuts off the optical fibers inside each optical fiber group and only retains the optical fiber communication between two different optical fiber groups. At this time, the files related to the optical fibers are the inter-optical files, specifically: the data transmitted when the two optical fiber groups use multiple optical fibers through the corresponding Pro Mid mid-end processing unit and center control center.
[0026] like Figure 4 The figure shows a code block diagram of the fiber group file of a digital beam synthesis chip after the second trimming. The trimming at this time belongs to the extremely simple trimming method. Figure 2In this method, one fiber group is cut off and only one fiber group is retained. At this time, the files related to the fiber are the inter-fiber group files, specifically: the data transmitted by the two fibers in the fiber group and the data transmitted by multiple fibers between the fiber group and the Pro Mid mid-end processing unit.
[0027] Figure 3 and Figure 4 Under the two trimming methods, the resource ratios reserved by each unit in the digital beam synthesis chip are quite different, and it is necessary to make a choice based on the storage requirements, control requirements, and operating speed requirements during actual verification. Taking the center control center and SRAM as examples, under the standard trimming method, the center control center will retain 20.05% of the lookup tables of the programmable logic function units and 4.56% of the registers of the programmable function units, and the SRAM will retain 1.29% of the lookup tables of the programmable logic function units and 1.22% of the registers of the programmable function units; under the minimalist trimming method, the center control center will retain less than 0.01% of the lookup tables of the programmable logic function units and 0% of the registers of the programmable function units, and the SRAM will retain 1.28% of the lookup tables of the programmable logic function units and 38.1% of the registers of the programmable function units.
[0028] In this embodiment, after the second trimming in step S2, if the pins or capacity of the FPGA still cannot meet the verification requirements of the digital beam synthesis chip, the network port replacement can be continued, that is, the network port of the digital beam synthesis chip that has been trimmed for the second time is replaced with a low-speed serial port, for example, an LSIO serial port. LSIO is the abbreviation of Low-Speed Input / Output. This serial port is a low-speed input or output serial port. Compared with the network port, the serial port can further reduce the pins and capacity resources occupied by the FPGA when transmitting data during verification, thereby saving more FPGA resources for other units in the digital synthesis chip except for transmission, so that the FPGA can meet the verification requirements of the digital beam synthesis chip.
[0029] S3, replace the IP core: when the judgment in step S2 belongs to the first case, obtain the first resource that cannot be integrated in the digital beam synthesis chip after the first trimming, and replace the first resource with multiple IP cores that can be recognized by the FPGA. The integration operation is to convert the code into a gate-level netlist. The ability to perform the integration operation means that it can be directly recognized by the FPGA; when the judgment in step S2 belongs to the second case, obtain the second resource that cannot be integrated in the digital beam synthesis chip after the second trimming, and replace the second resource with multiple IP cores that can be recognized by the FPGA.
[0030] In this embodiment, when multiple IP cores are replaced in step S3, a PLL phase-locked loop is used to replace a clock module in the first resource or the second resource, a block ram is used to replace a memory in the first resource or the second resource, and a transceiver high-speed transceiver is used to replace a Serdes serial deserializer in the first resource or the second resource. PLL phase-locked loop, block ram and transceiver high-speed transceiver are all types of IP cores. When performing actual replacement, affected by the actual specifications and performance of the digital beamforming chip, the number and performance of the clock modules are not fixed, the size of the memory is not fixed, and the number and specifications of the SerDes serial deserializers are also not fixed. When performing replacement, the number of corresponding IP cores can be increased to meet the actual replacement needs. For example, to replace 6 groups of 8b / 10b encoded SerDes serial deserializers, 3 transceiver high-speed transceivers are used to replace them, and each transceiver high-speed transceiver replaces 2 SerDes serial deserializers; to replace 64b / 66b encoded SerDes serial deserializers, 6 transceiver high-speed transceivers are used for one-to-one replacement.
[0031] It should be noted that inside the digital beam synthesis chip, the clock module is used to generate clock signals to control each unit to directly perform orderly data transmission; the memory is used to store the data generated by each unit during operation; the Serdes serial deserializer uses time domain conversion to achieve high-speed interactive transmission of related data between each optical fiber in the optical fiber group and high-speed interactive transmission of related data between each optical fiber between the optical fiber group and the corresponding Pro Mid mid-end control unit. The PLL phase-locked loop can generate and adjust high-precision clock signals, thereby replacing the function of the clock module; the block ram block random access memory can provide high-speed and low-latency storage, which can replace the function of the memory; the transceiver high-speed transceiver supports high-speed data transmission and multi-channel operation, and can replace the function of the Serdes serial deserializer to achieve high-speed interaction between different optical fibers.
[0032] In this embodiment, when a PLL phase-locked loop is used to replace a clock module in the first resource or the second resource, the PLL phase-locked loop is used to at least support verification of the CPU in the digital beamforming chip and verification of the Serdes serial deserializer interface in the digital beamforming chip. The use of the PLL phase-locked loop ensures the quality of the clock signal, which is crucial for components such as the CPU and the Serdes serial deserializer interface that have high requirements for clock accuracy, which not only enables verification to proceed smoothly, but also helps to improve the reliability of verification.
[0033] In this embodiment, when a transceiver high-speed transceiver is used to replace a Serdes serial deserializer in the first resource or the second resource, the parameters of the transceiver high-speed transceiver are limited to 1G rate, 20-bit data width, and 50MHz parallel data rate. The parameter restrictions here are to ensure that the FPGA can meet the basic communication requirements of the digital beam synthesis chip during verification.
[0034] S4, perform functional verification: after completing the replacement of multiple IP cores in step S3, start the functional verification of the digital beam synthesis chip by PFGA, record the verification results, and determine whether the verification results meet the requirements. If they meet the requirements, the operation ends; if they do not meet the requirements, return to step S1 to perform the first trimming of the digital beam synthesis chip, and repeat the cycle until the operation ends. After completing at least one trimming, the IP cores of the resources in the digital beam synthesis chip that cannot be integrated are replaced, and then the functional verification is carried out, so that the actual effectiveness of the at least one trimming operation can be accurately obtained.
[0035] In this embodiment, the functional verification in step S4 at least includes unit testing, interface verification, performance evaluation and physical layer testing. Performing multiple verifications can ensure that the functions of the digital beamforming chip at all levels after at least one trimming can be fully tested, thereby verifying the accuracy and effectiveness of at least one trimming operation.
[0036] In summary, the present invention can implement the verification of the digital beamforming chip with one FPGA through at least one trimming, while taking into account the comprehensiveness of the verification effect to the greatest extent and effectively reducing the cost; in addition, an IP core replacement is designed after at least one trimming, so as to effectively verify the accuracy and effectiveness of the trimming, which is significantly progressive.
[0037] The above embodiments are only for illustrating the technical idea of the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.
Claims
1. A method for cutting a digital beamforming chip during FPGA verification, characterized in that: The steps include: S1. Perform the first cutting: Performing a first trimming of the digital beam synthesis chip to reduce the capacity of the SRAM in the digital beam synthesis chip and the number of optical fibers in the two optical fiber groups; S2. Make a situation assessment: After the first trimming in step S1, it is determined whether the verification of the digital beam synthesis chip by the FPGA belongs to the first case or the second case; wherein the first case includes: the FPGA meets the verification requirements for the digital beam synthesis chip; the second case includes: the FPGA does not meet the verification requirements for the digital beam synthesis chip, and a second trimming is performed to split the two optical fiber groups into inter-optical fiber files and inter-optical fiber group files; S3. Replace the IP core: When the judgment in step S2 belongs to the first case, a first resource that cannot be integrated in the digital beam synthesis chip after the first trimming is obtained, and the first resource is replaced with a plurality of IP cores that can be recognized by the FPGA; When the determination in step S2 belongs to the second situation, obtaining the second resource that cannot be integrated in the digital beam synthesis chip after the second trimming, and replacing the second resource with a plurality of IP cores that can be recognized by the FPGA; S4. Perform functional verification: After completing the replacement of multiple IP cores in step S3, start the PFGA functional verification of the digital beam synthesis chip, record the verification results, and determine whether the verification results meet the requirements. If yes, end the operation; if not, return to step S1 to perform the first trimming of the digital beam synthesis chip, and repeat the cycle until the operation ends.
2. The method for cutting a digital beamforming chip during FPGA verification according to claim 1, characterized in that: When the first cutting is performed in step S1, the capacity of the SRAM is at least not less than 4M, and the number of optical fibers in each optical fiber group is not less than 2.
3. The method for cutting a digital beamforming chip during FPGA verification according to claim 1, characterized in that: After the second trimming is performed in step S2, the network port of the digital beam synthesis chip that has undergone the second trimming is replaced with a low-speed serial port.
4. The method for cutting a digital beamforming chip during FPGA verification according to claim 1, characterized in that: When multiple IP cores are replaced in step S3, a PLL phase-locked loop is used to replace a clock module in the first resource or the second resource, a block ram is used to replace a memory in the first resource or the second resource, and a transceiver is used to replace a Serdes serial deserializer in the first resource or the second resource.
5. The method for cutting a digital beamforming chip during FPGA verification according to claim 4, characterized in that: When a PLL phase-locked loop is used to replace a clock module in the first resource or the second resource, the PLL phase-locked loop is used to at least support verification of a CPU in a digital beamforming chip and verification of a Serdes serializer-deserializer interface in the digital beamforming chip.
6. The method for cutting a digital beamforming chip during FPGA verification according to claim 4, characterized in that: When a transceiver high-speed transceiver is used to replace a Serdes serial deserializer in the first resource or the second resource, parameters of the transceiver high-speed transceiver are limited to a 1G rate, a 20-bit data width, and a 50 MHz parallel data rate.
7. The method for cutting a digital beamforming chip during FPGA verification according to claim 1, characterized in that: The functional verification in step S4 at least includes unit testing, interface verification, performance evaluation and physical layer testing.