Multi-core collaborative navigation computer and design method thereof

Abstract

The invention provides a multi-core collaborative navigation computer and a design method thereof in order to overcome the defects that an existing navigation computer is large in processor computing power resource waste, high in hardware circuit cost and large in size and weight. A data processing unit, a gyroscope unit, a quantization unit and an interface protocol conversion unit of a navigation computer are integrated into an integrated circuit, namely an SOPC (System On Programmable Chip) by adopting a multi-core collaborative technology, and a processor and an FPGA (Field Programmable Gate Array) do not need to be independently designed. Therefore, on the basis of having the functions of optical fiber / laser gyroscope control resolving, quantizer control resolving, sensor data processing, navigation resolving, navigation parameter output and the like, the total number of peripheral circuits such as a processor, an FPGA, a FLASH, a DDR (or RAM), a clock circuit, a power supply circuit and the like which need to be equipped for each functional unit by a traditional navigation computer is greatly reduced; and the cost, the size and the weight of the navigation computer are greatly reduced, so that the application of the navigation computer in the aviation airborne field is more competitive.

Description

Technical Field

[0001] The invention relates to a multi-core collaborative navigation computer and a design method thereof. Background Art

[0002] As an important component of an aircraft, the navigation computer is used to provide the aircraft with important information such as speed, real-time position, heading, attitude, and navigation data. Its importance is self-evident. In the field of aviation, low cost and miniaturization have always been important indicators for considering the design level of navigation computers.

[0003] The design and development of navigation computers in the industry usually adopts the method of combining and reconstructing functional unit circuits, that is, the data processing unit, gyroscope unit, quantization unit, interface protocol conversion unit and other functional units of the navigation computer are interconnected and communicated through a digital bus or digital pulse signal to form a navigation computer and realize the function of navigation information processing. Since each functional unit is equipped with processing circuits such as DSP+FPGA, FPGA or digital quantization circuits and their peripheral circuits, it causes a waste of processor computing power resources to a certain extent, and increases the cost and volume weight of the navigation computer hardware circuit. Summary of the invention

[0004] In order to solve the drawbacks of existing navigation computers, such as large waste of processor computing resources, high hardware circuit cost, and large size and weight, the present invention proposes a multi-core collaborative navigation computer and a design method thereof.

[0005] The technical solution of the present invention is:

[0006] A design method for a multi-core collaborative navigation computer includes the following steps:

[0007] Step 1: Design and function division of the main processor of the navigation computer;

[0008] The main processor uses a multi-core SOPC chip that integrates PS and PL, and divides the functions of PS and PL:

[0009] At least one core processor in the PS is used to integrate the data processing unit to realize sensor data processing, navigation solution, and navigation parameter output. Some logic resources in the PL are used for navigation parameter output interface protocol expansion;

[0010] A single-core processor in the PS is used to integrate the gyro unit to implement the fiber / laser gyro control solution, and some logic resources in the PL are used to expand the gyro parameter output interface protocol;

[0011] Some logic resources in PL are used for quantizer control solution and quantizer data acquisition;

[0012] Step 2: Design of the memory of the navigation computer;

[0013] Step 3: Design of DDR circuit of navigation computer;

[0014] Step 4: Design of the clock circuit of the navigation computer;

[0015] Step 5: Design of the power supply circuit of the navigation computer;

[0016] Step 6: Draw the circuit schematic of the navigation computer, design the printed circuit board, and make and process the board;

[0017] Step 7: Make the Circuit Board for the Navigation Computer.

[0018] Furthermore, in step 1, the main processor selects a heterogeneous multi-core SOPC chip integrating PS and PL; some logic resources are reserved in PL for later function expansion.

[0019] Furthermore, step 2 is specifically as follows: selecting a serial communication FLASH circuit with a certain capacity as a memory, which is mainly used for non-volatile storage of SOPC software target code and logic target code.

[0020] Furthermore, step 3 is specifically as follows: the DDR circuit selects a low-power DDR memory with a certain capacity as the memory required for the main processor to run, so as to support the running of the SOPC software program.

[0021] Furthermore, step 4 is specifically as follows: the clock circuit selects an active crystal oscillator with a fixed frequency to provide a frequency reference for the main processor of the navigation computer.

[0022] Furthermore, step 5 is specifically as follows: the power supply circuit selects a multi-channel onboard power supply chip that meets the voltage and power requirements of the multi-core SOPC chip, clock circuit, memory and DDR circuit according to their power supply requirements.

[0023] 7. The design method of a multi-core collaborative navigation computer according to claim 6 is characterized in that step 6 specifically comprises: using EDA software to draw a schematic symbol model of a multi-core SOPC chip, a clock circuit, a memory and a DDR circuit; designing the circuit principle of the navigation computer according to the function of the navigation product, and using Mentor software to draw the circuit schematic diagram of the navigation computer; using EDA software to design a printed circuit board according to the circuit schematic diagram of the navigation computer, forming an EDA file that can be processed and produced for the printed circuit board, and performing board making.

[0024] Furthermore, step 7 is specifically as follows: according to the circuit schematic diagram of the navigation computer, the multi-core SOPC chip, clock circuit, memory and DDR circuit are all soldered on the printed circuit board processed in step 6 to form the circuit board of the navigation computer; according to the functions and performance to be achieved by the navigation computer in the design requirements, the navigation solution software and navigation control logic are developed, and the developed navigation solution software and navigation control logic are loaded on the circuit board of the navigation computer, and it is ensured that they can run on the circuit board of the navigation computer.

[0025] A multi-core collaborative navigation computer is special in that it is designed using the above method.

[0026] The beneficial effects of the present invention are:

[0027] 1. The present invention adopts multi-core collaborative technology to integrate the data processing unit (used to realize sensor data processing, navigation solution, navigation parameter output), gyro unit (used to realize gyro control solution), quantization unit (used to realize quantizer control solution and quantizer data acquisition), interface protocol conversion unit of the navigation computer into an integrated circuit, i.e. SOPC (Programmable System on Chip). SOPC contains two major modules, PS (Processing Systerm) and PL (Programmable Logic), and there is no need to design a processor and FPGA separately. Therefore, the navigation computer designed by the present invention can greatly reduce the total number of peripheral circuits such as processor, FPGA, FLASH, DDR (or RAM), clock circuit, power supply circuit, etc. that traditional navigation computers must be equipped with for each functional unit, which can greatly reduce the cost of navigation computers, reduce the volume and weight of navigation computers, and make its application in the field of aviation airborne more competitive.

[0028] 2. The navigation computer of the present invention can be used for products such as fiber-optic heading and attitude navigation, fiber-optic inertial navigation, and laser inertial navigation, and provides an operating platform for navigation software. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a principle block diagram of the multi-core collaborative navigation computer of the present invention.

[0030] Figure 2 It is a principle block diagram of a high-performance heterogeneous multi-core SOPC processor used in the navigation computer of the present invention. DETAILED DESCRIPTION

[0031] To make the technical solution and advantages of the present invention clearer, the present invention is further described below in conjunction with the accompanying drawings. The number of cores of the multi-core SOPC processor described and shown in the accompanying drawings is 4 cores, and in other embodiments, the number of cores of the multi-core SOPC processor can be any number not less than 2; the architecture of the embodiment of the present invention described and shown in the accompanying drawings can be implemented with various different component selections, connection relationships, and different printed circuit board layouts.

[0032] like Figure 1 As shown, the multi-core collaborative navigation computer provided by the present invention can be used in navigation products such as fiber-optic attitude and navigation, fiber-optic inertial navigation, and laser inertial navigation. The external communication interface protocol conversion of products such as fiber-optic attitude and navigation, fiber-optic inertial navigation, and laser inertial navigation is realized through the configuration of the logic unit inside the navigation computer, providing an operating platform for the navigation software. The multi-core collaborative navigation computer includes a main processor, a FLASH circuit, a DDR circuit, a clock circuit, and a power supply circuit.

[0033] The main processor uses a multi-core SOPC chip to realize sensor data processing, navigation solution, navigation parameter output and gyro control solution. The multi-core SOPC chip includes PS and PL; PS is a multi-core processor used to run the navigation computer software; PL is a programmable logic unit, which implements the interface protocol by configuring its internal logic resources; PS and PL exchange data through the AXI high-speed communication interface built into the multi-core SOPC chip. In addition to the application processing unit, the PS also integrates CAN, SPI, UART, SRAM, Q_SPI CTRL, DDR controller, etc.; the PL integrates conventional FPGA resources such as logic resources and storage, as well as hard cores such as ADC.

[0034] The FLASH circuit is used for non-volatile storage of SOPC software target code, logic target code and data required by the software.

[0035] The clock circuit is used to provide a frequency reference for the main processor of the navigation computer.

[0036] The power supply circuit is used to convert the voltage of the external input power supply to provide power for the multi-core SOPC chip and the clock circuit, FLASH circuit and DDR circuit.

[0037] The design method of the multi-core collaborative navigation computer provided by the present invention is specifically as follows:

[0038] Step 1: Design and function division of the main processor of the navigation computer;

[0039] The main processor of the navigation computer uses a multi-core SOPC chip (heterogeneous multi-core SOPC chip can also be used) that integrates PS (multi-core processor) and PL (programmable logic unit), and the PS and PL in the multi-core SOPC chip are functionally divided to ensure:

[0040] One or more core processors are used to integrate data processing units to realize sensor data processing, navigation solution, and navigation parameter output. Some logic resources in PL are used for navigation parameter output interface protocol expansion.

[0041] One of the core processors is used to integrate the gyro unit to realize the fiber / laser gyro control solution, and some logic units in the PL are used for gyro parameter output interface protocol expansion;

[0042] Some logic resources in PL are used for quantizer control solution (for multi-channel zeroing principle quantizer) and quantizer data acquisition (for other types of quantizers besides multi-channel zeroing principle quantizer).

[0043] The core processors in the PS communicate with the logic resources in the PL using the multi-core SOPC chip internal bus.

[0044] In this embodiment, the main processor of the navigation computer uses a 4-core SOPC chip and performs function allocation:

[0045] The first and second core processors in the PS are used to integrate the data processing unit to realize sensor data processing, navigation solution, and navigation parameter output functions. The third core processor is used for fiber / laser gyro control solution, and the function of the fourth core processor is reserved;

[0046] Part of the logic resources in PL are used to realize quantizer control solution (for multi-channel zeroing principle quantizer) and quantizer data acquisition (for other types of quantizers except multi-channel zeroing principle quantizer), part of the logic resources are used to realize navigation parameter output interface protocol conversion, part of the logic resources are used to realize gyro parameter output interface protocol expansion, part of the logic resources are used to realize navigation computer logic timing control, and some logic resources are reserved for later function expansion;

[0047] like Figure 2 As shown, the 4-core SOPC chip in this embodiment is specifically JFMQL15T, which is composed of PS and PL. In addition to the application processing unit, the PS also integrates CAN, SPI, UART, SRAM, and DDR controllers; the PL integrates conventional FPGA resources such as logic resources and storage, as well as ADC hard cores.

[0048] Step 2: Design of the memory of the navigation computer;

[0049] A serial communication FLASH circuit with a certain capacity is selected as a memory, which is mainly used for non-volatile storage of SOPC software target code and logic target code. In this embodiment, FLASH uses JFM25QL256, whose capacity is 256Mbit.

[0050] Step 3: Design of DDR circuit of navigation computer;

[0051] The DDR circuit selects a DDR memory with a certain capacity and low power consumption as the memory required for the operation of the main processor to support the operation of the SOPC software program. In this embodiment, the DDR circuit selects the SM41J256M16HA DDR3 memory, whose single-chip capacity is 32M×16×8banks and the data transmission rate is 1.6GHz. In order to match the data bit width of the main processor, two SM41J256M16HA DDR3 memories are used, and the software operation space with a capacity of 32M×32×8banks is formed by data splicing.

[0052] Step 4: Design of the clock circuit of the navigation computer;

[0053] The clock circuit selects an active crystal oscillator with a fixed frequency to provide a frequency reference for the main processor of the navigation computer. In this embodiment, the active crystal oscillator selects PX32AEGCGZ-40M, whose output frequency is 40M and output level is TTL level.

[0054] Step 5: Design of the power supply circuit of the navigation computer;

[0055] The power circuit selects a multi-channel on-board power chip that meets the voltage and power requirements of the multi-core SOPC chip, clock circuit, memory and DDR circuit according to their power supply requirements, converts the external input power into voltage, and provides power for the main processor and each chip to ensure that the navigation computer can achieve the corresponding solution function. In this embodiment, the multi-channel on-board power chip uses 2 JCER4644, each with 4 outputs, each with an output current of up to 4A, and can be used in parallel. It also has power-on timing control, which can meet the power-on timing requirements of the main processor.

[0056] Step 6: Draw the circuit schematic of the navigation computer, design the printed circuit board, and make and process the board;

[0057] Use EDA software to draw schematic symbol models of multi-core SOPC chips, clock circuits, memory and DDR circuits; design the circuit principle of the navigation computer according to the functions of the navigation product, and use Mentor software to draw the circuit schematic of the navigation computer, which mainly includes the signal interconnection relationship between the multi-core SOPC chip, clock circuit, memory and DDR circuit to ensure the normal operation of the navigation computer; according to the circuit schematic of the navigation computer, use EDA software to design the printed circuit board, which mainly includes the layout and wiring of the multi-core SOPC chip, clock circuit, memory and DDR circuit, to form an EDA file that can be processed and produced for printed circuit board production, and then carry out board making.

[0058] Step 7: Make the circuit board of the navigation computer;

[0059] According to the circuit schematic diagram of the navigation computer, the multi-core SOPC chip, clock circuit, memory and DDR circuit are all mounted and soldered on the printed circuit board processed in step 6 to form the circuit board of the navigation computer; according to the design requirements of the functions and performance to be achieved by the navigation computer, the navigation solution software and navigation control logic are developed, and the developed navigation solution software and navigation control logic are loaded on the circuit board of the navigation computer, and it is ensured that they can run on the circuit board of the navigation computer.

Claims

1. A design method for a multi-core collaborative navigation computer, characterized in that: The following steps are involved: Step 1: Design and function division of the main processor of the navigation computer; The main processor uses a multi-core SOPC chip that integrates PS and PL, and divides the functions of PS and PL: At least one core processor in the PS is used to integrate the data processing unit to realize sensor data processing, navigation solution, and navigation parameter output. Some logic resources in the PL are used for navigation parameter output interface protocol expansion; A single-core processor in the PS is used to integrate the gyro unit to implement the fiber / laser gyro control solution, and some logic resources in the PL are used to expand the gyro parameter output interface protocol; Some logic resources in PL are used for quantizer control solution and quantizer data acquisition; Step 2: Design of the memory of the navigation computer; Step 3: Design of DDR circuit of navigation computer; Step 4: Design of the clock circuit of the navigation computer; Step 5: Design of the power supply circuit of the navigation computer; Step 6: Draw the circuit schematic of the navigation computer, design the printed circuit board, and make and process the board; Step 7: Make the Circuit Board for the Navigation Computer.

2. The design method of a multi-core collaborative navigation computer according to claim 1, characterized in that: In step 1, the main processor uses a heterogeneous multi-core SOPC chip that integrates PS and PL; some logic resources are reserved in PL for later function expansion.

3. The design method of a multi-core collaborative navigation computer according to claim 2, characterized in that: Step 2 is specifically as follows: a serial communication FLASH circuit with a certain capacity is selected as a memory, which is mainly used for non-volatile storage of SOPC software target code and logic target code.

4. The design method of a multi-core collaborative navigation computer according to claim 3, characterized in that: Step 3 is specifically as follows: the DDR circuit selects a low-power DDR memory with a certain capacity as the memory required for the main processor to run, so as to support the running of the SOPC software program.

5. The design method of a multi-core collaborative navigation computer according to claim 4, characterized in that: Step 4 is specifically as follows: the clock circuit selects an active crystal oscillator with a fixed frequency to provide a frequency reference for the main processor of the navigation computer.

6. The design method of a multi-core collaborative navigation computer according to claim 5, characterized in that: Step 5 is specifically as follows: the power circuit selects a multi-channel onboard power chip that meets the voltage and power requirements of the multi-core SOPC chip, clock circuit, memory and DDR circuit according to their power supply requirements.

7. The design method of a multi-core collaborative navigation computer according to claim 6, characterized in that: Step 6 is specifically as follows: use EDA software to draw schematic symbol models of multi-core SOPC chips, clock circuits, memory and DDR circuits; design the circuit principle of the navigation computer according to the functions of the navigation product, and use Mentor software to draw the circuit schematic of the navigation computer; use EDA software to design a printed circuit board according to the circuit schematic of the navigation computer, form an EDA file that can be processed and produced for the printed circuit board, and perform board making.

8. The design method of a multi-core collaborative navigation computer according to claim 7, characterized in that: Step 7 is specifically as follows: according to the circuit schematic diagram of the navigation computer, the multi-core SOPC chip, clock circuit, memory and DDR circuit are all mounted and soldered on the printed circuit board processed in step 6 to form the circuit board of the navigation computer; according to the functions and performance to be achieved by the navigation computer in the design requirements, the navigation solution software and navigation control logic are developed, and the developed navigation solution software and navigation control logic are loaded on the circuit board of the navigation computer, and it is ensured that they can run on the circuit board of the navigation computer.

9. A multi-core collaborative navigation computer, characterized in that: The invention is designed by the method described in any one of claims 1 to 8.

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