A method and device for improving the design efficiency of TFT semiconductor devices

Abstract

The present invention belongs to the technical field of semiconductor device design and simulation, and provides a method and device for improving the design efficiency of TFT semiconductor devices. The method includes the following steps: S1: Obtain the design data of the geometric model of the TFT semiconductor device, and the model includes the geometric models of several device components; S2: Respectively assign boundary conditions, material properties, and mesh generation control parameters to the geometric models of each device component; S3: Perform preliminary processing on the geometric model to obtain a base mesh; S4: Generate a coarse mesh according to the generated base mesh and the parameters of the geometric model; S5: Adopt a concentric shell layer segmentation strategy to refine the mesh in the area with small angles in the coarse mesh to generate a fine mesh; S6: Input the generated fine mesh into the device simulation solver for solution, and adjust the design data according to the solution result. This method improves the design efficiency and significantly shortens the design cycle through fine mesh division and optimized simulation processes.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device design and simulation, and particularly to a method and device for improving the design efficiency of TFT semiconductor devices. Background Art

[0002] A thin film transistor (TFT) is a semiconductor device. TFT displays are the mainstream display devices on various notebook computers and desktop computers. Each liquid crystal pixel on such displays is driven by a thin film transistor integrated behind the pixel. Therefore, TFT displays are also a type of active matrix liquid crystal display device. It is one of the best LCD color displays. TFT displays have advantages such as high responsiveness, high brightness, and high contrast, and their display effects are close to those of CRT displays.

[0003] In the design process of TFT semiconductor devices, accurately simulating device performance is crucial for optimizing the design. Simulating device performance is achieved by establishing a discrete mathematical model based on the grid obtained from device meshing. The quality of the generated grid has a decisive impact on the accuracy of simulating device performance. However, due to principle limitations, the grid meshing method used in traditional device design is prone to meshing failure due to infinite loops. Relaxing the grid generation accuracy to avoid this problem will result in unreasonable grid division, and further lead to problems such as inaccurate simulation calculations, resulting in low design efficiency.

[0004] Therefore, it is particularly important to develop a method that can effectively improve design efficiency and ensure simulation accuracy. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a method and device for improving the design efficiency of TFT semiconductor devices. Through fine grid division and optimized simulation processes, the present invention realizes a double improvement in design efficiency and simulation accuracy.

[0006] In a first aspect, embodiments of the present invention provide a method for improving the design efficiency of TFT semiconductor devices, including the following steps:

[0007] S1: Obtain design data of the geometric model of the TFT semiconductor device, where the geometric model of the TFT semiconductor device includes geometric models of several device components;

[0008] S2: Assign boundary conditions, material properties, and geometric model grid generation control parameters to the geometric model of each device component respectively;

[0009] S3: Perform preliminary processing on the geometric model of the TFT semiconductor device to obtain a base grid;

[0010] S4: Generate the coarse grid of the TFT semiconductor device based on the generated base grid, the boundary conditions, material properties, and grid generation control parameters of the geometric model of the TFT semiconductor device;

[0011] S5: Adopt a concentric shell segmentation strategy to refine the grid in the areas with small angles in the coarse grid to generate a fine grid;

[0012] S6: Input the generated fine grid into a device simulation solver for solution, and adjust the design data of the TFT semiconductor device according to the solution results.

[0013] According to a specific implementation manner of an embodiment of the present invention, the device component is a gate, a drain, an insulating layer, etc.

[0014] According to a specific implementation manner of an embodiment of the present invention, in step S2, the boundary conditions include metal-semiconductor boundary, metal-metal boundary, metal-insulator boundary, semiconductor-semiconductor boundary, semiconductor-insulator boundary, applied voltage, applied current, etc.; the material properties include doping type and concentration, defect model and its corresponding parameters, dielectric constant, mobility model and its corresponding parameters, etc.; the geometric model grid generation control parameters include grid cell type, minimum grid size, grid gradient coefficient, etc.

[0015] According to a specific implementation manner of an embodiment of the present invention, in step S3, the preliminary processing includes interference analysis, component position adjustment, characteristic parameter adjustment, and construction of a topological model based on the geometric model and calculation attributes of the TFT semiconductor device; the topological model discretizes the geometric model of the TFT semiconductor device according to the geometric model grid generation control parameters to obtain a base grid.

[0016] According to a specific implementation manner of an embodiment of the present invention, in step S3, further optimize the base grid, and the optimization processing includes region decomposition of the base grid to obtain multiple sub-regions, and discretization processing according to the characteristics of the edges on the boundaries of each sub-region.

[0017] According to a specific implementation manner of an embodiment of the present invention, in step S4, the coarse grid includes point grid, line grid, surface grid, and volume grid, which are respectively generated based on the geometric points, geometric lines, geometric surfaces, and topological model in the base grid.

[0018] According to a specific implementation manner of an embodiment of the present invention, in the step S5, the concentric shell layer segmentation strategy is specifically as follows: taking the shared vertex of the line grid in the small-angle region as the center, constructing concentric circle shells with a power of 2 as the radius as the segmentation points. Analyze the coarse grid data to identify the small-angle grid regions; adopt an improved grid refinement algorithm to segment the line grid in the small-angle region in a non-centered manner, using the concentric circle shells as the segmentation points, effectively preventing the generation of dead loops and improving the grid quality.

[0019] According to a specific implementation manner of an embodiment of the present invention, in the step S6, the simulation solver is used to perform simulation calculations on the fine grid and output the device performance parameters.

[0020] In a second aspect, an embodiment of the present invention provides a device for improving the design efficiency of TFT semiconductor devices, including:

[0021] An acquisition module for acquiring the design data of the geometric model of the TFT semiconductor device, where the geometric model of the TFT semiconductor device includes the geometric models of several device components;

[0022] An assignment module for respectively assigning boundary conditions, material properties, and geometric model grid generation control parameters to the geometric models of each of the device components;

[0023] A processing module for performing preliminary processing on the geometric model of the TFT semiconductor device to obtain a base grid;

[0024] A coarse grid module for generating the coarse grid of the TFT semiconductor device according to the generated base grid and the boundary conditions, material properties, and grid generation control parameters of the geometric model of the TFT semiconductor device;

[0025] A fine grid module for using the concentric shell layer segmentation strategy to refine the grid in the regions with small angles in the coarse grid to generate a fine grid;

[0026] A solution module for inputting the generated fine grid into a device simulation solver for solution and adjusting the design data of the TFT semiconductor device according to the solution result.

[0027] In a third aspect, an embodiment of the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps of the method for improving the design efficiency of TFT semiconductor devices in the foregoing first aspect or any implementation manner of the first aspect.

[0028] The embodiments of the present invention at least have the following technical effects:

[0029] First, through fine grid division and optimized simulation processes, the present invention improves the design efficiency and significantly shortens the design cycle.

[0030] Second, the improved grid refinement algorithm of the present invention effectively solves the problem of unstable simulation in small-angle regions and improves the accuracy of simulation results.

[0031] Third, the timely feedback of the simulation results of the present invention provides strong support for device design and enhances the flexibility and adjustability of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0033] Figure 1 Shows a flowchart of a method for improving the design efficiency of a TFT semiconductor device provided by an embodiment of the present invention;

[0034] Figure 2 Shows a schematic diagram of concentric shell layer segmentation in an embodiment of the present invention;

[0035] Figure 3 Shows a structural block diagram of a device for improving the design efficiency of a TFT semiconductor device provided by an embodiment of the present invention;

[0036] Figure 4 Shows a schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The following will describe in detail the embodiments of the technical solutions of the present invention with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and, therefore, are only examples and should not be used to limit the protection scope of the present invention.

[0038] It should be noted that unless otherwise specified, the technical terms or scientific terms used in this application should have the ordinary meaning understood by those skilled in the art to which the present invention belongs.

[0039] Figure 1 For the step flowchart of a method for improving the design efficiency of a TFT semiconductor device provided by an embodiment of the present invention, see Figure 1 , the method includes the following steps:

[0040] S1: Obtain the design data of the geometric model of the TFT semiconductor device, where the geometric model of the TFT semiconductor device includes the geometric models of several device components.

[0041] The geometric model of the TFT semiconductor device includes the geometric models of several device components, generally including a gate, a drain, an insulating layer, etc.

[0042] S2: Assign boundary conditions, material properties, and geometric model mesh generation control parameters to the geometric models of each device component respectively.

[0043] Specifically:

[0044] Assign boundary conditions, material properties, and geometric model mesh generation control parameters to the geometric model of each device component involved in the design.

[0045] Boundary conditions include: metal-semiconductor boundary, metal-metal boundary, metal-insulator boundary, semiconductor-semiconductor boundary, semiconductor-insulator boundary, applied voltage, applied current, etc.

[0046] Material properties include: doping type and concentration, defect model and its corresponding parameters, dielectric constant, mobility model and its corresponding parameters, etc.

[0047] Geometric model mesh generation control parameters include: mesh cell type, minimum mesh size, mesh gradient coefficient, etc.

[0048] S3: Perform preliminary processing on the geometric model of the TFT semiconductor device to obtain a base mesh.

[0049] Specifically:

[0050] Perform interference analysis on the geometric model of the TFT semiconductor device, and eliminate geometric interference between device components by adjusting component positions, adjusting characteristic parameters, etc. Construct mutual mappings of the boundary conditions and material properties, these calculation properties assigned in S2, and obtain a topological model based on the geometric model and calculation properties of the semiconductor device; then, according to the mesh generation control parameters in S2 from the obtained topological model, discretize the geometric model of the semiconductor device to obtain a preliminary base mesh.

[0051] Furthermore, perform attribute region decomposition on the preliminary base mesh based on the attributes (of each device component) included in the topological model to obtain multiple sub-regions, and the sub-regions respectively correspond to each device component. For each edge on the boundary of the sub-region, if the angle where its endpoint is located is a right angle, then adopt the fractional knapsack algorithm to discretize the edge according to the given control parameters such as the minimum mesh size and the mesh gradient coefficient, otherwise no discretization process is performed; thus, an optimized base mesh is obtained.

[0052] S4: Generate a coarse mesh of the TFT semiconductor device according to the generated base mesh and the boundary conditions, material properties, and mesh generation control parameters of the geometric model of the TFT semiconductor device.

[0053] Specifically:

[0054] According to the boundary conditions, material properties, and mesh generation control parameters (determined corresponding to each device component) of the generated base mesh and the semiconductor device geometry model, generate point meshes, line meshes, surface meshes, and volume meshes of the semiconductor device, that is, coarse meshes.

[0055] Based on each geometric point in the base mesh obtained in S3, point meshes are obtained; at the same time, using the points in two point meshes as endpoint constraints, each geometric line in the semiconductor device geometry model is discretized to obtain line meshes; combining the line meshes and the topology model obtained in S3, the line mesh data is encapsulated according to the geometric surfaces in the semiconductor device geometry model to obtain surface meshes; the surface meshes are further encapsulated according to the topology model and the semiconductor device geometry model to obtain volume meshes.

[0056] S5: For the regions with small angles in the coarse mesh, adopt a concentric shell segmentation strategy to refine the mesh and generate fine meshes.

[0057] Specifically:

[0058] Analyze the coarse mesh data generated in S4 to identify the mesh regions with small angles (referring to the regions where the edge angles in the line meshes are less than 90°).

[0059] Since numerical instability is likely to occur in the device simulation solution in small-angle regions, resulting in divergent solutions and thus causing the failure of the semiconductor simulation design process, generally, mesh refinement is carried out in the mesh regions with small angles. Traditional mesh refinement algorithms are achieved by inserting points in the middle of the line meshes in small-angle mesh regions. However, in practice, when the edge angle is less than 60°, the mesh quality will significantly decline. When the angle is less than 45°, this method is prone to falling into an infinite loop and further deteriorating the mesh quality, resulting in refinement failure.

[0060] This step is a mesh division strategy for dealing with regions with small angles. This strategy divides the line meshes in small-angle regions in a non-centered manner to avoid the problem of mesh quality degradation that may be caused by traditional midpoint division.

[0061] Such as Figure 2As shown, when one side of the small-angle grid area in the line grid meets another side at an angle less than 90°, instead of simply dividing at the midpoint of the sub-segment, a certain circular shell centered on the shared vertex is selected as the division point, and the radii of these circular shells are powers of 2 (2^i, where i is an integer); this concentric shell division strategy can effectively prevent the problem of dead loop generation, so that the grid can be stably and successfully refined, improving the numerical calculation stability of the device simulation algorithm in this area, and thus enhancing the success rate of the simulation design. When the angle between one side and another side in the line grid is greater than 90°, no division is performed.

[0062] Then, based on the line grid after the division process, surface grids and volume grids are regenerated to obtain fine grids.

[0063] S6: Input the generated fine grids into the device simulation solver for solution, and adjust the design data of the TFT semiconductor device according to the solution results.

[0064] S6 specifically is:

[0065] The device simulation solver can use existing tools such as Nuwa, input the generated fine grids into the device simulation solver for solution, and adjust the device design according to the results. Since the grid is successfully refined, the numerical stability of the simulation solution is stably improved, and the results can be smoothly output to guide the optimization design.

[0066] It should be noted that arranging each module in a flow layout is only one embodiment of the present invention, and other arrangements can also be adopted. The present invention does not limit this.

[0067] The embodiments of the present invention have the following technical effects:

[0068] First, improve the design efficiency: Through fine grid division and optimized simulation processes, the present invention significantly shortens the design cycle.

[0069] Second, improve the simulation accuracy: The improved grid refinement algorithm of the present invention effectively solves the problem of unstable simulation in the small-angle area and improves the accuracy of the simulation results.

[0070] Third, enhance the design flexibility: The timely feedback of the simulation results of the present invention provides strong support for device design, enhancing the flexibility and adjustability of the design.

[0071] Figure 3 It is a structural block diagram of a device for improving the design efficiency of a TFT semiconductor device provided by an embodiment of the present invention. The device includes:

[0072] An acquisition module for acquiring design data of a geometric model of a TFT semiconductor device, where the geometric model of the TFT semiconductor device includes geometric models of a plurality of device components;

[0073] An assignment module for respectively assigning boundary conditions, material properties, and geometric model mesh generation control parameters to the geometric models of each device component;

[0074] A processing module for preliminarily processing the geometric model of the TFT semiconductor device to obtain a base mesh;

[0075] A coarse mesh module for generating a coarse mesh of the TFT semiconductor device according to the generated base mesh, boundary conditions, material properties, and mesh generation control parameters of the geometric model of the TFT semiconductor device;

[0076] A fine mesh module for refining the mesh in the area with small angles in the coarse mesh by using a concentric shell segmentation strategy to generate a fine mesh;

[0077] A solving module for inputting the generated fine mesh into a device simulation solver for solving, and adjusting the design data of the TFT semiconductor device according to the solving result.

[0078] Figure 3 The functions of the modules in the embodiments correspond to the contents in the corresponding method embodiments, and will not be elaborated here.

[0079] Figure 4 The structural schematic diagram of the electronic device 40 provided by the embodiment of the present invention is shown. The electronic device 40 includes at least one processor 401 (such as a CPU), at least one input / output interface 404, a memory 402, and at least one communication bus 403 for realizing the connection and communication between these components. The at least one processor 401 is used to execute computer instructions stored in the memory 402, so that the at least one processor 401 can execute the embodiments of any of the foregoing methods for improving the design efficiency of the TFT semiconductor device. The memory 402 is a non-transitory memory, which may include volatile memory, such as high-speed random access memory (RAM: Random Access Memory), and may also include non-volatile memory, such as at least one disk memory. The communication connection with at least one other device or unit is realized through at least one input / output interface 404 (which may be a wired or wireless communication interface).

[0080] In some embodiments, the memory 402 stores a program 4021, and the processor 401 executes the program 4021 to execute the content in any of the foregoing method embodiments.

[0081] The electronic device may exist in various forms, including but not limited to:

[0082] (1) Mobile communication devices: Such devices are characterized by having mobile communication functions and mainly aim to provide voice and data communications. Such terminals include: smart phones, multimedia phones, functional phones, and low-end phones, etc.

[0083] (2) Ultra-mobile personal computer devices: Such devices belong to the category of personal computers, have computing and processing functions, and generally also have the characteristic of mobile Internet access. Such terminals include: PDA, MID, and UMPC devices, etc.

[0084] (3) Portable entertainment devices: Such devices can display and play multimedia content. Such devices include: audio and video players, handheld game consoles, e-books, and smart toys and portable vehicle navigation devices.

[0085] (4) Specific servers: Devices that provide computing services. The composition of a server includes a processor, hard disk, memory, system bus, etc. A server is similar to a general computer architecture, but due to the need to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, manageability, etc.

[0086] (5) Other electronic devices with data interaction functions.

[0087] It should be understood that each part of the present invention can be implemented by hardware, software, firmware, or a combination thereof.

[0088] In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits with appropriate combinational logic gate circuits, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

[0089] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A method for improving the design efficiency of TFT semiconductor devices, characterized in that, Including the following steps: S1: Obtain the design data of the geometric model of the TFT semiconductor device, where the geometric model of the TFT semiconductor device includes the geometric models of a number of device components; S2: Assign boundary conditions, material properties, and geometric model mesh generation control parameters to the geometric models of each of the device components respectively; S3: Perform preliminary processing on the geometric model of the TFT semiconductor device to obtain a base mesh; S4: Generate a coarse mesh of the TFT semiconductor device according to the generated base mesh and the boundary conditions, material properties, and mesh generation control parameters of the geometric model of the TFT semiconductor device; S5: Use a concentric shell segmentation strategy to refine the mesh in the areas with small angles in the coarse mesh to generate a fine mesh; the concentric shell segmentation strategy is: when one side of a small angle mesh area in a line mesh meets another side at an angle less than 90°, select a certain circular shell centered on the shared vertex as the segmentation point, and the radii of these circular shells are powers of 2; while when the angle between one side and another side in the line mesh is greater than 90°, no segmentation is performed; S6: Input the generated fine mesh into a device simulation solver for solution, and adjust the design data of the TFT semiconductor device according to the solution result.

2. The method for improving the design efficiency of a TFT semiconductor device according to claim 1, wherein: The device components are a gate, a drain, or an insulating layer.

3. The method for improving the design efficiency of a TFT semiconductor device according to claim 1, wherein: In step S2, the boundary conditions include metal-semiconductor boundary, metal-metal boundary, metal-insulator boundary, semiconductor-semiconductor boundary, semiconductor-insulator boundary, applied voltage, applied current; the material properties include doping type and concentration, defect model and its corresponding parameters, dielectric constant, mobility model and its corresponding parameters; the geometric model mesh generation control parameters include mesh element type, minimum mesh size, and mesh gradient coefficient.

4. The method for improving the design efficiency of a TFT semiconductor device according to claim 1, characterized in that: In step S3, the preliminary processing includes interference analysis, component position adjustment, characteristic parameter adjustment, and construction of a topological model based on the geometric model and calculation attributes of the TFT semiconductor device; the topological model discretizes the geometric model of the TFT semiconductor device according to the geometric model mesh generation control parameters to obtain a base mesh.

5. The method for improving the design efficiency of a TFT semiconductor device according to claim 4, characterized in that: In step S3, further optimize the base mesh, and the optimization processing includes performing regional decomposition on the base mesh to obtain multiple sub-regions, and performing discretization processing according to the characteristics of the edges on the boundaries of each sub-region.

6. The method for improving the design efficiency of a TFT semiconductor device according to claim 5, characterized in that: In step S4, the coarse mesh includes point mesh, line mesh, surface mesh, and volume mesh, which are generated respectively based on the geometric points, geometric lines, geometric surfaces in the base mesh, and the topological model.

7. The method for improving the design efficiency of a TFT semiconductor device according to claim 1, characterized in that: In step S5, the concentric shell segmentation strategy is specifically: centered on the shared vertex of the line mesh in the small angle area, construct concentric circular shells with powers of 2 as the radii as the segmentation points.

8. The method for improving the design efficiency of a TFT semiconductor device according to claim 1, characterized in that: In step S6, the simulation solver is used to perform simulation calculations on the fine mesh and output the performance parameters of the TFT semiconductor device.

9. A device for improving the design efficiency of TFT semiconductor devices, characterized in that, Using the method for improving the design efficiency of the TFT semiconductor device as described in any one of claims 1-8, including: An acquisition module for acquiring design data of a geometric model of a TFT semiconductor device, wherein the geometric model of the TFT semiconductor device includes geometric models of a plurality of device components; An assignment module for respectively assigning boundary conditions, material properties, and geometric model mesh generation control parameters to the geometric models of each of the device components; A processing module for preliminarily processing the geometric model of the TFT semiconductor device to obtain a base mesh; A coarse mesh module for generating a coarse mesh of the TFT semiconductor device according to the generated base mesh and the boundary conditions, material properties, and mesh generation control parameters of the geometric model of the TFT semiconductor device; A fine mesh module for refining the mesh by using a concentric shell segmentation strategy for regions with small angles in the coarse mesh to generate a fine mesh; A solution module for inputting the generated fine mesh into a device simulation solver for solution and adjusting the design data of the TFT semiconductor device according to the solution result.

10. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, the steps of the method for improving the design efficiency of a TFT semiconductor device according to any one of claims 1-8 are implemented.

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