Methods, apparatus, equipment, storage media, and program products for generating model files

Abstract

The application discloses a model file generation method and device, equipment, a storage medium and a program product, and relates to the technical field of etching. The model file generation method comprises the following steps: obtaining target load effect data corresponding to a plurality of target position points in a chip layout; obtaining a plurality of region ranges corresponding to each target position point according to the coordinate positions of the target position points and a range division strategy corresponding to the target etching load effect; calculating the region density of the region range corresponding to each target position point for each target position point; determining the target influence region of each target position point under the target etching load effect according to the target load effect data of each target position point and the region density of each region range corresponding to the target position point; and generating a model file corresponding to the target etching load effect according to the target influence region corresponding to each target position point.

Description

Technical Field

[0001] This application belongs to the field of etching technology, and in particular relates to a method, apparatus, device, storage medium and program product for generating model files. Background Technology

[0002] In integrated circuit manufacturing, as critical dimensions shrink, loading effects in the etching process become increasingly prevalent. Loading effects refer to the decrease in etching rate or uneven distribution of patterns under different environments due to variations in the consumption and supply of etching gases. If loading effects in the etching process are not properly addressed, they can severely impact the etching quality of the patterns.

[0003] Existing methods mainly use optical proximity correction, employing two approaches—enlarging and shrinking the pattern size—to compensate for etching.

[0004] However, this method can only address the aspect ratio effect in the loading effect, without considering the influence of long-range or short-range etching loading effects, resulting in poor etching quality. Summary of the Invention

[0005] This application provides a method, apparatus, device, storage medium, and program product for generating model files, which can improve the etching quality in etching processes.

[0006] One aspect of this application provides a method for generating a model file, including:

[0007] Obtain target load effect data corresponding to multiple target locations in the chip layout. The multiple target locations are locations that can measure the target etching load effect. The target etching load effect includes at least one of long-range etching load effect and short-range etching load effect.

[0008] Based on the coordinates of each target location and the range division strategy corresponding to the target etching load effect, multiple region ranges corresponding to each target location are obtained respectively.

[0009] For each target location point, the region density corresponding to the target location point is calculated. The region density is used to characterize the proportion of the area occupied by the etched area within the region.

[0010] Based on the target load effect data of each target location point and the corresponding regional density of each region, the target influence area of ​​each target location point affected by the target etching load effect is determined. The target influence area is the region range whose regional density meets the preset fitting conditions.

[0011] Based on the target influence area corresponding to each target location point, a model file corresponding to the target etching load effect is generated. The etching load deviation of each chip layout is detected based on the model file. The etching load deviation is the deviation caused by the target etching load effect.

[0012] One aspect of this application provides a model file generation apparatus, comprising:

[0013] The data acquisition module is used to acquire target load effect data corresponding to multiple target location points in the chip layout. The multiple target location points are location points that can measure the target etching load effect. The target etching load effect includes at least one of long-range etching load effect and short-range etching load effect.

[0014] The region division module is used to obtain multiple region ranges corresponding to each target location point based on the coordinate position of each target location point and the range division strategy corresponding to the target etching load effect.

[0015] The density calculation module is used to calculate the regional density of the area corresponding to each target location point. The regional density is used to characterize the proportion of the area occupied by the etched area within the region.

[0016] The region determination module is used to determine the target influence region of each target location point affected by the target etching load effect based on the target load effect data of each target location point and the corresponding region density of each region. The target influence region is the region range whose region density meets the preset fitting conditions.

[0017] The file generation module is used to generate a model file corresponding to the target etching load effect based on the target influence area corresponding to each target location point. The etching load deviation of each chip layout is detected based on the model file. The etching load deviation is the deviation caused by the target etching load effect.

[0018] In one aspect of this application, an electronic device is provided, the device including: a memory and a program or instructions stored in the memory and executable on a processor, wherein when the program or instructions are executed by the processor, they implement the model file generation method provided in any aspect of the above-described embodiments of this application.

[0019] One aspect of this application provides a readable storage medium storing a program or instructions, which, when executed by a processor, implements the model file generation method provided in any aspect of the above-described embodiments of this application.

[0020] In one aspect of the embodiments of this application, a computer program product is provided, wherein when the instructions in the computer program product are executed by the processor of an electronic device, the electronic device performs a model file generation method as provided in any aspect of the embodiments of this application described above.

[0021] In the model file generation method provided in this application embodiment, multiple target locations on the chip layout are selected based on the target etching load effect, and the region density of multiple regions corresponding to each target location is calculated. Then, based on the target load effect data of each target location and the region density of each region corresponding to each target location, the target influence region most significantly affected by the target etching load effect is determined for each target location. Finally, a model file corresponding to the target etching load effect is generated based on the target influence region corresponding to each target location. Thus, the model file finally obtained in this application embodiment records the target influence region most significantly affected by the target etching load effect for each target location. Based on the model file, the preset model can be optimally configured, thereby enabling the preset model to accurately detect etching load deviations caused by the target etching load effect on the chip layout. This can solve the problems of long-range and short-range etching load effects in the etching process and improve the etching quality in the etching process. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating a method for generating model files according to an embodiment of this application;

[0024] Figure 2 This is a flowchart illustrating a method for generating model files according to another embodiment of this application;

[0025] Figure 3 This is a schematic diagram of the region corresponding to the target location point under the long-range etching load effect provided in one embodiment of this application;

[0026] Figure 4 This is a schematic diagram of the target location of the long-range etching load effect provided in one embodiment of this application;

[0027] Figure 5 This is a schematic diagram of the target location of the short-range etching load effect provided in one embodiment of this application;

[0028] Figure 6 This is a schematic diagram of the structure of a model file generation apparatus provided in one embodiment of this application;

[0029] Figure 7 This is a schematic diagram of the structure of a model file generation device provided in one embodiment of this application. Detailed Implementation

[0030] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0032] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations.

[0033] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0034] Existing methods primarily compensate for etching by optical proximity correction, using either increasing or decreasing the pattern size. However, this method only addresses the aspect ratio effect within the loading effect, failing to consider the influence of long-range or short-range etching loading effects, resulting in poor etching quality.

[0035] The purpose of this application is to provide a method, apparatus, device, storage medium, and program product for generating model files. In the model file generation method provided in this application, multiple target locations on the chip layout are selected based on the target etching load effect, and the region density of multiple areas corresponding to each target location is calculated. Then, based on the target load effect data of each target location and the region density of each area corresponding to each target location, the target influence area most significantly affected by the target etching load effect is determined for each target location. Finally, a model file corresponding to the target etching load effect is generated based on the target influence area corresponding to each target location. Thus, the final model file obtained in this application records the target influence area most significantly affected by the target etching load effect for each target location. Based on the model file, a preset model can be optimally configured, enabling the preset model to accurately detect etching load deviations caused by the target etching load effect on the chip layout. This solves the problems of long-range and short-range etching load effects in the etching process, improving the etching quality.

[0036] The following describes specific embodiments of the model file generation method, apparatus, device, storage medium, and program product provided in this application. The model file generation method will be described first.

[0037] Figure 1 A flowchart illustrating a method for generating model files is provided. This method can be applied to a server and may include steps S101 to S105.

[0038] S101, acquire target load effect data corresponding to multiple target locations in the chip layout. The multiple target locations are locations that can measure the target etching load effect. The target etching load effect includes at least one of long-range etching load effect and short-range etching load effect.

[0039] In this embodiment, the target location point is a location point determined based on the target etching load effect that can be used to measure the target etching load effect.

[0040] The target etching load effect refers to the effect that the etching rate is different or the etching distribution is uneven at different locations on the chip layout due to the difference in the consumption and supply of etching gas.

[0041] In this context, the long-range etching load effect refers to the macroscopic effect where the etching rate gradually decreases as the area to be etched increases. The short-range etching load effect refers to the localized effect where the etching rate is slower in areas with dense etching patterns and faster in areas with sparse patterns. For example, when the target etching load effect is a long-range effect, it is necessary to reflect the relationship between etching rate and etching area on a macroscopic scale. Therefore, feature points within each cell of the chip layout can be selected as target locations. Conversely, when the target etching load effect is a short-range effect, it is necessary to reflect the relationship between etching rate and etching area on a microscopic scale. Therefore, multiple feature points within specific cells of the chip layout can be selected as target locations.

[0042] Target loading effect data is used to characterize and reflect the specific situation of the target etching loading effect. For example, target loading effect data can be the etching depth at each target location point.

[0043] As an example, when the target etching load effect is a long-range etching load effect, the server selects feature points as target location points from each cell in the chip layout and obtains the etching depth of each target location point.

[0044] S102, based on the coordinates of each target location and the range division strategy corresponding to the target etching load effect, obtain multiple region ranges corresponding to each target location.

[0045] In this embodiment, the range division strategy is used to characterize the strategy for dividing the area range where the target location point is located.

[0046] For example, when the target etching load effect is a long-range etching load effect, the range division strategy can be to set the initial length to 10µm and increase it in increments of 5µm until 10 regions are obtained. These regions can be rectangular or circular.

[0047] As an example, the server uses the target location's coordinates as the center and then divides the area into a rectangle with sides of 10µm to obtain the first region corresponding to the target location. Then, it increases the step size by 15µm to obtain the second region corresponding to the target location. This process is repeated, increasing the step size multiple times, until ten regions corresponding to the target location are obtained.

[0048] S103, For each target location point, calculate the region density of the area corresponding to the target location point. The region density is used to characterize the proportion of the area occupied by the etched area within the region.

[0049] In this embodiment, the region density is the ratio of the area occupied by the etched region within the region to the total area within the region.

[0050] As an example, for each region corresponding to a target location, the server uses image processing techniques (such as edge detection or morphological operations) to identify the etched areas within that region. It then calculates the ratio of the etched area's area to the total area within that region, thus obtaining the region density for each region.

[0051] S104. Based on the target load effect data of each target location point and the corresponding regional density of each region, determine the target influence area of ​​each target location point affected by the target etching load effect. The target influence area is the region range whose regional density meets the preset fitting conditions.

[0052] In this embodiment, the target influence region is used to characterize the region within each area of ​​the target location point that has a significant impact on the target etching load effect of the target location point.

[0053] Preset fitting conditions are used to filter the target influence region. For example, the preset fitting condition can be a pre-set density threshold.

[0054] As an example, the server pre-sets a density threshold and then compares the density of each region with the density threshold. If the density of a region exceeds the density threshold, it is considered that the region has a significant impact on the target etching load effect at the target location point, and this region is then determined as the target area affected by the target etching load effect at the target location point.

[0055] S105, Based on the target influence area corresponding to each target location point, generate a model file corresponding to the target etching load effect, so as to detect the etching load deviation of each chip layout according to the model file. The etching load deviation is the deviation caused by the target etching load effect.

[0056] In this embodiment, the model file may include the coordinates of the target location point and the target influence area corresponding to the target location point.

[0057] As an example, the server integrates information on the target influence areas corresponding to each target location point to generate a model file corresponding to the target etching load effect. This model file is then integrated into an EDA tool or a pre-defined model. Based on the target influence areas of each target location point in the model file, the EDA tool or pre-defined model can then detect the target etching load effect on each chip layout during the full chip design process.

[0058] As another example, such as Figure 2 The diagram illustrates another method for generating model files. The target etching load effect includes long-range etching load effect and short-range etching load effect. The server first collects long-range etching load effect data via S201, then calculates the density of different ranges at the target location points corresponding to the long-range etching load effect via S202. Next, it collects short-range etching load effect data via S203, and then calculates the density of different ranges at the target location points corresponding to the short-range etching load effect via S204. Then, via S205, it fits the different range densities corresponding to the long-range and short-range etching load effects respectively. Finally, via S206, it determines the region with the smallest fitting error as the target influence region, and generates the model file based on the target influence region.

[0059] In the model file generation method provided in this embodiment, multiple target locations on the chip layout are selected based on the target etching load effect, and the region density of multiple areas corresponding to each target location is calculated. Then, based on the target load effect data of each target location and the region density of each area corresponding to each target location, the target influence area most significantly affected by the target etching load effect is determined for each target location. Finally, a model file corresponding to the target etching load effect is generated based on the target influence area corresponding to each target location. Thus, the model file obtained in this embodiment records the target influence area most significantly affected by the target etching load effect for each target location. Based on the model file, the preset model can be optimally configured, thereby enabling the preset model to accurately detect etching load deviations caused by the target etching load effect on the chip layout. This can solve the problems of long-range and short-range etching load effects in the etching process and improve the etching quality.

[0060] As an optional embodiment, the range partitioning strategy includes a minimum partition length, a maximum partition length, and an interval step size;

[0061] S102 may specifically include:

[0062] Obtain the minimum partition length, maximum partition length, and interval step size corresponding to the target etching load effect;

[0063] Starting from the minimum division length, the interval step size is increased sequentially until the maximum division length is reached, thus obtaining multiple division lengths corresponding to the target location point;

[0064] For each target location point, the following steps are performed: using the coordinates of the target location point as the center, and according to the division length, multiple regions corresponding to the target location point are obtained.

[0065] In this embodiment, the range partitioning strategy is matched with the target etching load effect. For example, when the target etching load effect is a long-range etching load effect, the corresponding range partitioning strategy can be: a minimum partition length of 50µm, a maximum partition length of 100µm, and an interval step size of 5µm; when the target etching load effect is a short-range etching load effect, the corresponding range partitioning strategy can be: a minimum partition length of 1µm, a maximum partition length of 30µm, and an interval step size of 1.5µm.

[0066] For example, such as Figure 3 As shown, a schematic diagram of the region corresponding to the target location point under long-range etching load effect is provided. The region corresponding to the target location point is a circular area. Specifically, a small circle 310 with the target location point as the center and a radius of 50 μm is constructed as the smallest region; a large circle 320 with the target location point as the center and a radius of 100 μm is constructed as the largest region. Then, between the small circle 310 and the large circle 320, multiple circles are further divided according to the interval step size, thus obtaining multiple region ranges corresponding to the target location point under long-range etching load effect.

[0067] As an example, the server first obtains the coordinates of the target location point, as well as the minimum partition length, maximum partition length, and interval step size corresponding to the target etching load effect.

[0068] Then, the segment length sequence corresponding to the target location point is calculated. Specifically, starting from the minimum segment length, the interval step is increased by one step each time until the maximum segment length is reached, thus obtaining multiple segment lengths corresponding to the target location point, which constitute the segment length sequence.

[0069] Then, for each division length in the division length sequence, a square or circular region is divided with the target location point as the center as the region range corresponding to the target location point.

[0070] Specifically, in the case of a circular region, the region is divided using the dividing length as the radius, thus obtaining the region range corresponding to the target location point.

[0071] In the case of a square region, subtract half the division length from the x-coordinate of the target location point and add half the division length to the y-coordinate to obtain the top-left vertex of the square region; add half the division length to the x-coordinate of the target location point and add half the division length to the y-coordinate to obtain the top-right vertex of the square region; add half the division length to the x-coordinate of the target location point and subtract half the division length to obtain the bottom-right vertex of the square region; subtract half the division length to the x-coordinate of the target location point and subtract half the division length to obtain the bottom-left vertex of the square region. This gives the range of the region corresponding to the target location point.

[0072] Table 1 below provides a schematic table of different region ranges and corresponding densities corresponding to target locations. The first column represents the serial number of the target location, the second column represents the X-axis coordinate of the target location, the third column represents the Y-axis coordinate of the target location, the fourth column represents the critical dimension of the target location, the sixth column represents the target etching load effect type of the target location, the seventh column represents the etching load deviation of the target location, the eighth column represents the region range of the target location, and the ninth column represents the density of the region range of the target location.

[0073] Table 1. Schematic diagram of different area ranges and corresponding densities corresponding to target locations.

[0074]

[0075] This embodiment systematically divides multiple regions based on the coordinates of the target location and the range division strategy corresponding to the target etching load effect. This facilitates subsequent optimization analysis of the target etching load effect, thereby further improving the etching quality in the etching process.

[0076] As an optional embodiment, S104 may specifically include:

[0077] For each target location, perform the following steps:

[0078] Arbitrarily select a number of target regions from the regions corresponding to the target location points to form a fitting region group, where the number of targets corresponds to the target etching load effect;

[0079] For each fitting region group corresponding to the target location point, the region density of each region range in the fitting region group is fitted to obtain the fitted load effect data.

[0080] Based on the fitted load effect data and the target load effect data at the target location point, the fitting error of each fitted region group is obtained;

[0081] The region range in the fitting region group with the smallest fitting error is determined as the target influence region where the target location point is affected by the target etching load effect.

[0082] In this embodiment, based on the complexity of the etching load effect and the process accuracy requirements, it is necessary to select an appropriate number of regions from each region for fitting, and the number of fitting regions is the predetermined target number.

[0083] The number of targets corresponds to the target etching load effect. Considering that the etching area of ​​a long-range etching load effect is larger than that of a short-range etching load effect, its fitting complexity is higher. To ensure fitting efficiency, the number of targets for the long-range etching load effect can be smaller than the number of targets corresponding to the short-range etching load effect. For example, when the target etching load effect is a long-range etching load effect, the number of targets can be 3; when the target etching load effect is a short-range etching load effect, the number of targets can be 5.

[0084] As an example, when the target etching load effect is a long-range etching load effect, for each target location point, the server randomly selects three regions from all corresponding regions or selects them according to a preset selection strategy (e.g., selecting based on the size of the region range) to form a fitting region group, until all combinations are traversed to obtain multiple fitting region groups corresponding to the target location point.

[0085] Then, for each fitted region group, based on the region density of each region within the fitted region group, statistical methods (such as linear regression or multinomial regression) are used to fit the relationship between region density and the target etching load effect, obtaining fitted load effect data. These data reflect the predicted etching load effect under the current fitted region group configuration.

[0086] Then, for each fitted region group, the fitted load effect data obtained from its fitting is compared with the target load effect data of the target location point, and the fitting error corresponding to the fitted region group is calculated.

[0087] Finally, the fitting errors of all fitted region groups are compared, and the group with the smallest fitting error is selected as the optimal fitted region group. The region within this group is defined as the target area affected by the target etching load effect at the target location point. These regions will receive special attention in subsequent process control to ensure the accuracy of the etching process.

[0088] In this embodiment, based on the target load effect data of the target location point and the corresponding regional density of each area, the target influence area of ​​the target location point under the target etching load effect is determined. Thus, through density fitting, the optimal influence area of ​​the target location point under the target etching load effect is obtained, which helps in the subsequent generation of the model file corresponding to the target etching load effect. Based on the model file, the etching load deviation caused by the target etching load effect can be accurately detected, thereby improving the etching quality in the etching process.

[0089] As an optional embodiment, S103 may specifically include:

[0090] For each area of ​​each target location, perform the following operations:

[0091] Obtain the area of ​​the region and the etching area of ​​the etched region within the region;

[0092] Divide the etched area by the area of ​​the region to obtain the region density.

[0093] In this embodiment, when the area is a square area, the server calculates the area using the side length of the area; when the area is a circular area, the server calculates the area using the radius of the area.

[0094] Then, the server identifies the etched areas within the region and calculates the etched area within the region.

[0095] Finally, by dividing the etched area within the region by the area of ​​the region, the region density within the region can be obtained.

[0096] In this embodiment, the regional density of the region is calculated based on the area of ​​the region and the etching area. This helps to subsequently determine the optimal region affected by the target etching load effect at the target location point through density fitting, thereby improving the etching quality in the etching process.

[0097] As an optional embodiment, the target load effect data includes critical dimensions and etching load deviation;

[0098] S101 may specifically include:

[0099] Obtain the key dimensions corresponding to each of the multiple target locations in the chip layout;

[0100] The etching load deviation of each target location point is obtained by subtracting the critical dimension from the reference dimension corresponding to the target etching load effect.

[0101] In this embodiment, the reference size is a target size value set according to the performance requirements and process capabilities of the chip design. For example, the reference size can be a preset value.

[0102] As an example, the server can use high-precision measurement tools such as scanning electron microscope (SEM), atomic force microscope (AFM) or optical critical dimension measuring instrument (OCD) to accurately measure the target location points on the chip layout, thereby obtaining the critical dimensions corresponding to the target location points.

[0103] Then, for each target location, its measured critical dimension is compared with the reference dimension, and the difference is calculated as the etching load deviation for that target location.

[0104] This embodiment enables precise measurement of critical dimensions at multiple target locations in the chip layout and effective evaluation of etching load deviations, thereby providing strong support for subsequent optimization analysis of target etching load effects and further improving etching quality in the etching process.

[0105] As an optional embodiment, when the target etching load effect is a long-range etching load effect, the target location point is the feature location point of the first grid in different cells of the chip layout, each first grid corresponds to the same position of the cell, and the reference size is the critical size of the first grid of the central cell of the chip layout.

[0106] When the target etching load effect is a short-range etching load effect, the target location point is the feature location point of the second grid within the same cell of the chip layout. Each second grid corresponds to a different position in the cell, and the reference size is the critical size of the central grid within the cell of the chip layout.

[0107] In this embodiment, when the target etching load effect is a long-range etching load effect, it is necessary to reflect the change law between etching speed and etching area in the macroscopic range. That is, the target location point must cover the entire chip layout to reflect the macroscopic law.

[0108] Therefore, the target location point at this time is the characteristic location point of the first grid in different cells of the chip layout, and each first grid corresponds to the same position in the cell. For example, the target location point can be the center point of the center grid of each cell, and the reference size is the critical size of the center grid position of the center cell of the chip layout.

[0109] As an example, such as Figure 4 As shown, a schematic diagram of the target location point for a long-range etching load effect is provided. The chip layout includes nine cells: m1, m2, m3, m4, m5, m6, m7, m8, and m9. The center point of the central grid of each cell is selected as the target location point.

[0110] When the target etching load effect is a short-range etching load effect, what needs to be reflected is the change law between etching rate and etching area in the microscopic range. That is, the target location point must cover all positions in the cell of the chip layout to reflect the microscopic law.

[0111] Therefore, the target location point at this time is the characteristic location point of the second grid within the same cell of the chip layout, and each second grid corresponds to a different position within the cell. For example, the target location point can be the center point of each corresponding grid on the target line segment within the cell, and the reference dimension is the critical dimension of the center grid position within the cell. Here, the target line segment is the line connecting any vertex within a cell of the chip layout to the center point.

[0112] As an example, such as Figure 5 As shown, a schematic diagram of the target location point for a short-range etching load effect is provided. The target location point is selected as the center point of each grid on the line connecting the lower left vertex to the center point within the cell.

[0113] This embodiment accurately obtains the target location point and reference size corresponding to the target etching load effect, thereby providing strong support for subsequent optimization analysis of the target etching load effect and further improving the etching quality in the etching process.

[0114] A method for generating model files. Accordingly, this application also provides specific embodiments of a model file generation apparatus.

[0115] like Figure 6 As shown, the model file generation device 600 provided in this application embodiment includes a data acquisition module 610, a region division module 620, a density calculation module 630, a region determination module 640, and a file generation module 650.

[0116] The data acquisition module 610 is used to acquire target load effect data corresponding to multiple target location points in the chip layout. The multiple target location points are location points that can measure the target etching load effect. The target etching load effect includes at least one of long-range etching load effect and short-range etching load effect.

[0117] The region division module 620 is used to obtain multiple region ranges corresponding to each target location point based on the coordinate position of each target location point and the range division strategy corresponding to the target etching load effect.

[0118] The density calculation module 630 is used to calculate the regional density of the area corresponding to each target location point. The regional density is used to characterize the proportion of the area occupied by the etched area within the region.

[0119] The region determination module 640 is used to determine the target influence region of each target location point affected by the target etching load effect based on the target load effect data of each target location point and the corresponding region density of each region. The target influence region is the region range whose region density meets the preset fitting conditions.

[0120] The file generation module 650 is used to generate a model file corresponding to the target etching load effect based on the target influence area corresponding to each target location point, so as to detect the etching load deviation of each chip layout based on the model file. The etching load deviation is the deviation caused by the target etching load effect.

[0121] As an optional embodiment, the range partitioning strategy includes a minimum partition length, a maximum partition length, and an interval step size;

[0122] The region division module 620 specifically includes the following units:

[0123] The information acquisition unit is used to acquire the minimum partition length, maximum partition length, and interval step size corresponding to the target etching load effect.

[0124] The length determination unit is used to start from the minimum division length and increase the interval step size sequentially until the maximum division length is reached, so as to obtain multiple division lengths corresponding to the target position point;

[0125] The range division unit is used to perform the following for each target location point: taking the coordinate position of the target location point as the center, and dividing it into multiple regions corresponding to the target location point according to the division length.

[0126] As an optional embodiment, the region determination module 640 specifically includes the following units:

[0127] The region group is a unit used to select any number of target regions from the regions corresponding to the target location point to form a fitting region group. The number of targets corresponds to the target etching load effect.

[0128] The density fitting unit is used to fit the density of each region in the fitting region group corresponding to the target location point to obtain the fitted load effect data.

[0129] The error determination unit is used to obtain the fitting error of each fitting region group based on the fitted load effect data and the target load effect data of the target location point.

[0130] The region determination unit is used to determine the region range in the fitting region group with the smallest fitting error as the target influence region affected by the target etching load effect at the target location point.

[0131] As an optional embodiment, the density calculation module 630 specifically includes the following units:

[0132] The area acquisition unit is used to acquire the area of ​​the region and the etching area of ​​the etched region within the region.

[0133] The density determination unit is used to divide the etched area by the area of ​​the region to obtain the region density.

[0134] As an optional embodiment, the target load effect data includes critical dimensions and etching load deviation;

[0135] The data acquisition module 610 specifically includes the following units:

[0136] The dimension acquisition unit is used to acquire the key dimensions corresponding to multiple target locations in the chip layout.

[0137] The deviation determination unit is used to subtract the critical dimension of each target location point from the reference dimension corresponding to the target etching load effect to obtain the etching load deviation of each target location point.

[0138] A method for generating model files. Accordingly, this application also provides specific embodiments of a device for generating model files.

[0139] Figure 7 A schematic diagram of the hardware structure of the model file generation device provided in the embodiments of this application is shown.

[0140] The device for generating model files may include a processor 701 and a memory 702 storing computer program instructions.

[0141] Specifically, the processor 701 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0142] Memory 702 may include mass storage for data or instructions. For example, and not limitingly, memory 702 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 702 may include removable or non-removable (or fixed) media. Where appropriate, memory 702 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 702 is non-volatile solid-state memory.

[0143] The processor 701 reads and executes computer program instructions stored in the memory 702 to implement any of the model file generation methods in the above embodiments.

[0144] In one example, the device for generating the model file may further include a communication interface 703 and a bus 710. For example, Figure 7 As shown, the processor 701, memory 702, and communication interface 703 are connected through bus 710 and complete communication with each other.

[0145] The communication interface 703 is mainly used to realize communication between various modules, devices, layout units and / or equipment in the embodiments of this application.

[0146] Bus 710 includes hardware, software, or both, that couples components of the device used to generate the model file together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 710 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0147] Furthermore, in conjunction with the model file generation methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. This computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the model file generation methods in the above embodiments.

[0148] In addition, in conjunction with the model file generation method in the above embodiments, this application embodiment can provide a computer program product for implementation. When the instructions in the computer program product are executed by the processor of an electronic device, the electronic device executes the model file generation method provided by any aspect of the above embodiments of this application.

[0149] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0150] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0151] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0152] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0153] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and layout units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method of generating a model file, characterized by, The method comprises the following steps: obtaining target load effect data corresponding to each of a plurality of target position points in a chip layout, the plurality of target position points being position points capable of measuring target etching load effects, the target etching load effects including at least one of long-range etching load effects and short-range etching load effects, in the case of the target etching load effects being long-range etching load effects, the target position points being feature position points of first grids in different cells of the chip layout, each of the first grids corresponding to the same position of a cell, in the case of the target etching load effects being short-range etching load effects, the target position points being feature position points of second grids in the same cell of the chip layout, each of the second grids corresponding to a different position of a cell; obtaining a plurality of region ranges corresponding to each of the target position points according to the coordinate positions of the target position points and a range division strategy corresponding to the target etching load effects; calculating a region density of the region range corresponding to each of the target position points, the region density being used to represent the proportion of the area occupied by the etching region in the region range; determining a target influence region of each of the target position points under the target etching load effects according to the target load effect data of each of the target position points and the region density of the region range corresponding to each of the target position points, the target influence region being a region range in which the region density meets a preset fitting condition; generating a model file corresponding to the target etching load effects according to the target influence region corresponding to each of the target position points, so as to detect etching load deviations of each of the chip layouts according to the model file, the etching load deviations being deviations caused by the target etching load effects.

2. The method of claim 1, wherein, The range division strategy includes a minimum division length, a maximum division length, and an interval step; The method of obtaining a plurality of region ranges corresponding to each of the target position points according to the coordinate positions of the target position points and a range division strategy corresponding to the target etching load effects comprises the following steps: obtaining the minimum division length, the maximum division length, and the interval step corresponding to the target etching load effects; starting from the minimum division length, sequentially increasing the interval step until the maximum division length is reached, to obtain a plurality of division lengths corresponding to the target position points; for each of the target position points, performing the following steps: taking the coordinate position of the target position point as the center, dividing a plurality of region ranges corresponding to the target position point according to each of the division lengths.

3. The method of claim 1, wherein, The method of determining a target influence region of each of the target position points under the target etching load effects according to the target load effect data of each of the target position points and the region density of the region range corresponding to each of the target position points comprises the following steps: for each of the target position points, performing the following steps: selecting a target number of region ranges from the region ranges corresponding to the target position point to form a fitting region group, the target number corresponding to the target etching load effects; fitting error of each of the fitting region groups is obtained according to each of the fitting load effect data and the target load effect data of the target position point; the region range in the fitting region group with the minimum fitting error is determined as a target influence region of the target position point under the target etching load effect. The method further includes the following steps:

4. The method of claim 1, wherein, The method further includes the following steps: The target load effect data includes a critical dimension and an etching load deviation; The method further includes the following steps: The target load effect data includes a critical dimension and an etching load deviation; 5. The method according to any one of claims 1 to 4, characterized in that, The method further includes the following steps: In a case where the target etching load effect is a long-range etching load effect, the reference dimension is a critical dimension of a first grid of a center cell of the chip layout; In a case where the target etching load effect is a short-range etching load effect, the reference dimension is a critical dimension of a center grid within a cell of the chip layout. The method further includes the following steps:

6. The method of claim 5, wherein, The data acquisition module is configured to acquire target load effect data corresponding to a plurality of target position points in a chip layout, the plurality of target position points being position points capable of measuring a target etching load effect, the target etching load effect including at least one of a long-range etching load effect and a short-range etching load effect, in a case where the target etching load effect is a long-range etching load effect, the target position points being feature position points of first grids in different cells of the chip layout, each of the first grids corresponding to a same position of a cell, in a case where the target etching load effect is a short-range etching load effect, the target position points being feature position points of second grids in a same cell of the chip layout, each of the second grids corresponding to a different position of the cell; The region division module is configured to obtain, according to coordinate positions of each of the target position points and a range division strategy corresponding to the target etching load effect, a plurality of region ranges corresponding to each of the target position points respectively; 7. An apparatus for generating a model file, characterized by comprising: The density calculation module is configured to calculate, for each of the target position points, a region density of the region range corresponding to the target position point, the region density being used to represent a proportion of an area of an etching region in the region range. ​ ​ ​ A region determining module is configured to determine a target influence region of each target position point under the target etching load effect according to the target load effect data of each target position point and a region density of a corresponding region range, the target influence region being a region range in which the region density meets a preset fitting condition; A file generating module is configured to generate a model file corresponding to the target etching load effect according to the target influence region corresponding to each target position point, so as to detect an etching load deviation of each chip layout according to the model file, the etching load deviation being a deviation caused by the target etching load effect.

8. An electronic device, comprising: The device comprises a processor and a memory storing computer program instructions; The processor executes the computer program instructions to implement the model file generation method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer program instructions, and the computer program instructions are executed by the processor to implement the model file generation method according to any one of claims 1-6.

10. A computer program product, characterised in that, The instructions in the computer program product are executed by the processor of the electronic device to enable the electronic device to implement the model file generation method according to any one of claims 1-6.

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