STT-MRAM-based storage calculation circuit and implementation method

Abstract

The embodiment of the invention provides a STT-MRAM-based storage calculation circuit and an implementation method, and the circuit comprises a 2T2M storage array which comprises a gate circuit and an STT-MARM device which are electrically connected; the read-write control circuit is connected with the 2T2M storage array; the WL driver module is connected with the 2T2M storage array; the ECC circuit is connected with the 2T2M storage array; the ADC module is connected with the 2T2M storage array; the logic control module is connected with the read-write control circuit, the buffer and counter module and the WL driver module; the Adder module is connected with the ADC module; the buffer and counter module is connected with the WL driver module; the Timer module is connected with the buffer and counter module, the WL driver module, the ADC module and the Adder module; and the buffer module is connected with the ADC module and the Adder module.

Description

Technical Field

[0001] This document relates to the field of electrical technology, and in particular to a storage computing circuit based on STT-MRAM and an implementation method. Background Art

[0002] In the traditional von Neumann architecture, system data needs to be repeatedly transferred between the storage unit and the processing unit to realize the computing process. Due to the long-term mismatch between the development speed of processors and memory devices, the current memory access capability lags far behind the computing speed of processors. In large-scale computing systems, the "storage wall" problem caused by the communication bandwidth and latency of the memory itself has become a key bottleneck restricting the further improvement of system computing performance.

[0003] With the continuous development of AloT technology, in order to cope with the high power consumption and huge time overhead brought by large-scale network computing and massive data processing in this process, further improve computing throughput, and break the "storage wall", the Compute-in-Memory (CIM) solution based on memory units has gradually attracted the attention of academia and industry. As a new computing architecture that integrates storage and computing functions on one end, CIM is of great significance to reducing the latency and power consumption of data transmission and access, and improving the overall energy efficiency and performance of the system. High-performance CIM solutions have broad prospects for promoting the deployment and training reasoning of advanced ultra-large-scale artificial intelligence models and promoting the implementation of AI chip products.

[0004] Considerations of computing power and power consumption have driven the mapping of CIM solutions on non-volatile memory (NVM). Many new memories (ReRAM, FeRAM, PRAM and MRAM) have shown their potential for application in this field. As a new type of NVM, magnetic random access memory (MRAM) is becoming a favorable competitor for the next generation of IMC computing units with its excellent retention characteristics, high integration and low energy consumption. Limited by the process and design level, in-memory computing based on MRAM is still in its infancy. Therefore, a reliable and effective in-memory computing circuit based on STT-MRAM is urgently needed.

[0005] In the prior art, an in-memory computing circuit based on MRAM and a control method thereof are provided. It uses 2T2M (2Transistor 2MTJ) as a basic unit, sets a reference unit in a fixed configuration mode and compares the resistance difference between them through a sense amplifier (SA), thereby constructing different logical relationships for logical calculation. The prior art also provides an in-memory binary neural network computing circuit based on MRAM, which uses 4T2M as a basic computing unit. Binary weight calculation is performed between units using XNOR logic, and the current-type SA and accumulator at the output end are used to repeat the operation row by row to complete the training of the binary network. At the same time, based on specific bit alignment rules, the architecture can also complete convolution operations under a single time step. The above in-memory computing solution based on STT-MRAM can carry part of the hardware mapping acceleration process in specific neural network calculations, but the digital computing process design based on SA will bring serious area loss and pose challenges to the timing control of array units. Summary of the invention

[0006] The purpose of the present invention is to provide a storage computing circuit based on STT-MRAM and an implementation method thereof, aiming to solve the above-mentioned problems in the prior art.

[0007] The present invention provides a storage computing circuit based on STT-MRAM, comprising:

[0008] A 2T2M storage array, comprising a plurality of electrically connected gate circuits and STT-MARM devices, for applying sufficiently large currents in different directions to the STT-MARM devices through the gate circuits, and performing high-resistance and low-resistance writes to the STT-MARM devices;

[0009] A read and write control circuit, connected to the 2T2M storage array, for controlling the read and write data operations of the 2T2M storage array;

[0010] A WL driver module, connected to the 2T2M storage array, and used to select the gate circuit at the corresponding position of the 2T2M storage array through a conduction voltage;

[0011] An ECC circuit, connected to the 2T2M storage array, for performing error correction on the 2T2M storage array;

[0012] An ADC module, connected to the 2T2M storage array, obtains current from the 2T2M storage array in columns, converts the current into data, and sends it to the Adder module;

[0013] A logic control module, connected to the read-write control circuit, the buffer and counter module, and the WL driver module, and used to send a logic control signal, and perform logic control on the read-write control circuit, the buffer and counter module, and the WL driver module through the logic control signal to achieve data writing and reading;

[0014] An Adder module, connected to the ADC module, is used to calculate the data received from the ADC module to obtain a calculation result;

[0015] A buffer and counter module is connected to the WL driver module and is used to store instruction data in a time sequence and send the instruction data to the WL driver module under the control of the logic control module, wherein the instruction data is used to control the WL driver module to conduct the gate array;

[0016] A Timer module, connected to the buffer and counter module, the WL driver module, the ADC module, and the Adder module, for providing a timing signal;

[0017] The buffer module is connected to the ADC module and the Adder module, and is used to store the intermediate data and calculation results generated when the ADC module and the Adder module perform data calculation.

[0018] The present invention provides a method for implementing storage calculation based on STT-MRAM. Based on the above-mentioned storage calculation circuit based on STT-MRAM, the above-mentioned method specifically includes:

[0019] Data is written in rows as basic units. The corresponding LSL / RSL and BL are controlled by the read-write control circuit, and appropriate voltage signals are applied. The corresponding WL / WLb is controlled by the WL driver module to select the gate circuit to realize data storage.

[0020] By adopting the embodiment of the present invention, Bitcell is constructed using complementary MRAM, and a simulated neural network training calculation process is completed based on XNOR logic with columns as calculation units, which simplifies the data writing and logic calculation process, making it more suitable for binary or ternary neural network mapping, thereby achieving a calculation process with higher calculation accuracy and lower power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0022] Figure 1 is a schematic diagram of a storage computing circuit based on STT-MRAM according to an embodiment of the present invention;

[0023] Figure 2 is a schematic structural diagram of a Bitcell unit according to an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of the structure of data writing and refreshing according to an embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of data writing and refreshing states according to an embodiment of the present invention;

[0026] Figure 5 is a structural diagram of a data reading operation according to an embodiment of the present invention;

[0027] Figure 6 is a structural diagram of a MAC operation according to an embodiment of the present invention;

[0028] Figure 7 is a schematic diagram of the state of MAC operation according to an embodiment of the present invention;

[0029] Figure 8 is a logical schematic diagram of an XNOR Bitcell according to an embodiment of the present invention;

[0030] Fig. 9 is a schematic diagram of an XNOR truth value of an embodiment of the present invention;

[0031] Fig.10 is a structural diagram of a ternary weight configuration operation according to an embodiment of the present invention;

[0032] Fig.11 is a schematic diagram of the state of an embodiment of the present invention;

[0033] Fig.12 It is a flow chart of a storage computing implementation method based on STT-MRAM according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.

[0035] Device Embodiment

[0036] According to an embodiment of the present invention, a storage computing circuit based on STT-MRAM is provided. Figure 1 is a schematic diagram of a storage computing circuit based on STT-MRAM according to an embodiment of the present invention, such as Figure 1 As shown, the storage computing circuit based on STT-MRAM according to an embodiment of the present invention specifically includes:

[0037] 2T2M storage array (corresponding to Figure 1 The MRAM Array in the invention comprises an electrically connected gate circuit and an STT-MARM device, which is used to apply a sufficiently large current in different directions to the STT-MARM device through the gate circuit, and write the STT-MARM device into a high-resistance state and a low-resistance state; the 2T2M storage array specifically comprises: a plurality of Bitcell units, 8 Bitcell units constitute 8-bit data, and data is written in a row as a basic unit, and logic calculation output is performed in a column as a basic unit, wherein each Bitcell unit comprises a first STT-MARM device M0, a first gate circuit N0, a second STT-MARM device M1 complementary to M0, and a second gate circuit N1 complementary to N0, which are connected in sequence, one end of the first STT-MARM device is connected to an LSL signal, and the other end is connected to one end of the first gate circuit, the other end of the first gate circuit is connected to a BL signal and connected to one end of the second STT-MARM device, the other end of the second STT-MARM device is connected to the second gate circuit, the other end of the second gate circuit is connected to an RSL signal, and the upper and lower ends of the first STT-MARM device are connected to a WL signal and a WLb signal respectively.

[0038] Read and write control circuit (corresponding to Figure 1 A Read / Write Driver Circuit in the memory is connected to the 2T2M memory array and is used to control the reading and writing operations of the 2T2M memory array;

[0039] WL driver module (corresponding to Figure 1WL driver in the 2T2M memory array), connected to the 2T2M memory array, and used to select the gate circuit at the corresponding position of the 2T2M memory array through the conduction voltage;

[0040] ECC circuit (corresponding to Figure 1 ECC and Reference Circuit in the 2T2M storage array), connected to the 2T2M storage array, for performing error correction on the 2T2M storage array;

[0041] ADC module (corresponding to Figure 1 SAR ADC in the 2T2M storage array), connected to the 2T2M storage array, for obtaining current from the 2T2M storage array in columns, converting the current into data, and sending it to the Adder module;

[0042] Logic control module (corresponding to Figure 1 Logic Controller in the control circuit), connected to the read-write control circuit, the buffer and the counter module, and the WL driver module, for issuing a logic control signal, and performing logic control on the read-write control circuit, the buffer and the counter module, and the WL driver module through the logic control signal to realize data writing and reading;

[0043] Adder module (corresponding to Figure 1 Shift Adder in the ADC module), connected to the ADC module, and used to calculate the data received from the ADC module to obtain a calculation result;

[0044] Buffer and counter modules (corresponding to Figure 1 Buffer and Counter in the memory array, connected to the WL driver module, used to store instruction data in time sequence, and under the control of the logic control module, send the instruction data to the WL driver module, wherein the instruction data is used to control the WL driver module to conduct the gate array; when the storage array is in calculation mode, the activation data Xin participating in the MAC sum calculation is pre-programmed and stored in the Buffer and counter in a certain order, and is input into the MRAM array through the WL Driver in a pipeline manner in parallel, and performs XOR logic calculation with the weight data pre-stored in the array. The final result is sampled and converted by the SAR-ADC in the form of column current / voltage, and shifted and summed through the Shift Adder to realize the calculation process of multi-bit data. The Logic Controller and Timer are used to give the logic control signal to realize this parallel calculation process to ensure the effectiveness and reliability of the array operation.

[0045] Timer module (corresponding to Figure 1 The Timer in the module is connected to the buffer and counter module, the WL driver module, the ADC module, and the Adder module to provide a timing signal;

[0046] Buffer module (corresponding to Figure 1 Buffer in the ADC module and the Adder module, connected to the ADC module and the Adder module, and used to store intermediate data and calculation results generated when the ADC module and the Adder module perform data calculation.

[0047] The logic control module is specifically used for:

[0048] When writing and refreshing data, the WL driver module controls WL and WLb to apply a conduction voltage to turn on the complementary unit strobes N0 and N1, and the read-write control circuit controls BL to be connected to a high level, LSL and RSL to be grounded, M0 is written to AP state and M1 is written to P state, and the Bitcell configuration is -1. The above process is performed in units of rows until all cells in the 2T2M storage array are written; in units of rows, the Bitcell in the corresponding column that needs to be written to the +1 state is selected, and WL and WLb are controlled to apply a conduction voltage to turn on the strobes, and the read-write control circuit controls BL to be grounded, LSL and RSL to be connected to a high level, M0 is written to P state and M1 is written to AP state, and the Bitcell configuration is updated to +1.

[0049] The logic control module is specifically used for:

[0050] When performing data reading operations, the read-write control circuit is controlled to switch the working mode to the read mode, BL is grounded, LSL and RSL are connected to the SA circuit, the unit to be read is selected through the WL driver module, and the turn-on voltage VWL is applied to the WL and WLb terminals to turn on N1 and N2. The resistance state of the positive and negative ports corresponding to M1 and M2 is sensed through the SA circuit. Since M1 and M2 are in a complementary state under normal circumstances, the SA circuit determines the resistance state distribution of M1 and M2 through the voltage difference generated by the positive and negative ports to realize data reading.

[0051] When performing a MAC operation, the corresponding calculation voltage is applied by the LSL and RSL terminals through the read-write control circuit, the Bitcell current is sensed at the BL terminal, and the XNOR result shown in Formula 1 is obtained, and the calculation result of the same column is summarized in the form of current to the ADC module, wherein the MAC operation is specifically a process of indirectly reading the column unit selected by the WLdriver module in a resistive state within a single time step:

[0052] Yout =∑X in ⊕W i Formula 1;

[0053] Among them, Yout represents the MAC summation result, which is output in the form of the current at the unit BL end; Xin represents input activation, which is configured by the level combination of the two MOS tube gate input lines WL and WLb of the 2T2M unit; Wi represents the storage weight, which is configured by the storage resistance state combination of the two MTJ units of the 2T2M unit.

[0054] When performing the ternary weight configuration operation, the WL driver module controls WL and WLb to turn on N0 and turn off N1, connects the write voltage to the BL terminal, controls LSL and RSL to be grounded through the read-write control circuit, and writes "AP" state to M0; the WL driver module controls WL and WLb to turn on N1 and turn off N0, connects the write voltage to the RSL terminal, controls LSL and BL to be grounded through the read-write control circuit, and writes "AP" state to M1.

[0055] The above technical solution of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings.

[0056] like Figure 1 As shown, the embodiment of the present invention uses a STT-MARM device structure with perpendicular magnetic anisotropy (PMA) as the core component, and cooperates with the gate circuit made by CMOS process to form a storage array with 2T2M (2Transistor 2MTJ) as the basic unit. A single MTJ device has two configurations: high resistance AP and low resistance P. Figure 2 As shown, by applying sufficiently large currents in different directions between SL and BL, the AP and P resistance states of the MTJ device can be written. The overall CIM architecture consists of MRAMArray, R&D driver circuits for data writing, WL driver for gating the corresponding position MOS tube, ECC circuits for error correction, ADC and Adder structures for calculation and data isolation, and Timer and Logic Controller circuits for generating timing and logic control signals. The writing of unit weight data is based on the basic unit of row, relying on the Write driver to apply appropriate voltage signals to the corresponding LSL / RSL and BL, and cooperating with the corresponding WL / WLb to control the Bitcell unit gating. 8-bit data is composed of 8 Bitcells to improve the calculation accuracy, and the column is used as the basic calculation unit for logical calculation output.

[0057] like Figure 3 , 4As shown, taking a single complementary Bitcell as an example, its data writing / refreshing process is based on the row primitive, and is divided into two stages: initialization writing "-1" and specific cell writing "+1": 1. Control WL and WLb to apply the conduction voltage VWL to turn on the complementary cell strobe tubes N0 and N1, and the Write Driver controls BL to connect to the high level Vw, LSL and RSL to ground, write AP to M0 and P to M1, and the Bitcell configuration is -1 (AP, P). This process is performed in rows until all cells in the Array are written. 2. In rows, select the Bitcell in the corresponding column that needs to be written to the +1 state, and similarly control WL and WLb to apply the conduction voltage to turn on the strobe tube, and the Write Driver controls BL to connect to the high level Vw, and LSL and RSL to connect to the high level Vw, and write P to M0 and AP to M1, and the Bitcell configuration is updated to +1 (AP, P). Among them, the defined states are: M0 low impedance state (P), M1 high impedance state (AP), BitcellState: +1; M0 high impedance state (AP), M1 low impedance state (P), Bitcell State: -1.

[0058] like Figure 5 As shown, data reading operation: The interconnection mode of the array determines that it can read a specific unit or read a row or column of data as a whole. The data reading operation here refers to the process of reading a single unit. The specific operation process is as follows:

[0059] 1. Switch the working mode to read mode through R&W Driver, connect BL to ground, and connect LSL and RSL to SA (Sense Amplifier) ​​circuit.

[0060] 2. The WL Driver selects the cell to be read and applies a turn-on voltage VWL to the WL and WLb terminals to turn on N1 and N2.

[0061] 3. The resistance state of the positive and negative ports (corresponding to M1 and M2) is sensed through SA. Since M1 and M2 are in a complementary state under normal circumstances, the pressure difference generated by the positive and negative ports of SA can determine the resistance state distribution of M1 and M2.

[0062] Among them, the existence of complementary units inside the Bitcell enables the SA circuit to adopt a self-reference design, thereby improving the sensing margin and accuracy.

[0063] like Figure 6-9As shown, MAC operation: This architecture is a MAC process built on XNOR logic. The MAC operation process in this architecture is the process of indirectly reading the resistance state of the column cell selected by WL in a single time step. After the calculation based on XNOR logic starts, the corresponding calculation voltage is applied from LSL and RSL terminals, and the Bitcell current is sensed at the BL terminal to obtain the following XNOR (X in ,W i )Result: Y out =∑X in ⊕W i The calculation results of the same column are summarized in the form of current to the bottom processing circuit (ADC+Adder), and finally fed back to the processing unit for subsequent calculation and processing.

[0064] like Figure 10-11 As shown, the ternary weight configuration operation: In order to suppress the accuracy loss and training cost increase caused by the traditional binary network, the academic community has proposed the idea of ​​multi-valued (such as ternary) network. Compared with the traditional 1T1M architecture, this scheme can effectively adapt to the ternary network by utilizing the asymmetry of MTJ and NMOS interconnection. Its configuration principle is shown in the table on the left. The configuration method of weights (+1, -1) for a single Bitcell has been described in the previous article. The configuration timing process of weight "0" is as follows: 1. Control WL and WLb to turn on N0 and turn off N1, connect BL to write voltage VW, LSL and RSL to ground, and write "AP" state to M0; 2. Control WL and WLb to turn on N1 and turn off N0, connect RSL to write voltage VW, connect LSL and BL to ground, and write "AP" state to M1. Note: It is worth noting that if the cell has been initialized, only the operation in (1) is required to complete the "0" state write.

[0065] By adopting the embodiment of the present invention, the data writing and logic calculation process are simplified, making it more suitable for binary or ternary neural network mapping, thereby achieving a calculation process with higher calculation accuracy and lower power consumption.

[0066] Method Embodiment

[0067] According to an embodiment of the present invention, a method for implementing storage calculation based on STT-MRAM is provided. Based on the storage calculation circuit based on STT-MRAM, Fig.12 is a flow chart of a storage computing implementation method based on STT-MRAM according to an embodiment of the present invention, such as Fig.12 As shown, the storage computing implementation method based on STT-MRAM according to an embodiment of the present invention specifically includes:

[0068] Step S1201, writing data in a row as a basic unit, controlling the corresponding LSL / RSL and BL through a read-write control circuit, and applying a suitable voltage signal;

[0069] Step S1202: The WL driver module is used to control the corresponding WL / WLb to select the gate circuit to realize data storage.

[0070] Specifically include:

[0071] When writing and refreshing data, the WL driver module controls WL and WLb to apply a conduction voltage to turn on the complementary cell gate tubes N0 and N1, and the read-write control circuit controls BL to connect to a high level, LSL and RSL to ground, write AP to M0 and P to M1, and the Bitcell configuration is -1. The above process is performed in units of rows until all cells in the 2T2M storage array are written; in units of rows, the Bitcell in the corresponding column that needs to be written to the +1 state is selected, and WL and WLb are controlled to apply a conduction voltage to turn on the gate tube, and the read-write control circuit controls BL to connect to a high level, LSL and RSL to connect to a high level, write P to M0 and AP to M1, and the Bitcell configuration is updated to +1;

[0072] When performing data reading operations, the read-write control circuit is controlled to switch the working mode to the read mode, BL is grounded, LSL and RSL are connected to the SA circuit, the unit to be read is selected through the WL driver module, and the turn-on voltage VWL is applied to the WL and WLb terminals to turn on N1 and N2. The resistance state of the positive and negative ports corresponding to M1 and M2 is sensed through the SA circuit. Since M1 and M2 are in a complementary state under normal circumstances, the SA circuit determines the resistance state distribution of M1 and M2 through the voltage difference generated by the positive and negative ports to realize data reading.

[0073] When performing a MAC operation, the corresponding calculation voltage is applied by the LSL and RSL terminals through the read-write control circuit, the Bitcell current is sensed at the BL terminal, and the XNOR result shown in Formula 1 is obtained, and the calculation result of the same column is summarized in the form of current to the ADC module, wherein the MAC operation is specifically a process of indirectly reading the column unit selected by the WLdriver module in a resistive state within a single time step:

[0074] Y out =∑X in ⊕W i Formula 1;

[0075] Among them, Yout represents the MAC summation result, which is output in the form of the current at the unit BL end; Xin represents input activation, which is configured by the level combination of the two MOS tube gate input lines WL and WLb of the 2T2M unit; Wi represents the storage weight, which is configured by the storage resistance state combination of the two MTJ units of the 2T2M unit.

[0076] When performing the ternary weight configuration operation, the WL driver module controls WL and WLb to turn on N0 and turn off N1, connects the write voltage to the BL terminal, controls LSL and RSL to be grounded through the read-write control circuit, and writes "AP" state to M0; the WL driver module controls WL and WLb to turn on N1 and turn off N0, connects the write voltage to the RSL terminal, controls LSL and BL to be grounded through the read-write control circuit, and writes "AP" state to M1.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A storage computing circuit based on STT-MRAM, characterized in that: include: A 2T2M storage array, comprising a plurality of electrically connected gate circuits and STT-MARM devices, for applying sufficiently large currents in different directions to the STT-MARM devices through the gate circuits, and performing high-resistance and low-resistance writes to the STT-MARM devices; A read and write control circuit, connected to the 2T2M storage array, for controlling the read and write data operations of the 2T2M storage array; A WL driver module, connected to the 2T2M storage array, and used to select the gate circuit at the corresponding position of the 2T2M storage array through a conduction voltage; An ECC circuit, connected to the 2T2M storage array, for performing error correction on the 2T2M storage array; An ADC module, connected to the 2T2M storage array, for acquiring current from the 2T2M storage array in columns, converting the current into data, and sending the data to the Adder module; A logic control module, connected to the read-write control circuit, the buffer and counter module, and the WL driver module, and used to send a logic control signal, and perform logic control on the read-write control circuit, the buffer and counter module, and the WL driver module through the logic control signal to achieve data writing and reading; An Adder module, connected to the ADC module, is used to calculate the data received from the ADC module to obtain a calculation result; A buffer and counter module is connected to the WL driver module and is used to store instruction data in a time sequence and send the instruction data to the WL driver module under the control of the logic control module, wherein the instruction data is used to control the WL driver module to conduct the gate array; A Timer module, connected to the buffer and counter module, the WL driver module, the ADC module, and the Adder module, for providing a timing signal; The buffer module is connected to the ADC module and the Adder module, and is used to store the intermediate data and calculation results generated when the ADC module and the Adder module perform data calculation.

2. The method according to claim 1, characterized in that: The 2T2M storage array specifically includes: a plurality of Bitcell units, 8 Bitcell units form 8-bit data, data is written with rows as basic units, and logic calculation output is performed with columns as basic units, wherein each Bitcell unit includes a first STT-MARM device M0, a first gate circuit N0, a second STT-MARM device M1 complementary to M0, and a second gate circuit N1 complementary to N0, which are connected in sequence, one end of the first STT-MARM device is connected to an LSL signal, and the other end is connected to one end of the first gate circuit, the other end of the first gate circuit is connected to a BL signal and connected to one end of the second STT-MARM device, the other end of the second STT-MARM device is connected to the second gate circuit, the other end of the second gate circuit is connected to an RSL signal, and the upper and lower ends of the first STT-MARM device are connected to a WL signal and a WLb signal respectively.

3. The method according to claim 2, characterized in that The logic control module is specifically used for: When writing and refreshing data, the WL driver module controls WL and WLb to apply a conduction voltage to turn on the complementary unit strobes N0 and N1, and the read-write control circuit controls BL to be connected to a high level, LSL and RSL to be grounded, M0 is written to AP state and M1 is written to P state, and the Bitcell configuration is -1. The above process is performed in units of rows until all cells in the 2T2M storage array are written; in units of rows, the Bitcell in the corresponding column that needs to be written to the +1 state is selected, and WL and WLb are controlled to apply a conduction voltage to turn on the strobes, and the read-write control circuit controls BL to be grounded, LSL and RSL to be connected to a high level, M0 is written to P state and M1 is written to AP state, and the Bitcell configuration is updated to +1.

4. The method according to claim 2, characterized in that The logic control module is specifically used for: When performing data reading operations, the read-write control circuit is controlled to switch the working mode to the read mode, BL is grounded, LSL and RSL are connected to the SA circuit, the unit to be read is selected through the WL driver module, and the turn-on voltage VWL is applied to the WL and WLb terminals to turn on N1 and N2. The resistance state of the positive and negative ports corresponding to M1 and M2 is sensed through the SA circuit. Since M1 and M2 are in a complementary state under normal circumstances, the SA circuit determines the resistance state distribution of M1 and M2 through the voltage difference generated by the positive and negative ports to realize data reading.

5. The method according to claim 2, characterized in that: The logic control module is specifically used for: When performing a MAC operation, the corresponding calculation voltage is applied by the LSL and RSL terminals through the read-write control circuit, the Bitcell current is sensed at the BL terminal, and the XNOR result shown in Formula 1 is obtained, and the calculation result of the same column is summarized in the form of current to the ADC module, wherein the MAC operation is specifically a process of indirectly reading the column unit selected by the WL driver module in a single time step in a resistive state: Y out = ∑X in ⊕W i Formula 1; Among them, Y out Represents the MAC summation result, which is output in the form of unit BL terminal current; X in Indicates input activation, which is configured by the level combination of the two MOS gate input lines WL and WLb of the 2T2M unit; W i Represents the storage weight, which is configured by the storage resistance state combination of the two MTJ units of the 2T2M unit.

6. The method according to claim 2, characterized in that The logic control module is specifically used for: When performing the ternary weight configuration operation, the WL driver module controls WL and WLb to turn on N0 and turn off N1, connects the write voltage to the BL terminal, controls LSL and RSL to be grounded through the read-write control circuit, and writes "AP" state to M0; the WL driver module controls WL and WLb to turn on N1 and turn off N0, connects the write voltage to the RSL terminal, controls LSL and BL to be grounded through the read-write control circuit, and writes "AP" state to M1.

7. A storage computing implementation method based on STT-MRAM, characterized in that: Based on the STT-MRAM-based storage computing circuit according to any one of claims 1 to 6, the method specifically comprises: Data is written in rows as basic units. The corresponding LSL / RSL and BL are controlled by the read-write control circuit, and appropriate voltage signals are applied. The corresponding WL / WLb is controlled by the WL driver module to select the gate circuit to realize data storage.

8. The method according to claim 7, characterized in that Data is written in the basic unit of line, and the corresponding LSL / RSL and BL are controlled by the read-write control circuit, and the appropriate voltage signal is applied. The corresponding WL / WLb is controlled by the WL driver module to select the gate circuit to realize data storage. Specifically, it includes: When writing and refreshing data, the WL driver module controls WL and WLb to apply a conduction voltage to turn on the complementary cell gate tubes N0 and N1, and the read-write control circuit controls BL to connect to a high level, LSL and RSL to ground, write AP to M0 and P to M1, and the Bitcell configuration is -1. The above process is performed in units of rows until all cells in the 2T2M storage array are written; in units of rows, the Bitcell in the corresponding column that needs to be written to the +1 state is selected, and WL and WLb are controlled to apply a conduction voltage to turn on the gate tube, and the read-write control circuit controls BL to connect to a high level, LSL and RSL to connect to a high level, write P to M0 and AP to M1, and the Bitcell configuration is updated to +1; When performing data reading operations, the read-write control circuit is controlled to switch the working mode to the read mode, BL is grounded, LSL and RSL are connected to the SA circuit, the unit to be read is selected through the WL driver module, and the turn-on voltage VWL is applied to the WL and WLb terminals to turn on N1 and N2. The resistance state of the positive and negative ports corresponding to M1 and M2 is sensed through the SA circuit. Since M1 and M2 are in a complementary state under normal circumstances, the SA circuit determines the resistance state distribution of M1 and M2 through the voltage difference generated by the positive and negative ports to realize data reading.

9. The method according to claim 7, characterized in that: The method further comprises: When performing a MAC operation, the corresponding calculation voltage is applied by the LSL and RSL terminals through the read-write control circuit, the Bitcell current is sensed at the BL terminal, and the XNOR result shown in Formula 1 is obtained, and the calculation result of the same column is summarized in the form of current to the ADC module, wherein the MAC operation is specifically a process of indirectly reading the column unit selected by the WL driver module in a single time step in a resistive state: Y out = ∑X in ⊕W i Formula 1; Among them, Y out Represents the MAC summation result, which is output in the form of unit BL terminal current; X in Indicates input activation, which is configured by the level combination of the two MOS gate input lines WL and WLb of the 2T2M unit; W i Represents the storage weight, which is configured by the storage resistance state combination of the two MTJ units of the 2T2M unit.

10. The method according to claim 7, characterized in that The method further comprises: When performing the ternary weight configuration operation, the WL driver module controls WL and WLb to turn on N0 and turn off N1, connects the write voltage to the BL terminal, controls LSL and RSL to be grounded through the read-write control circuit, and writes "AP" state to M0; the WL driver module controls WL and WLb to turn on N1 and turn off N0, connects the write voltage to the RSL terminal, controls LSL and BL to be grounded through the read-write control circuit, and writes "AP" state to M1.

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