Stacked memory device and method of manufacturing the same

Abstract

The invention relates to a stacked memory device and a method of manufacturing the same. The stacked memory device may include a memory cell array, a peripheral circuit block, and a leakage control block. The memory cell array may include at least one memory cell string. The memory cell string may include a plurality of memory cells vertically stacked. The peripheral circuit block may include a circuit configured to control an operation of the memory cell. The leakage control block may be disposed between the memory cell array and the peripheral circuit block. The leakage control block may include at least one select switch. The selection switch may selectively connect and disconnect the memory cell string from the peripheral circuit block. The memory cell array, the leakage control block, and the peripheral circuit block may be stacked in a vertical direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Application No. 10-2023-0093772, filed on Jul. 19, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a stacked memory device and a method of manufacturing the same, and more particularly, to a stacked memory device configured to reduce leakage and a method of manufacturing the stacked memory device. Background Art

[0004] In order to meet the good performance and low price required by customers, it is necessary to further improve the integration level (also called integration density) of semiconductor devices.

[0005] The integration level of a semiconductor device can be an important factor for determining the price of a product. The integration level of a two-dimensional or planar semiconductor device is mainly determined by the occupied area of ​​a unit memory cell. In addition, the occupied area of ​​a unit memory cell depends on the available technology for forming fine patterns.

[0006] In particular, fine patterns may be formed using expensive exposure devices or high-resolution exposure devices. Therefore, there may be a limit to increasing the integration of two-dimensional semiconductor devices.

[0007] Therefore, technology for arranging memory cells in a three-dimensional structure and for stacking a memory cell array and a peripheral circuit block in a three-dimensional structure has been developed.

[0008] However, since the unit memory cells are vertically stacked, stacked semiconductor devices may have problems with increased charge leakage, which may affect the control of the stacked memory cells. These and other problems associated with stacked semiconductor devices require new and more effective solutions to reduce charge leakage and effectively control the stacked memory cells. Summary of the invention

[0009] According to various embodiments of the present invention, a stacked memory device is provided. The stacked memory device may include a memory cell array, a peripheral circuit block, and a leakage control block. The memory cell array may include at least one memory cell string. The memory cell string may include a plurality of vertically stacked memory cells. The peripheral circuit block may include a circuit configured to control the operation of the memory cell. The leakage control block may be arranged between the memory cell array and the peripheral circuit block. The leakage control block may include at least one selection switch. The selection switch may selectively connect the memory cell string to the peripheral circuit block and disconnect the memory cell string from the peripheral circuit block. The memory cell array, the leakage control block, and the peripheral circuit block may be stacked in a vertical direction.

[0010] In some embodiments, the selection switch may include a single crystal column, a gate, a gate insulating layer, a drain, and a source. The single crystal column may extend in a vertical direction. The gate may be formed on the column. The gate insulating layer may be formed between the column and the gate. The drain may be formed at the column adjacent to the memory cell array. The source may be formed at the column adjacent to the peripheral circuit block.

[0011] In some embodiments, the peripheral circuit block may include a column decoding block configured to provide a driving voltage to a memory cell selected from memory cells connected to the memory cell string. The selection switch may be electrically connected to the column decoding block.

[0012] In some embodiments, when a memory cell among the memory cells of the memory cell string connected to the selection switch is selected, the selection switch may be turned on. Therefore, the memory cell string may be selectively connected to the peripheral circuit block. When the memory cell of the memory cell string connected to the selection switch is not selected, the selection switch may be turned off. Therefore, the memory cell string may be electrically disconnected from the peripheral circuit block.

[0013] According to various embodiments, a stacked memory device is provided, which includes a first structure, a second structure, and a third structure. The first structure may include a memory cell array. The memory cell array may include a plurality of memory cell strings. Each of the memory cell strings may include a plurality of memory cells. The second structure may be hybrid-joined with the first structure. The second structure may include a leakage control block. The leakage control block may include a plurality of selection switches connected to at least one of the memory cell strings. The third structure may be hybrid-joined with the second structure. The third structure may include a peripheral circuit block. The peripheral circuit block may be selectively connected or disconnected with the memory cell string by driving the selection switch.

[0014] In some embodiments, at least one of the first to third structures may include a wafer, a portion of a wafer, or a die.

[0015] According to an embodiment, a method for manufacturing a stacked memory device is provided. In the method for manufacturing a stacked memory device, a first structure, a second structure, and a third structure may be provided. The first structure may include a plurality of memory cell strings. The second structure may include a leakage control block. The third structure may include a peripheral circuit block. The second structure may be hybrid bonded with an upper surface of the first structure. Then, the third structure may be hybrid bonded with an upper surface of the second structure.

[0016] In some embodiments, providing the second structure may include providing a single crystal semiconductor layer. A plurality of selection switches may be formed in the single crystal semiconductor layer to form a leakage control block. Each of the selection switches may use a portion of the single crystal semiconductor layer as a vertical channel.

[0017] In some embodiments, forming a selection switch may include: etching a single crystal semiconductor layer to form a trench configured to define a vertical column; forming a gate insulating layer on a sidewall facing an outer sidewall of the vertical column; filling the trench with a conductive layer to form a gate; forming a drain in the exposed vertical column; planarizing the back side of the single crystal semiconductor layer to expose the back side of the vertical column and the gate; and forming a source on the exposed back side of the vertical column. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features, and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a simplified block diagram illustrating a stacked memory device according to an embodiment of the present disclosure;

[0020] Figure 2 and Figure 3 is a simplified cross-sectional schematic diagram showing a stacked memory device according to an embodiment of the present disclosure;

[0021] Figures 4 to 6 is a circuit diagram showing a stacked memory device according to an embodiment of the present disclosure;

[0022] Figure 7 is an enlarged and simplified cross-sectional schematic diagram showing a stacked memory device according to an embodiment of the present disclosure;

[0023] FIG. 8A to FIG. 11B , Fig.12 , Fig.13 , 14A and Fig. 14B is a simplified cross-sectional schematic diagram illustrating a method of manufacturing a selection switch of a leakage control block according to an embodiment of the present disclosure;

[0024] Fig.15A is a plan view showing a leakage control block according to an embodiment of the present disclosure; and

[0025] Fig. 15B It is along Fig.15A A simplified cross-sectional diagram taken along the a-a' line in FIG. DETAILED DESCRIPTION

[0026] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams of various embodiments and intermediate structures. Therefore, it is expected that the configurations and shapes shown in the drawings will vary due to reasons such as manufacturing technology and / or tolerances. Therefore, the described embodiments should not be interpreted as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not deviate from the technical concepts and scope of the present disclosure.

[0027] Embodiments of the present disclosure are described herein with reference to cross-sections and / or plan schematic diagrams showing some embodiments of the present disclosure. Importantly, the described embodiments are presented as examples of the present invention and should not be construed as limiting the concept of the invention. Although only a few embodiments of the present invention are shown and described, it should be understood by those of ordinary skill in the art that various changes and modifications may be made in these embodiments, and other embodiments may also be implemented without departing from the principles and technical concepts of the present disclosure.

[0028] As used herein, "memory device" means and includes a microelectronic device that exhibits a memory function, but is not necessarily limited to a memory function. In other words, and by way of non-limiting example only, the term "memory device" includes not only conventional memory (e.g., conventional volatile memory; conventional non-volatile memory), but also application specific integrated circuits (ASICs) (e.g., systems on a chip (SoC)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) that combine memory.

[0029] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of the one or more of the structure and device in a predetermined manner.

[0030] As used herein, the terms "vertical," "longitudinal," "horizontal," and "transverse" refer to the principal planes of a structure and are not necessarily defined by the Earth's gravitational field. A "horizontal" or "transverse" direction is a direction substantially parallel to the principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to the principal plane of a structure. The principal plane of a structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the accompanying drawings, a "horizontal" or "transverse" direction may be perpendicular to the indicated "Z" axis, and may be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, may be perpendicular to the indicated "X" axis, and may be perpendicular to the indicated "Y" axis.

[0031] As used herein, features (e.g., regions, structures, devices) described as being "adjacent" to each other mean and include features of the disclosed entity (or entities) that are closest (e.g., closest) to each other. Additional features (e.g., additional regions, additional structures, additional devices) that do not match the disclosed entity (or entities) of the "adjacent" features may be disposed between the "adjacent" features. In other words, the "adjacent" features may be positioned directly adjacent to each other, such that no other features intervene between the "adjacent" features; or, the "adjacent" features may be positioned indirectly adjacent to each other, such that at least one feature of a different entity from the entity associated with at least one "adjacent" feature is positioned between the "adjacent" features. Thus, features described as being "vertically adjacent" to each other mean and include features of the disclosed entity (or entities) that are closest (e.g., closest vertically) to each other. Furthermore, features described as being "horizontally adjacent" to each other mean and include features of the disclosed entity (or entities) that are closest (e.g., closest horizontally) to each other.

[0032] As used herein, for ease of description, spatial relative terms (such as, "below," "below," "lower," "bottom," "above," "upper," "top," "front," "back," "left," "right," etc.) may be used to describe the relationship between an element or feature shown in the figure and another element or feature. Unless otherwise stated, in addition to the orientation depicted in the figure, spatial relative terms are also intended to cover different orientations of materials. For example, if the material in the figure is inverted, the element described as being "below" or "below" or "under" or "on the bottom" of other elements or features will be oriented as "above" or "on the top" of other elements or features. Therefore, the term "below" can cover the orientation above and below, depending on the context in which the term is used, which will be obvious to a person of ordinary skill in the art. The material can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein are interpreted accordingly.

[0033] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0034] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] As used herein, it is understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. The same number always indicates the same element.

[0036] Embodiments of the present disclosure include a stacked memory device, which may include a leakage control block interposed between a memory cell array and a peripheral circuit block. The leakage control block may include at least one selection switch connected to at least one cell string. The selection switch may include a vertical transistor having a vertical channel. The vertical channel may have a single crystal structure. The selection switch of the leakage control block may selectively connect or disconnect the memory cell array with the peripheral circuit block to prevent the movement of leakage. Below, the stacked memory device may be described in detail.

[0037] Figure 1 is a simplified block diagram illustrating a stacked memory device according to an embodiment of the present disclosure.

[0038] refer to Figure 1 , the stacked memory device 10 may include a memory cell array 100 , a peripheral circuit block 200 , and a leakage control block 300 .

[0039] The memory cell array 100 may include at least one memory bank. For example, the memory cell array 100 may include a plurality of stacked memory banks MB1-MBn. Each of the memory banks MB1-MBn may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC, and the plurality of memory cells MC are arranged near the intersections between the word lines WL and the bit lines BL. In some embodiments, the memory banks MB1-MBn may be integrated in one wafer or a plurality of wafers. For example, each of the memory cells MC may include an access transistor TR and a capacitor CAP.

[0040] For example, when an access transistor TR located at a cross point between a selected word line WL and a selected bit line BL may be enabled, data may be written to or read from a capacitor CAP connected to the enabled access transistor TR.

[0041] The word lines WL of the memory cell array 100 may extend in parallel with each other along a first direction D1, and the bit lines BL may extend in parallel with each other along a second direction D2 crossing the first direction D1.

[0042] In some embodiments, each of the memory banks MB1-MBn may include a plurality of memory cell strings. The memory cell strings may each include a plurality of stacked memory cells MC along a third direction D3, and the third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2. The memory cells MC arranged in the same memory cell string may be commonly connected to a bit line BL or a portion of the bit line BL extending in the third direction D3.

[0043] The peripheral circuit block 200 may include a circuit configured to control the operation of the memory cell MC in the memory cell array 100. The operation of the memory cell MC may include a selection operation of a word line WL, a selection operation of a bit line BL, an operation for storing data in a selected memory cell or a capacitor of a memory cell, and an operation for reading data in a selected memory cell. Typically, the peripheral circuit block 200 may include a column decoding block 210 and a row decoding block 220.

[0044] The column decoding block 210 may select at least one of the bit lines BL of the memory cell array 100 based on the column address CADD.

[0045] The row decoding block 220 may select at least one of the word lines WL of the memory cell array 100 based on the row address RADD.

[0046] The peripheral circuit block 200 may further include a voltage generation block 230 , an address generation block 240 , and a control signal generation block 250 .

[0047] The voltage generation block 230 may receive a power supply voltage. The voltage generation block 230 may provide voltages to the column decoding block 210, the row decoding block 220, the address generation block 240, the control signal generation block 250, and other circuit blocks.

[0048] The address generation block 240 may receive an address command ADD provided from the controller to generate a column address CADD, a row address RADD, and a bank selection signal.

[0049] The control signal generation block 250 may generate a control signal CON and may transmit the control signal CON to the leakage control block 300 .

[0050] The leakage control block 300 may be arranged between the memory cell array 100 and the peripheral circuit block 200. The leakage control block 300 may include at least one selection switch. The selection switch may selectively connect or disconnect at least one memory cell string with the peripheral circuit block 200, for example, connect or disconnect at least one memory cell string with the column decoding block 210.

[0051] Figure 2 and Figure 3 is a simplified cross-sectional schematic diagram illustrating a stacked memory device according to an embodiment of the present disclosure.

[0052] refer to Figure 2 and Figure 3 , the peripheral circuit block 200 , the leakage control block 300 , and the memory cell array 100 in the stacked memory device 10 may be stacked along a third direction D3 .

[0053] The memory cell array 100 may include stacked memory banks MB1-MBn. In some embodiments, the memory banks MB1-MBn may be integrated in one structure. Alternatively, the memory banks MB1-MBn may be integrated in different structures. Then, the different structures may be coupled or bonded to each other.

[0054] The peripheral circuit block 200 may provide a plurality of driving signals for a memory operation to the selected memory cells MC of each of the memory banks MB1 ˜MBn The peripheral circuit block 200 may receive data of the selected memory cells MC in the memory cell array 100 .

[0055] As described above, the selection switch SW of the leakage control block 300 may form a current transmission path through which the drive signal S and the data DATA may be transmitted between the memory cell array 100 and the peripheral circuit block 200. In addition, the selection switch SW may cut off the current transmission path between the memory cell array 100 and the peripheral circuit block 200.

[0056] Figures 4 to 6 is a circuit diagram illustrating a stacked memory device according to an embodiment of the present disclosure.

[0057] refer to Figure 4 , the selected memory bank MB of the memory cell array 100 may include a plurality of rows and a plurality of columns. For convenience of description, three rows 1R to 3R and one column 1C may be shown in the drawings.

[0058] Each of the first to third rows 1R, 2R, and 3R may be substantially parallel to the first direction D1. The first column 1C may be substantially parallel to the second direction D2.

[0059] The three-layer word lines WL11-WL13, WL21-WL23, WL31-WL33 may be arranged at rows 1R, 2R, 3R, respectively. The word lines WL11-WL13 may be electrically isolated from each other. The word lines WL21-WL23 may be electrically isolated from each other. The word lines WL31-WL33 may be electrically isolated from each other.

[0060] The bit line BL may be located at the first column 1C. The bit line BL may include a plurality of bit line contacts BLC1 to BLC3 at intersections between the word lines WL11 to WL13, WL21 to WL23, and WL31 to WL33. The bit line contacts BLC1 to BLC3 may extend in a third direction D3. Hereinafter, the bit line contacts BLC1 to BLC3 may be interpreted as bit lines extending in the third direction D3 or in a vertical direction.

[0061] The memory cells MC may be located near intersections between the bit line contacts BLC1 ˜ BLC3 and the word lines WL11 ˜ WL13 , WL21 ˜ WL23 , and WL31 ˜ WL33 .

[0062] In some embodiments, a group of memory cells MC connected to each of the bit line contacts BLC1 ˜ BLC3 may be referred to as memory cell strings CTR1 , CTR2 , and CTR3 .

[0063] The leakage control block 300 may include at least one selection switch SW. For example, the selection switch SW may selectively connect or disconnect the first to third memory cell strings CTR1 to CTR3 from the peripheral circuit block 200. In particular, the selection switch SW may include a transistor.

[0064] The drain of the selection switch SW may be commonly connected to the bit line contacts BLC1 to BLC3 of the first to third memory cell strings CTR1 to CTR3. The source of the selection switch SW may be connected to the peripheral circuit block 200 (e.g., the column decoding block 210). The gate of the selection switch SW may receive a control signal CON. For example, the control signal CON may be generated from the control signal generation circuit 250 of the peripheral circuit block 200. The control signal generation circuit 250 may generate the control signal CON based on the address information of the selected memory cell. The address information of the selected memory cell may include a column selection signal CS and a row selection signal RS. For example, when the memory cell array 100 includes Figure 1 When selecting the memory banks MB1 to MBn in the address generation circuit 250, the address information of the selected memory cell may also include the memory bank selection signal BS and the column selection signal CS and the row selection signal RS. Therefore, the control signal generation circuit 250 may generate the control signal CON by combining the memory bank selection signal BS, the column selection signal CS and the row selection signal RS. For example, the address generation block 240 may generate the memory bank selection signal BS. The column decoding block 210 may generate the column selection signal CS. The row decoding block 220 may generate the row selection signal RS.

[0065] Alternatively, the control signal generating circuit 250 may output an enabled control signal CON to the selection switch SW connected to the selected memory cell MC based on the address information. The control signal generating circuit 250 may output a disabled control signal CON to the selection switch SW connected to the unselected memory cell MC.

[0066] For example, when the control signal CON is enabled, the selection switch SW may be turned on. The peripheral circuit block 200 may provide a driving voltage, i.e., a bit line voltage, to the bit line contacts BLC1 to BLC3 through the selection switch SW according to an operation command for determining a memory operation. In addition, the data in the selected memory cell MC may be transmitted to the peripheral circuit block 200 through the bit line contacts BLC1 to BLC3 and the selection switch SW according to the operation command. When the operation command is a write command, the bit line voltage may be a write voltage. When the operation command is a read command, the bit line voltage may be a read voltage.

[0067] Because the memory cells MC of the memory cell array 100 are densely arranged in the vertical and horizontal directions, leakage may be generated at the unselected memory cells MC around the selected memory cells MC due to the influence of the selected memory cells MC on the unselected memory cells MC. This may be a deep-rooted problem in DRAM devices. Specifically, in a stacked memory device, the leakage charge generated at the memory cell array 100 may flow into the peripheral circuit block 200, thereby causing other electrical problems of the peripheral circuit block 200.

[0068] In contrast, when the leakage control block 300 having the selection switch SW may be interposed between the memory cell array 100 and the peripheral circuit block 200, at least one memory cell string CTR1 to CTR3 including the unselected memory cell MC and the peripheral circuit block 200 may be electrically disconnected from each other by the selection switch SW. Therefore, the charge in the unselected memory cell MC does not flow into the peripheral circuit block 200. The charge in the unselected memory cell MC may return to the original position (i.e., the original memory cell). Therefore, data loss may be prevented.

[0069] Or, if Figure 5 As shown, the leakage control block 300a may include a plurality of selection switches SW1-SW3 respectively connected to the memory cell strings CTR1-CTR3. That is, the selection switches SW1-SW3 may be respectively connected to the bit line contacts BLC1-BLC3 in a one-to-one correspondence.

[0070] The selection switches SW1-SW3 may be driven in response to a plurality of corresponding control signals CON1-CON3. The control signal generation circuit 250a in the peripheral circuit block 200 may generate the control signals CON1-CON3. The control signal generation circuit 250a may generate the control signals CON1-CON3 by a combination of a bank selection signal BS, a column selection signal CS, and a row selection signal RS.

[0071] For example, when the memory cell MC connected to the first bit line contact BLC1 of the first memory cell string CTR1 is selected and the memory cells MC of the second memory cell string CTR2 and the third memory cell string CTR3 are not selected, the control signal generating circuit 250a can output the enabled first control signal CON1 and the disabled second control signal CON2 and the third control signal CON3.

[0072] Therefore, the first selection switch SW1 may be turned on based on the enabled first control signal CON1 so that a bit line voltage according to an operation command may be transmitted to the first bit line contact BLC1 .

[0073] The second selection switch SW2 and the third selection switch SW3 may be turned off based on the disabled second control signal CON2 and the third control signal CON3 , respectively.

[0074] Although the selected memory cell MC of the first memory cell string CTR1 may generate leakage charge at the unselected memory cells MC of the second and third memory cell strings CTR2 and CTR3 , the leakage current caused by the leakage charge is not transmitted to the peripheral circuit block 200 due to the turning off of the second and third selection switches SW2 and SW3 .

[0075] In addition, if Figure 6 As shown, the leakage control block 300b may include first to third selection switches SW1 to SW3 connected between the first to third storage cell strings CTR1 to CTR3 and the peripheral circuit 200. Specifically, the first selection switch SW1 is connected between the first storage cell string CTR1 and the peripheral circuit 200, the second selection switch SW2 is connected between the second storage cell string CTR2 and the peripheral circuit 200, and the third selection switch SW3 is connected between the third storage cell string CTR3 and the peripheral circuit 200. The gates of the first to third selection switches SW1 to SW3 may receive the control signal CON from the peripheral circuit block 200 in common. The source of each of the first to third selection switches SW1 to SW3 may be connected in common to the peripheral circuit block 200, that is, via a common line (not shown) in the peripheral circuit block 200. Reference symbol Lg denotes a gate signal line for transmitting the control signal CON from the peripheral circuit block 200 to the gate of each of the first to third selection switches SW1 to SW3.

[0076] Figure 7 is an enlarged and simplified cross-sectional schematic diagram showing a stacked memory device according to an embodiment of the present disclosure.

[0077] The memory cell array 100, the peripheral circuit block 200, and the leakage control block 300 of the stacked memory device 10 may be integrated in different structures. The memory cell array 100, the peripheral circuit block 200, and the leakage control block 300 may be integrated in different structures, for example, by stacking them on each other, wherein the leakage control block is disposed between the peripheral circuit board 200 and the memory cell array 100, and bonding them to each other, for example Figure 2 or Figure 3 shown.

[0078] refer to Figure 7 , the stacked memory device 10 may include a first structure to a third structure W1, W2 and W3 stacked in the order listed. The structure may correspond to a wafer, a die or a portion of a wafer. The first structure to the third structure W1, W2 and W3 may be hybrid bonded to each other. Hybrid bonding involves bonding the structures together at the atomic level to establish a strong and reliable connection. This can be achieved by bonding insulating layers or pads that are positioned to be in direct contact with each other. Van der Waals forces cause the structures to adhere to each other. In some embodiments, bonding can be enhanced by applying heat and / or pressure.

[0079] In some embodiments, the first memory cell array 100 may be integrated in a first structure W1. The leakage control block 300 may be integrated in a second structure W2. The peripheral circuit block 200 may be integrated in a third structure W3.

[0080] The first structure W1 may include a main body substrate. The memory cell array 100 may be formed on one surface of the main body substrate. The main body substrate may be removed after completing a process for forming a stacked memory bank.

[0081] The memory cell array 100 may include at least one layer of memory banks MB. The memory banks MB may include at least two stacked memory cells MC. The at least two stacked memory cells MC may be stacked along a third direction D3 that may be perpendicular to a planar surface of the body substrate defined by the directions D1 and D2.

[0082] Each of the at least two stacked memory cells MC may include a word line WL, a bit line, an access transistor TR, a capacitor CAP, and a plate line PL. The access transistor TR and the capacitor CAP may be arranged in a second direction D2 (e.g., a first horizontal direction). The word line WL may extend in a first direction D1 (e.g., a second horizontal direction). The bit line may extend in a third direction D3. Figure 7 The bit lines in can correspond to Figures 4 to 6 The bit line contacts BLC.

[0083] The memory cell array 100 may include a DRAM memory cell array. Alternatively, the memory cell array 100 may have a cross-point structure such as PCRAM, RERAM, MRAM, etc. The capacitor CAP may be replaced by another memory element.

[0084] For example, the stacked memory cells MC may share one bit line contact BLC. The bit line contact BLC may include a conductive material, such as a silicon-based material, a metal-based material, and a combination thereof.

[0085] The access transistor TR may be located between the bit line contact BLC and the capacitor CAP. The transistor TR may include an active layer ACT, a gate insulating layer GD, and a word line WL.

[0086] The active layer ACT may extend from a sidewall of the bit line contact BLC in the second direction D2. The active layer ACT may include a semiconductor material having conductive impurities. A plurality of active layers ACT may be stacked in the third direction D3.

[0087] The word line WL may be formed on at least one side surface of the active layer ACT. The word line WL may extend in the first direction D1. For example, the word line WL may be arranged above or below the active layer ACT corresponding to the central portion between the bit line contact BLC and the capacitor CAP. The gate insulating layer GD may be interposed between the word line WL and the active layer ACT. For example, when the upper word line WLU and the lower word line WLL may be arranged on the upper surface and the lower surface of an active layer ACT, the upper word line WLU and the lower word line WLL may have different potentials. Alternatively, the word line WL may have a full surround gate (GAA) structure configured to surround the active layer ACT. The word line WL may include a metal, a metal mixture, a metal alloy, a semiconductor material, and the like.

[0088] The first junction region SD1 may be formed in the active layer ACT between the word line WL and the bit line contact BLC. The second junction region SD2 may be formed in the active layer ACT between the word line WL and the capacitor CAP. The first junction region SD1 and the second junction region SD2 may include n-type impurities having a high concentration. The first junction region SD1 may contact the bit line contact BLC. The second junction region SD2 may contact the capacitor CAP. The active layer ACT between the first junction region SD1 and the second junction region SD2 may be defined by a channel CH. The channel CH may be formed by a voltage applied to the word line WL and a voltage applied to the bit line contact BLC.

[0089] The active layer ACT stacked in the third direction D3 may be isolated and supported by the insulating interlayer ILD. For example, the insulating interlayer ILD may include an insulating material such as silicon oxide.

[0090] The capacitor CAP may be connected to the second junction region SD2 of the access transistor TR. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN, the dielectric layer DE, and the plate node PN may be arranged horizontally in the second direction D2. The storage node SN may have a cylindrical shape arranged horizontally. The plate node PN may have a shape extending to the inner wall and the outer wall of the cylindrical storage node SN. The dielectric layer DE may be inserted between the storage node SN and the plate node PN. The plate line PL may extend in a third direction D3. The plate line PL may contact the stacked plate node PN of the capacitor CAP.

[0091] In order to form the stacked memory body MB, the main substrate may be removed. When the main substrate may be removed, the upper and lower surfaces of the memory cell array 100 may be exposed. Pad electrodes that may transmit signals to the memory cell array 100 may be formed on the exposed upper and lower surfaces of the memory cell array 100. The pad electrodes may be conductive pads configured to transmit signals to electrodes in the memory cell array 100.

[0092] A first bonding insulating layer 140 and a first bonding pad 150 may be formed on an upper surface of the memory cell array 100 having the pad electrode. The first bonding pad 150 may be electrically connected to the pad electrode. Figure 7 Only the first bonding pad 150 electrically connected to the bit line contact BLC may be shown. Alternatively, a bonding pad may be provided to the first bonding insulating layer 140, and the bonding pad may be connected to a pad electrode connected to an electrode of the memory cell array 100 except the bit line contact BLC.

[0093] A leakage control block 300 having at least one selection switch SW may be integrated in the second structure SW2. The leakage control block 300 may include a single crystal semiconductor layer 310. The selection switch SW may be located between the single crystal semiconductor layers 310. The selection switch SW may have a vertical channel structure. The selection switch SW may connect or disconnect at least one memory cell string CTR in the first structure W1 with the peripheral circuit block 200 in the third structure W3.

[0094] The structure of the leakage control block 300 and a method of manufacturing the leakage control block 300 having the selection switch SW will be described later.

[0095] The second bonding insulating layer 340 and the second bonding pad 350 may be formed on the bottom surface of the second structure W2, wherein the selection switch SW faces the first structure W1. The second bonding insulating layer 340 may be hybrid bonded to the first bonding insulating layer 140 of the first structure W1. The second bonding pad 350 may be hybrid bonded to the first bonding pad 150 of the first structure W1. The third bonding insulating layer 380 and the third bonding pad 390 may be further formed on the upper surface of the second structure W2 facing the third structure W3. The leakage control block 300 may include a wiring structure MS configured to electrically connect the selection switch SW to the third bonding pad 390. Therefore, the selection switch SW and the third bonding pad 390 may be electrically connected to each other through the wiring structure MS. Although not described in the drawings, the wiring structure may also be inserted between the selection switch SW and the second bonding pad 150.

[0096] The third structure W3 may include a semiconductor substrate 201. A plurality of transistors tr may be formed on the substrate 201. Therefore, the third structure W3 may include a peripheral circuit block 200, and the peripheral circuit block 200 includes a column decoding block 210a and a row decoding block 220. A fourth bonding insulating layer 280 and a fourth bonding pad 290 may be formed on the bottom surface of the third structure W3 facing the second structure W2. The peripheral circuit block 200 may also include a wiring structure ms. The wiring structure ms may include a plurality of multilayer metal wirings configured to electrically connect the fourth bonding pad 290 to the transistor tr. The wiring structure ms may be a conductive path configured to reciprocate current in a vertical direction (i.e., a third direction D3).

[0097] The fourth bonding insulation layer 280 of the third structure W3 may be directly bonded to the third bonding insulation layer 380 of the second structure W2. The fourth bonding pad 290 of the third structure W3 may be directly bonded to the third bonding pad 390 of the second structure W2.

[0098] Therefore, the first structure W1 having the memory cell array 100 , the second structure W2 having the leakage control block 300 , and the third structure W3 having the peripheral circuit block 200 may be hybrid-bonded with each other to form the stacked memory device 10 .

[0099] According to some embodiments, leakage control block 300 may be interposed between memory cell array 100 and peripheral circuit block 200 to selectively connect or disconnect memory cell array 100 and peripheral circuit block 200 , thereby preventing leakage charge from penetrating into peripheral circuit block 200 .

[0100] In addition, the leakage control block 300 may be adjacent to the memory cell block 100 and the peripheral circuit block 200 to reduce a transfer path of leakage charges.

[0101] Furthermore, the leakage control block 300 may be formed in a structure independently of the memory cell array 100 and the peripheral circuit block 200. Therefore, the channel of the selection switch SW, which is an actual current path, may include a material that may be slightly affected by leakage.

[0102] FIG. 8A to FIG. 11A and Fig.14A is a simplified cross-sectional schematic diagram illustrating a method of manufacturing a selection switch of a leakage control block according to an embodiment of the present disclosure. FIG. 8B to FIG. 11B , Fig.12 , Fig.13 and Fig. 14B is a simplified cross-sectional schematic diagram illustrating a method of manufacturing a selection switch of a leakage control block according to an embodiment of the present disclosure. FIG. 8B to FIG. 11B , Fig.12 , Fig.13 and Fig. 14B is along FIG. 8A to FIG. 11A and Fig.14A A simplified cross-sectional diagram taken along the a-a' line in FIG.

[0103] refer to Fig. 8A and 8B The second structure W2 may include a semiconductor layer 310. The semiconductor layer 310 may have a single crystal structure. For example, the semiconductor layer 310 may include a silicon layer, a silicon substrate, an epitaxial growth layer, a silicon germanium layer, etc. The semiconductor layer 310 may include a first conductive type impurity, such as a p-type impurity.

[0104] A trench t1 for defining a pillar 315 may be formed in the semiconductor layer 310. The trench t1 may have a width and a depth. The trench t1 may have a planar annular shape. A portion of the semiconductor layer 310 may be defined as a pillar 315 of the selection switch SW by the annular trench t1. The width of the trench t1 may be set based on the width of the gate. The depth of the trench t1 may be set based on the height of the selection switch SW.

[0105] refer to Fig. 9A and Fig. 9B , gate insulating layers 320 and 320 a may be formed on both sidewalls of the trench t1 .

[0106] For example, an insulating layer having a conformal thickness may be formed on the upper surface of the semiconductor layer 310 having the trench t1. The insulating layer on the upper surface of the semiconductor layer 310 and the bottom surface of the trench t1 may be removed by an anisotropic etching process to form gate insulating layers 320 and 320a on both side walls of the trench t1. The gate insulating layers 320 and 320a may include a silicon oxide layer. Therefore, the outer peripheral surface of the pillar 315 and the semiconductor layer 310 may be covered by the gate insulating layers 320 and 320a.

[0107] refer to Fig. 10A and10B In the embodiment, the gate 330 may be formed in the trench t1.

[0108] For example, the gate 330 may be formed by forming a conductive layer in the trench t1 and planarizing the conductive layer until the upper surface of the semiconductor layer 310 may be exposed. The conductive layer may include a polysilicon layer having conductive impurities, at least one metal, etc. In example embodiments, the gate 330 may have a ring shape configured to surround the pillar 315.

[0109] refer to Fig.11A and 11B , the second conductive type impurities may be implanted into the upper surface of the pillar 315 surrounded by the gate 330 to form the drain D. The second conductive type impurities may include n-type impurities having a high concentration.

[0110] The second bonding insulating layer 340 may be formed on the upper surface of the semiconductor layer 310 having the drain D. The second bonding insulating layer 340 may include a silicon oxide layer. The second bonding insulating layer 340 may be etched until the drain D may appear to form a contact hole, which is filled with a conductive layer (e.g., a copper layer) to form a second bonding pad 350.

[0111] exist Fig.11A and 11B In FIG. 1 , the second bonding pad 350 may directly contact the drain electrode D. At least one conductive layer or wiring structure may be interposed between the second bonding pad 350 and the drain electrode D. In order to illustrate the connection relationship between the drain electrode D of the selection switch SW and the second bonding pad 350, Fig.11A The second bonding insulating layer 340 may be omitted.

[0112] refer to Fig.12 , the second structure W2 may be stacked on the first structure W1 having the memory cell array 100. For example, the second bonding insulating layer 340 of the second structure W2 may be directly bonded to the first bonding insulating layer 140 of the first structure W1. The first bonding pad 140 and the second bonding pad 350 may be directly bonded to each other to hybrid-bond the second structure W2 with the first structure W1.

[0113] Since the flipped second structure W2 may be bonded to the first structure W1, the backside of the semiconductor layer 310 of the second structure W2 may be exposed. Fig.13 , the back side of the semiconductor layer 310 may be polished until the surface of the gate 330 may be exposed to reduce the thickness of the second structure W2 , thereby exposing the pillar 315 of the selection switch SW.

[0114] The second conductive type impurities having a high concentration may be implanted into the exposed pillar 315 to form a source S. In some embodiments, the source S may be formed after the drain D is formed. Alternatively, the source S may be formed before the drain D is formed. Fig. 11B The drain D in the column 315 is previously formed by implanting impurities. The drain D may be arranged under the column 315 and the source S may be arranged above the column 315 (see FIG. Fig.13 ). Therefore, a vertical channel extending in the third direction D3 may be formed in the pillar 315 between the drain D and the source S. In addition, since the pillar 315 may include the single crystal semiconductor layer 310, the vertical channel may also have a single crystal structure, so that a leakage current source in the selection switch SW may be reduced.

[0115] refer to Fig.14A and 14B , the wiring structure MS may be formed at the gate 330 and the source S of the selection switch SW. The wiring structure MS may include a gate contact 370a, a source contact 370b, and a plurality of conductive lines 372. The gate contact 370a may be connected to the gate 330. The source contact 370b may be connected to the source S. The conductive line 372 may be connected to the gate contact 370a and the source contact 370b.

[0116] In some embodiments, when the gate insulating layers 320 and 320a are located on both side walls of the trench t1, the gate 330 may be isolated. That is, since the gate insulating layers 320 and 320a are located between the gate 330 and the semiconductor layer 310a and between the gate 330 and the pillar 315, the gate 330 of the selection switch SW is electrically isolated by the gate insulating layer 320a. Therefore, a gate contact 370a and a source contact 370b may be provided to each of the selection switches SW.

[0117] A first insulating interlayer 360 may be formed on the exposed surface of the second structure W2 having the selection switch SW. The first insulating interlayer 360 may be etched until the source S and the gate 320 of each of the selection switches SW may be exposed to form a through hole. The through hole may be filled with a conductive material to form a gate contact 370a and a source contact 370b. A conductive line 372 may contact the gate contact 370a and the source contact 370b to form a wiring structure MS of the second structure W2. Then, a protective layer 375 may be formed on the wiring structure MS.

[0118] exist Fig. 14B In the embodiment, the conductive line 372 connected to the gate contact 370a and the source contact 370b may be located on the first insulating interlayer 360, but is not limited thereto. For example, the conductive line 372 connected to the gate contact 370a and the source contact 370b may be located on different planes.

[0119] Alternatively, the gate insulating layer 320 may be located only between the gate 330 and the pillar 315. In this case, the gate 330 may be in contact with the semiconductor layer 310.

[0120] Fig.15A is a plan view showing a leakage control block according to an embodiment of the present disclosure, Fig. 15B It is along Fig.15A A simplified cross-sectional diagram taken along the a-a' line in FIG.

[0121] refer to Fig.15A and 15B , when the gate insulating layer 320 is located only between the gate 330 and the pillar 315, as described above, the gate 330 may be in direct contact with the semiconductor layer 310. Therefore, the semiconductor layer 310 outside the gate 330 may be used as a gate connection line connecting all the gates 330 of the adjacent selection switches SW. In some embodiments, the semiconductor layer 310 may correspond to Figure 6 The gate signal line Lg in.

[0122] In this case, the gate contact 370a may be formed at a portion of the semiconductor layer 310. The source contact 370b may be in contact with the source S. The source contacts 370b may be connected to each other through one wire.

[0123] In some embodiments, the leakage control block 300 having the selection switch SW may be provided to a structure different from the structure having the memory cell array 100 and the peripheral circuit block 200. The leakage control block 300 may be formed at a structure including a single crystal material, which may have a small leakage source. Therefore, the grain boundary of the channel of the selection switch SW may be smaller than that of other switch structures using a polysilicon channel to reduce leakage current.

[0124] The third structure W3 having the peripheral circuit block 200 may be hybrid-bonded with the second structure W2 to complete the stacked memory device 10 .

[0125] According to some embodiments, a leakage control block having a selection switch may be inserted between a memory cell array and a peripheral circuit block. The selection switch of the leakage control block may selectively connect or disconnect at least one memory cell string of the memory cell array with the peripheral circuit block. Therefore, when all memory cells in the memory cell string are not selected, leakage charges of the unselected memory cells will not penetrate into the peripheral circuit block to improve the repetition rate of the charges.

[0126] Specifically, the selection switch of the leakage control block may have a vertical channel structure. The selection switch may be adjacent to the memory cell array rather than the peripheral circuit block. Therefore, the leakage current path may be greatly reduced to prevent the electrical characteristics from being degraded due to the leakage current.

[0127] In addition, since the charge loss can also be reduced by reducing the leakage current, the volume of the capacitor can be reduced, and the volume of the capacitor can be designed to have a large volume in consideration of the charge loss. Therefore, the integration of the capacitor can be improved by reducing the volume of the capacitor.

[0128] In addition, the leakage control block may be integrated in a structure different from the structure in which the memory cell array and the peripheral circuit block may be integrated. When the structure having the leakage control block includes a single crystal semiconductor layer or a single crystal semiconductor substrate, the current path of the selection switch (i.e., the channel of the selection switch) may also include a single crystal semiconductor material to reduce accidental leakage current.

[0129] The above-described embodiments of the present disclosure are intended to illustrate rather than limit the present invention. There may be a variety of alternatives and equivalents. The present invention is not limited to the embodiments described herein. The present invention is also not limited to any particular type of semiconductor device. Other additions, reductions, or modifications that are apparent in view of the present disclosure are intended to fall within the scope of the appended claims. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A stacked memory device, comprising: a memory cell array comprising at least one memory cell string, the memory cell string comprising a plurality of memory cells stacked in a vertical direction; a peripheral circuit block including circuits for controlling the operation of the memory cell; as well as a leakage control block disposed between the memory cell array and the peripheral circuit block, the leakage control block comprising at least one selection switch that selectively connects and disconnects the at least one memory cell string from the peripheral circuit block, Wherein, the memory cell array, the leakage control block and the peripheral circuit block are stacked in the vertical direction.

2. The stacked memory device according to claim 1, in, The selection switch includes a vertical channel that selectively connects and disconnects the at least one memory cell string from the peripheral circuit block, and Wherein, the vertical channel has a single crystal structure.

3. The stacked memory device according to claim 1, wherein: The selection switch comprises: a single crystal column extending in a direction substantially parallel to the vertical direction; a gate formed on an outer surface of the pillar; a gate insulating layer disposed between the pillar and the gate; a drain formed in the pillar adjacent to the memory cell array; and A source is formed in the pillar adjacent to the peripheral circuit block.

4. The stacked memory device according to claim 1, wherein: The memory cell array is integrated in a first structure, the leakage control block is integrated in a second structure different from the first structure, the peripheral circuit block is integrated in a third structure different from the first structure and the second structure, and the first structure to the third structure are hybrid-joined with each other.

5. The stacked memory device according to claim 4, wherein: The second structure includes a single crystal semiconductor layer, and Wherein, the selection switch comprises: a pillar including a portion of the single crystal semiconductor layer; a gate formed on an outer surface of the pillar; a gate insulating layer disposed between the pillar and the gate; a drain formed in the pillar adjacent to the memory cell array; and A source is formed in the pillar adjacent to the peripheral circuit block.

6. The stacked memory device according to claim 5, wherein: The single crystal semiconductor layer is located outside the gate.

7. The stacked memory device according to claim 6, wherein: The gate insulating layer is arranged between the gate and the single crystal semiconductor layer.

8. The stacked memory device according to claim 1, wherein: The memory cell string includes a bit line contact extending in the vertical direction and commonly connected to the stacked memory cells.

9. The stacked memory device according to claim 8, wherein: Each of the storage units comprises: at least one active layer extending from a sidewall of the bit line contact in a horizontal direction intersecting the vertical direction; a word line disposed on at least one of an upper surface and a lower surface of the active layer and extending in a direction intersecting the active layer and the bit line contact; and A capacitor is electrically connected to an end of the active layer spaced apart from the bit line contact.

10. The stacked memory device according to claim 1, wherein: The peripheral circuit block includes a column decoding block which supplies a driving voltage to a memory cell selected from the memory cells, and the selection switch is electrically connected to the column decoding block.

11. The stacked memory device according to claim 1, wherein: The selection switch is turned on when a memory cell among the memory cells in the memory cell string connected to the selection switch is selected, and the selection switch is turned off when all memory cells in the memory cell string connected to the selection switch are not selected.

12. The stacked memory device according to claim 11, wherein: The memory cell array includes a plurality of the memory cell strings, and the selection switch of the leakage control block includes a plurality of switches respectively connected to the memory cell strings.

13. A stacked memory device, comprising: A first structure comprising a memory cell array, the memory cell array comprising a plurality of memory cell strings, each of the memory cell strings comprising a plurality of memory cells; a second structure hybridly coupled with the first structure, the second structure comprising a leakage control block including a plurality of selection switches connected to at least one of the memory cell strings; as well as A third structure is hybrid-joined with the second structure, the third structure including a peripheral circuit block that is selectively connected to and disconnected from the memory cell string by driving the selection switch.

14. The stacked memory device according to claim 13, wherein: At least one of the first to third structures includes a wafer, a portion of a wafer, or a die.

15. The stacked memory device according to claim 13, wherein: The second structure includes a single crystalline semiconductor layer.

16. The stacked memory device according to claim 15, wherein: Each of the selector switches comprises: a pillar extending in a vertical direction from the single crystal semiconductor layer; a gate formed on an outer surface of the pillar; a gate insulating layer disposed between the pillar and the gate; a drain formed in the pillar adjacent to the memory cell array; and A source is formed in the pillar adjacent to the peripheral circuit block.

17. The stacked memory device according to claim 16, wherein: The single crystal semiconductor layer directly contacts the outer sidewalls of the gate to connect the gates of the adjacent selection switches to each other.

18. The stacked memory device according to claim 16, wherein: The single crystal semiconductor layer is located outside the gate.

19. The stacked memory device according to claim 16, wherein: Each of the memory cell strings includes a bit line extending in the vertical direction, the memory cells in each of the memory cell strings are commonly connected to the bit line and stacked in the vertical direction, and the bit line is hybrid-joined with the drain of the selection switch.

20. The stacked memory device according to claim 16, wherein: The peripheral circuit block includes a column decoding block that provides a driving voltage to a memory cell selected from the memory cells and is electrically connected to the source of the selection switch.

21. A method for manufacturing a stacked memory device, the method comprising: providing a first structure including a memory cell array having a plurality of memory cell strings, a second structure including a leakage control block, and a third structure including a peripheral circuit block; hybridly bonding the second structure to the upper surface of the first structure; as well as The third structure is mixed and joined with the upper surface of the second structure, Wherein, providing the second structure comprises: providing a single crystal semiconductor layer; and A plurality of selection switches are formed in the single crystal semiconductor layer to form the leakage control block, the plurality of selection switches using a portion of the single crystal semiconductor layer as a vertical channel.

22. The method of claim 21, wherein: Forming the selection switch includes: etching the single crystalline semiconductor layer to form trenches defining vertical pillars; forming a gate insulating layer on the sidewalls of the trench facing the outer sidewalls of the vertical pillar; filling the trench with a conductive layer to form a gate; forming a drain on the exposed vertical column; planarizing a back surface of the single crystalline semiconductor layer of the second structure to expose a back surface of the vertical pillar and the gate; and A source is formed on the exposed backside of the vertical pillar.

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