Memory test circuit

Abstract

The invention provides a memory test circuit. The memory test circuit comprises a memory module. The storage module comprises a test power supply end, a current test end, a test interface, a memory, a selector, a test logic module and a control module, the test interface is connected with the test logic module, and the current test end is connected with the memory. And when the storage module is in a working mode, the selector connects the memory with the control module. The memory module enters a test mode through a test command, when the memory module is in the test mode, the test power supply end supplies power to the memory, the selector connects the test logic module with the memory, and the test logic module is connected with the memory. And performing serial communication with the test logic module through the test interface to test the storage module. Therefore, the performance of the memory under different conditions can be detected, and the chips which cannot reach various performance indexes can be screened out, so that the subsequent packaging cost is saved.

Description

[Technical field]

[0001] The present invention relates to the field of memory, and in particular to a memory test circuit. [Background technology]

[0002] Among the memories used in integrated circuits, the SRAM (static random access memory) has a BIST (built-in self-test) circuit to ensure that there are no problems in the manufacturing of the memory. EFLASH (embedded Flash) manufacturers also provide IP (Intellectual Property) test circuits. OTP (One time programable) memories, which are one-time programmable memories, do not require dedicated test circuits. As a memory that can be programmed many times, FTP (few time program) memories need to be tested for many of their performances. However, IP component manufacturers only provide performance indicators for FTP memories, but lack corresponding dedicated test circuits.

[0003] Therefore, it is urgent to propose a new technical solution to solve the above problems. [Summary of the invention]

[0004] One of the objectives of the present invention is to provide a memory test circuit that can detect the performance of the memory under different conditions.

[0005] According to one aspect of the present invention, the present invention provides a memory test circuit, which includes a memory module, wherein the memory module includes a test power supply terminal, a current test terminal, a test interface, a memory, a selector, a test logic module and a control module, wherein the test interface is connected to the test logic module, and the current test terminal is connected to the memory. When the memory module is in an operating mode, the selector connects the memory and the control module, and enables the memory module to enter a test mode through a test command. When the memory module is in a test mode, the test power supply terminal supplies power to the memory, and the selector connects the test logic module and the memory, and performs serial communication with the test logic module through the test interface to implement testing of the memory module.

[0006] Compared with the prior art, in the present invention, when the storage module is in the working mode, the selector connects the memory and the control module; when the storage module is in the test mode, the test power supply end supplies power to the memory; the selector connects the test logic module and the memory, and serial communication is performed with the test logic module through the test interface to implement the test of the storage module, thereby detecting the performance of the memory under different conditions.

Brief Description of the Drawings

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0008] Figure 1 is a schematic diagram of the structure of a memory test circuit in one embodiment of the present invention;

[0009] Figure 2 A schematic diagram of the format of the access command supported by the custom protocol in the present invention;

[0010] Figure 3 It is the register address of each address register in the test logic module of the present invention and its function description. [Specific implementation method]

[0011] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] The "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. The "in one embodiment" that appears in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments. In the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", "coupled" and other terms indicating electrical connection should be understood in a broad sense; for example, it can be a direct electrical connection, or it can be indirectly electrically connected through an intermediate medium, and the intermediate medium can be an electronic component, a functional circuit, etc. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0013] The invention provides a memory test circuit which can detect the performance of the memory under different conditions. Figure 1 FIG. 1 is a schematic diagram of the structure of a memory test circuit in an embodiment of the present invention.

[0014] like Figure 1As shown, the memory test circuit includes a memory module 100. The memory module 100 includes a test power supply terminal FTP_VDD, current test terminals CP1 and CP2, a test interface TI, a memory 110, a selector 140, a test logic module 130 and a control module 120. The test interface TI is connected to the test logic module 130, and the current test terminals CP1 and CP2 are connected to the memory 110. In this embodiment, there are two current test terminals CP1 and CP2, and in other embodiments, there may be 1, 3 or more current test terminals. Preferably, the memory 110 is an FTP memory, and the FTP memory is used as an example for description below. However, in other embodiments, the memory 110 may also be other types of memories.

[0015] When the storage module 100 is in the working mode, the selector 140 connects the memory 110 and the control module 120 . At this time, the control module 120 communicates with the memory 110 normally to control the memory 110 .

[0016] In one embodiment, the storage module 100 enters the test mode through a test command. When the storage module 100 is in the test mode, the test power supply terminal FTP_VDD supplies power to the memory 110, and the selector 140 connects the test logic module 130 and the memory 110, and performs serial communication with the test logic module 130 through the test interface TI to implement the test of the storage module 100. Preferably, the test command is an I3C common command code (CCC) command that will not be triggered by mistake. Of course, in other embodiments, the test command can also be other commands that are not easily triggered by the user.

[0017] like Figure 1 As shown, the memory test circuit further includes a power switch 210 connected between the memory 110 and the internal power supply DLDO_VDD. When the memory module 100 is in the test mode, the power switch 210 is controlled to be disconnected, and the test power supply terminal FTP_VDD supplies power to the memory 110. When the memory module 100 is in the working mode, the power switch 210 is controlled to be turned on, and the internal power supply DLDO_VDD supplies power to the memory 110. Figure 1 As shown, the power switch 210 is located outside the storage module 100. In other embodiments, the power switch 210 may also be located inside the storage module 100.

[0018] When the storage module 100 is in the test mode, the performance of the memory 110 under different voltages can be observed by changing the voltage of the test power supply terminal FTP_VDD.

[0019] The test interface TI comprises a serial clock terminal test_clk, a serial input terminal data_in and a serial output terminal data_out.

[0020] The test logic module 130 includes a test item selection register, an operation type register, a write data register, a read data register and a memory address register. Figure 3 is the register address and function description of each address register in the test logic module of the present invention. Figure 3 As shown, the register address of the test item selection register is 0, and the test item selection register is used to store the test item currently required; the register address of the operation type register is 1, and the operation type register is used to store the operation type performed on the memory, and the operation type is programming operation (PROG), erase operation (erase) and read operation (read); there are two write data registers, and the register addresses of the two write data registers are 2 and 3 respectively, and the write data register is used to store the data written to the memory; there are two read data registers, and the register addresses of the two read data registers are 4 and 5 respectively, and the read data register is used to store the data read from the memory; the register addresses of the memory address register are 6 respectively, and the register address of the memory address register is used to store the memory address of the memory currently accessed. Of course, in other embodiments, the register addresses of the test item selection register, the operation type register, the write data register, the read data register and the memory address register can be allocated as needed, as long as the corresponding register can be found. In other embodiments, depending on the needs, the number of write data registers and read data registers can also be 1 or more.

[0021] Information is written into the test item selection register, operation type register, write data register or memory address register of the test logic module 130 through the serial input terminal. Data is read out from the read data register of the test logic module 130 through the serial output terminal, or a memory erase completion signal is read out through the serial output terminal, or a memory programming completion signal is read out through the serial output terminal, etc.

[0022] In one embodiment, the test interface TI further includes a register access enable terminal set_mode and a test logic reset terminal ftp_test_rstn. When the register access enable terminal is valid, each register in the test logic module 130 can be accessed. When the test logic reset terminal is valid, the test logic module is reset. For example, the test logic reset terminal is valid at a low level.

[0023] In one embodiment, the test items in the test mode include one or more of a current detection test, an internal clock test, a memory erase test, a memory programming test, and a memory read test.

[0024] The serial clock terminal, the serial input terminal, and the serial output terminal communicate with the test logic module 130 through a series of access commands under a predetermined protocol. Each access command includes a register address field, an access type field, and a data field. The register address field indicates the register address in the test logic module 130 accessed by the current access command, the access type field indicates whether the access type of the current access command is write or read, and the data field of the access command is the data written to the currently accessed register or the data read from the currently accessed register. Figure 2 In the given example, Bit0-bit2 is the register address field, Bit3 is the access type field, 1 indicates write, 0 indicates read, and Bit4-bit11 is the data field. In other examples, the number of bits and the bit position of each field may be adjusted.

[0025] Combination Figure 2 and Figure 3 As shown, when the register address in the register address field of the current access command (for example, the register address is 0) points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write (for example, 1), and the data field of the current access command indicates the test item that needs to be performed currently. As described above, the test items in the test mode include one or more of current detection test, internal clock test, memory erase test, memory programming test, and memory read test, each test item corresponds to a test item code, and the data field of the access command can record the test item code.

[0026] When the register address in the register address field of the current access command (for example, the register address is 6) points to the memory address register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the memory address that currently needs to be tested.

[0027] When the register address in the register address field of the current access command (for example, the register address is 1) points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the operation type of the memory, and the operation types of the memory include programming operation (prog), erasing operation (erase) and reading operation (read).

[0028] When the register address in the register address field of the current access command (for example, the register address is 2 or 3) points to the write data register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the data written to the write data register.

[0029] When the register address in the register address field of the current access command (for example, the register address is 4 or 5) points to the read data register, the access type field of the current access command indicates that the access type of the current access command is read (for example, 0), and the data field of the current access command indicates the data read from the read data register.

[0030] Information is written to the test item selection register, operation type register, write data register and memory address register of the test logic module 130 through the serial input terminal, and data is read from the read data register of the test logic module 130 through the serial output terminal.

[0031] In one embodiment, in the test mode, performing a current detection test on the memory 110 includes:

[0032] Outputting the current of the memory 110 through the current test terminals CP1 and CP2 to measure the current value in an idle state;

[0033] When a current detection test is required, an access command is sent to the test logic module 130 through the serial input terminal, and the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that a current detection test is currently required;

[0034] The next access command is sent to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the memory address register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the memory address that needs to be tested currently,

[0035] The current of the storage unit corresponding to the memory address is output and measured through the current test terminal.

[0036] In one embodiment, in the test mode, performing an internal clock test on the memory includes:

[0037] When an internal clock test is required, an access command is sent to the test logic module 130 through the serial input terminal, and the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that an internal clock test is currently required;

[0038] observing an internal clock of the memory via the serial output terminal;

[0039] The observed internal clock of the memory is compared to an expected frequency.

[0040] The memory erase test includes a memory bulk erase test and a memory specific address erase test.

[0041] In one embodiment, in the test mode, performing a memory batch erase test on the memory 110 includes:

[0042] When a memory batch erase test is required, an access command is sent to the test logic module 130 through the serial input terminal, and the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that a memory batch erase test is currently required;

[0043] Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that the operation type of the memory is an erase operation;

[0044] The test logic module 130 performs a memory batch erase operation;

[0045] A memory erase completion signal is led out through the serial output terminal to observe whether the erase time reaches the expectation.

[0046] In one embodiment, in the test mode, erasing a specific memory address of the memory 110 includes:

[0047] When it is necessary to perform erasing of a specific memory address, an access command is sent to the test logic module 130 through the serial input terminal, at which time the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that a specific memory address erasing test is currently required;

[0048] Sending a next access command to the test logic module through the serial input terminal, wherein the register address in the register address field of the current access command points to the memory address register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the memory address that currently needs to be erased;

[0049] Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that the operation type of the memory is an erase operation;

[0050] The test logic module performs an erase operation;

[0051] A memory erase completion signal is led out through the serial output terminal to observe whether the erase time reaches the expectation.

[0052] In one embodiment, in the test mode, performing a read memory test on the memory includes:

[0053] When a read memory test is required, an access command is sent to the test logic module through the serial input terminal, at which time the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that a read memory test is currently required;

[0054] Sending a next access command to the test logic module through the serial input terminal, wherein the register address in the register address field of the current access command points to the memory address register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the memory address currently to be read;

[0055] Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that the operation type of the memory is a read operation;

[0056] The test logic module performs a read operation to read data from a memory address of the memory into the read data register;

[0057] The serial input terminal and the serial output terminal communicate with the test logic module via an access command, the register address in the register address field of the current access command points to the read data register, the access type field of the current access command indicates that the access type of the current access command is read, the data field of the current access command indicates the data read from the read data register, and the data read from the read data register is led out from the serial output terminal.

[0058] In one embodiment, the memory programming test includes a memory full write 1 or 0 test, a memory even address write predetermined data test, a memory odd address write predetermined data test, and a memory specific address write specific data test. The predetermined data in the memory even address write predetermined data test can be 5555, and the predetermined data in the memory odd address write predetermined data test can be AAAA.

[0059] In one embodiment, in the test mode, performing a memory full write 1 or 0 test, a memory even address write predetermined data test, or a memory odd address write predetermined data test on the memory includes:

[0060] When it is necessary to perform a memory full write 1 or 0 test, a memory even address write predetermined data test, or a memory odd address write predetermined data test on the memory, an access command is sent to the test logic module through the serial input terminal, and the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that it is currently necessary to perform a memory full write 1 or 0 test, a memory even address write predetermined data test, or a memory odd address write predetermined data test;

[0061] Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that the operation type of the memory is a programming operation;

[0062] The test logic module executes a memory full write 1 or 0 operation, a memory even address write predetermined data operation or a memory odd address write predetermined data operation;

[0063] A memory programming completion signal is led out through the serial output terminal to observe whether the programming completion time reaches the expectation.

[0064] In one embodiment, in the test mode, performing a memory specific address write specific data test on the memory includes:

[0065] When a test of writing specific data to a specific memory address is required, an access command is sent to the test logic module through the serial input terminal, and the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that a test of writing specific data to a specific memory address is currently required;

[0066] Sending a next access command to the test logic module through the serial input terminal, wherein the register address in the register address field of the current access command points to the memory address register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the memory address currently to be programmed;

[0067] Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the write data register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates data written into the write data register;

[0068] Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that the operation type of the memory is a programming operation;

[0069] The test logic module executes the programming operation to write the data in the write data register into a storage unit of the memory corresponding to the memory address in the memory address register;

[0070] A memory programming completion signal is led out through the serial output terminal to observe whether the programming completion time reaches the expectation.

[0071] Through the dedicated test circuit, the internal clock frequency of FTP is observed, the driving voltage of FTP is changed, and the erase, program and read operations are performed on FTP. The performance of FTP under different conditions is monitored, and chips that fail to meet various performance indicators are screened out, thereby saving subsequent packaging costs.

[0072] It can be seen that based on the memory test circuit, various tests can be completed on the memory under different voltages, the internal clock frequency of the memory can be observed, erasing, programming and reading operations can be performed on the memory, the performance of the memory under different conditions can be monitored, and chips that do not meet various performance indicators can be screened out, thereby saving subsequent packaging costs and ensuring that the memory has good erase, write and read performance in subsequent working modes.

[0073] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0074] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify and vary the above embodiments within the scope of the present invention.

Claims

1. A memory test circuit, characterized in that: It includes a memory module, The storage module includes a test power supply terminal, a current test terminal, a test interface, a memory, a selector, a test logic module and a control module. The test interface is connected to the test logic module, and the current test terminal is connected to the memory. When the storage module is in working mode, the selector connects the memory and the control module. The storage module enters the test mode through a test command. When the storage module is in the test mode, the test power supply end supplies power to the memory, the selector connects the test logic module and the memory, and serial communication is performed with the test logic module through the test interface to implement the test of the storage module.

2. The memory test circuit according to claim 1, characterized in that: The memory test circuit also includes a power switch connected between the memory and an internal power supply. When the memory module is in a test mode, the power switch is controlled to be disconnected, and the test power supply terminal supplies power to the memory. When the memory module is in a working mode, the power switch is controlled to be turned on, and the internal power supply supplies power to the memory. When the storage module is in the test mode, the voltage of the test power supply terminal is changed to observe the performance of the memory under different voltages.

3. The memory test circuit according to claim 2, characterized in that: The storage device is an FTP storage device. The power switch is located inside or outside the storage module, The test command is an I3C general command code command that will not be triggered by mistake.

4. The memory test circuit according to claim 1, wherein: The test interface includes a serial clock terminal, a serial input terminal and a serial output terminal. The test logic module includes a test item selection register, an operation type register, a write data register, a read data register and a memory address register. Write information to the test item selection register, the operation type register, the write data register or the memory address register of the test logic module through the serial input terminal, Data is read out from the read data register of the test logic module through the serial output terminal, or a memory erase completion signal is read out through the serial output terminal, or a memory programming completion signal is read out through the serial output terminal.

5. The memory test circuit according to claim 4, characterized in that: The test items in the test mode include one or more of a current detection test, an internal clock test, a memory erase test, a memory programming test, and a memory read test. The serial clock terminal, the serial input terminal, and the serial output terminal communicate with the test logic module through a series of access commands under a predetermined protocol, each access command includes a register address field, an access type field, and a data field, the register address field indicates the register address in the test logic module accessed by the current access command, the access type field indicates that the access type of the current access command is write or read, and the data field of the access command is data written to the register currently accessed or data read from the register currently accessed, When the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the test item that needs to be performed currently. When the register address in the register address field of the current access command points to the memory address register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the memory address currently to be tested. When the register address in the register address field of the current access command points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the operation type of the memory, and the operation type of the memory includes programming operation, erasing operation and reading operation, When the register address in the register address field of the current access command points to the write data register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the data written into the write data register, When the register address in the register address field of the current access command points to the read data register, the access type field of the current access command indicates that the access type of the current access command is read, and the data field of the current access command indicates the data read from the read data register, Information is written to the test item selection register, operation type register, write data register and memory address register of the test logic module through the serial input end, and data is read from the read data register of the test logic module through the serial output end.

6. The memory test circuit according to claim 5, characterized in that: In the test mode, performing a current detection test on the memory includes: Outputting the current of the memory through the current testing terminal to measure the current value in an idle state; When a current detection test is required, an access command is sent to the test logic module through the serial input terminal, at which time the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that a current detection test is currently required; The next access command is sent to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the memory address register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the memory address that needs to be tested currently, The current of the storage unit corresponding to the memory address is output and measured through the current test terminal.

7. The memory test circuit according to claim 5, characterized in that: In the test mode, performing an internal clock test on the memory includes: When an internal clock test is required, an access command is sent to the test logic module through the serial input terminal, at which time the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that an internal clock test is currently required; observing an internal clock of the memory via the serial output terminal; The observed internal clock of the memory is compared to an expected frequency.

8. The memory test circuit according to claim 5, characterized in that: The memory erase test includes a memory bulk erase test and a memory specific address erase test. In the test mode, performing a memory batch erasure test on the memory includes: When a memory batch erase test is required, an access command is sent to the test logic module through the serial input terminal, at which time the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that a memory batch erase test is currently required; Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that the operation type of the memory is an erase operation; The test logic module performs a memory batch erase operation; Leading out a memory erase completion signal through the serial output terminal to observe whether the erase time reaches the expectation; In the test mode, erasing a specific address of the memory includes: When it is necessary to perform erasure of a specific address of the memory, an access command is sent to the test logic module through the serial input terminal, at which time the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that a specific address erasure test of the memory is currently required; Sending a next access command to the test logic module through the serial input terminal, wherein the register address in the register address field of the current access command points to the memory address register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the memory address that currently needs to be erased; Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that the operation type of the memory is an erase operation; The test logic module performs an erase operation; A memory erase completion signal is led out through the serial output terminal to observe whether the erase time reaches the expectation.

9. The memory test circuit according to claim 5, characterized in that: In the test mode, performing a read memory test on the memory includes: When a read memory test is required, an access command is sent to the test logic module through the serial input terminal, at which time the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that a read memory test is currently required; Sending a next access command to the test logic module through the serial input terminal, wherein the register address in the register address field of the current access command points to the memory address register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the memory address currently to be read; Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that the operation type of the memory is a read operation; The test logic module performs a read operation to read data from a memory address of the memory into the read data register; The serial input terminal and the serial output terminal communicate with the test logic module through an access command, the register address in the register address field of the current access command points to the read data register, the access type field of the current access command indicates that the access type of the current access command is read, and the data field of the current access command indicates the data read from the read data register, and the data read from the read data register is drawn out from the serial output terminal.

10. The memory test circuit according to claim 5, characterized in that: The memory programming test includes a memory full write 1 or 0 test, a memory even address write predetermined data test, a memory odd address write predetermined data test, and a memory specific address write specific data test. In the test mode, performing a memory full write 1 or 0 test, a memory even address write predetermined data test, or a memory odd address write predetermined data test on the memory includes: When it is necessary to perform a memory full write 1 or 0 test, a memory even address write predetermined data test, or a memory odd address write predetermined data test on the memory, an access command is sent to the test logic module through the serial input terminal, and the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that it is currently necessary to perform a memory full write 1 or 0 test, a memory even address write predetermined data test, or a memory odd address write predetermined data test; Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that the operation type of the memory is a programming operation; The test logic module executes a memory full write 1 or 0 operation, a memory even address write predetermined data operation or a memory odd address write predetermined data operation; Leading out a memory programming completion signal through the serial output terminal to observe whether the programming completion time reaches the expectation; In the test mode, performing a memory specific address write specific data test on the memory includes: When a test of writing specific data to a specific memory address is required, an access command is sent to the test logic module through the serial input terminal, and the register address in the register address field of the current access command points to the test item selection register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that a test of writing specific data to a specific memory address is currently required; Sending a next access command to the test logic module through the serial input terminal, wherein the register address in the register address field of the current access command points to the memory address register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates the memory address currently to be programmed; Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the write data register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates data written into the write data register; Sending a next access command to the test logic module through the serial input terminal, the register address in the register address field of the current access command points to the operation type register, the access type field of the current access command indicates that the access type of the current access command is write, and the data field of the current access command indicates that the operation type of the memory is a programming operation; The test logic module executes the programming operation to write the data in the write data register into a storage unit of the memory corresponding to the memory address in the memory address register; A memory programming completion signal is led out through the serial output terminal to observe whether the programming completion time reaches the expectation.

11. The memory test circuit according to claim 4, characterized in that: The test interface also includes a register access enable terminal and a test logic reset terminal. Each register in the test logic module can be accessed only when the register access enable terminal is valid. When the test logic reset terminal is valid, the test logic module is reset.

Images