Consistency verification method, system and equipment of storage chip and storage medium

Abstract

The embodiment of the invention provides a consistency verification method, system and equipment of a storage chip and a storage medium, and belongs to the technical field of memories. The method comprises the following steps: controlling a mechanical arm to respectively place a plurality of to-be-verified storage chips on a preset test fixture; loading a preset tuning test assembly to each storage chip placed on the test fixture through the first terminal equipment, issuing various different reset instructions to obtain execution results of the reset instructions, and obtaining consistency verification data according to the tuning logs and the execution results; the multiple storage chips can be sequentially fed to the test jig through the mechanical arm, and the storage chips are detachably installed on the first terminal equipment through the test jig to be tested. And meanwhile, by configuring the tuning test component, the consistency of the production process of the storage chip can be verified while function verification is performed through different reset instructions, so that the consistency verification efficiency of the storage chip is improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a consistency verification method, system, device and storage medium for a memory chip. Background Art

[0002] In the field of memory technology, in order to ensure the factory quality of memory chips, it is often necessary to conduct consistency testing on memory chips to ensure the consistency of quality of each memory chip during the production process. Among them, the consistency test needs to verify the functional consistency and production process consistency of batches of memory chips. However, in actual applications, the consistency of memory chips is often tested manually for functional consistency and production process consistency, resulting in low test efficiency. Therefore, how to improve the efficiency of memory chip consistency verification is a technical problem that needs to be solved urgently. Summary of the invention

[0003] The main purpose of the embodiments of the present application is to provide a consistency verification method, system, device and storage medium for a storage chip, which can improve the consistency verification efficiency of the storage chip.

[0004] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application proposes a consistency verification method for a memory chip, the method comprising: Controlling the mechanical arm to place the multiple memory chips to be verified on a preset test fixture respectively; wherein the test fixture is detachably connected to the first terminal device, and the test fixture is used to electrically connect the memory chip to the mainboard of the first terminal device; Performing a test step on each memory chip placed on the test fixture to obtain a test result corresponding to each memory chip; Obtaining consistency verification data according to the test results of each of the memory chips; The test result of each memory chip is determined by the following steps: The storage chip is loaded with a preset tuning test component through the first terminal device; wherein the tuning test component is used to perform a tuning test on the storage chip during the startup process of the storage chip and save the result of the tuning test as a tuning log in a preset storage path; Sending a plurality of different reset instructions to the storage chip through the first terminal device to obtain execution results of the reset instructions, wherein the execution results are used to represent the execution status of the corresponding reset instructions; The test result is obtained according to each of the tuning logs and each of the execution results.

[0005] To achieve the above-mentioned purpose, a second aspect of an embodiment of the present application proposes a consistency verification system for a memory chip, comprising: Robotic arm; A first terminal device, wherein a detachable test fixture is provided on the first terminal device, and the test fixture is used to electrically connect the storage chip to a mainboard of the first terminal device; A second terminal device, wherein the second terminal device executes the method according to the first aspect.

[0006] To achieve the above-mentioned purpose, the third aspect of an embodiment of the present application proposes an electronic device, which includes a memory and a processor, the memory stores a computer program, and the processor implements the consistency verification method of the storage chip described in the first aspect when executing the computer program.

[0007] To achieve the above-mentioned purpose, the fourth aspect of an embodiment of the present application proposes a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the consistency verification method of the storage chip described in any one of the first aspects.

[0008] The consistency verification method, system, device and storage medium of the memory chip proposed in the present application can realize the sequential loading of multiple memory chips into the test fixture through the mechanical arm, and the memory chip can be detachably installed on the first terminal device for testing through the test fixture. At the same time, by configuring the tuning test component, the consistency of the production process of the memory chip can be verified while the function is verified through different reset instructions. Therefore, compared with the related art, the embodiment of the present application can improve the efficiency of consistency verification of memory chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a flowchart of a consistency verification method for a memory chip provided in an embodiment of the present application; Figure 2 It is a structural diagram of a system corresponding to the consistency verification method of a memory chip provided in an embodiment of the present application; Figure 3 It is a flowchart of an embodiment of a method for verifying the consistency of a memory chip provided in an embodiment of the present application; Figure 4 It is a structural diagram of the hardware structure corresponding to the consistency verification method of the storage chip provided in the embodiment of the present application. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0011] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0012] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0013] First, some nouns involved in this application are analyzed: Embedded Multi Media Card, also known as eMMC, is an integrated storage chip that is commonly used in embedded systems, smartphones, tablets, cameras and other portable devices.

[0014] In the field of memory technology, in order to ensure the factory quality of memory chips, it is often necessary to perform consistency testing on memory chips to ensure the consistency of quality of each memory chip during the production process. Among them, the consistency test needs to verify the functional consistency and production process consistency of batches of memory chips. However, in actual applications, the consistency of memory chips is often tested manually for functional consistency and production process consistency, resulting in low test efficiency. Therefore, how to improve the efficiency of memory chip consistency verification is a technical problem that needs to be solved urgently. Based on this, a memory chip consistency verification method, system, device and storage medium are proposed, which can improve the verification efficiency of the consistency of memory chips.

[0015] The consistency verification method, system, device and storage medium of the storage chip provided in the embodiments of the present application are specifically described through the following embodiments. First, the consistency verification method of the storage chip in the embodiments of the present application is described.

[0016] The consistency verification method of the memory chip of the present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld devices or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0017] Refer to the following Figure 1 As shown, according to the consistency verification method of the memory chip provided in the embodiment of the present application, the consistency verification method of the memory chip includes: Step S100, controlling the mechanical arm to place the plurality of memory chips to be verified on a preset test fixture respectively; wherein the test fixture is detachably connected to the first terminal device, and the test fixture is used to electrically connect the memory chip to the mainboard of the first terminal device; Step S200, executing a test step for each memory chip placed on the test fixture to obtain a test result corresponding to each memory chip; Step S300, obtaining consistency verification data according to the test results of each memory chip; The test result of each memory chip is determined by the following steps: Step S210: enabling the storage chip to load a preset tuning test component through the first terminal device; wherein the tuning test component is used to perform a tuning test on the storage chip during the startup process of the storage chip and save the result of the tuning test as a tuning log in a preset storage path; Step S220: Sending a plurality of different reset instructions to the storage chip through the first terminal device to obtain the execution result of each reset instruction, where the execution result is used to characterize the execution status of the corresponding reset instruction; Step S230: Obtain test results according to each tuning log and each execution result.

[0018] Therefore, a plurality of memory chips can be sequentially loaded into the test fixture through the robotic arm, and the memory chips can be detachably installed on the first terminal device for testing through the test fixture. At the same time, by configuring the tuning test component, the memory chip can be verified for consistency of production process while performing functional verification through different reset instructions. Therefore, compared with the related art, the embodiment of the present application can improve the efficiency of consistency verification of memory chips.

[0019] It is understandable that the storage chip may be an eMMC chip.

[0020] It is understandable that the tuning test component is a test based on the tuning interface supported by the memory chip, such as sampling the data of the memory chip bus (taking EMMC as an example, the bus includes command lines, data lines, and clock lines), such as sampling of read and write operations, and sampling of device initialization, and then determining whether the production process parameters are consistent based on the log generated by the sampled data. The present application embodiment does not elaborate on what the tuning test component is specifically, and those skilled in the art can selectively set it according to actual needs.

[0021] The consistency verification data indicates whether the test feedback of each memory chip for the same test item is consistent and whether it meets the expected verification result. In the embodiment of the present application, how to obtain the consistency verification data in step S300 is not described one by one.

[0022] The reset instruction in step S220 represents an instruction that can cause the memory chip to reset, which can be a soft reset (such as restarting a program) or a hard reset (such as simulating a power failure). There is no limit on the number of times the same reset instruction can be issued to each memory chip.

[0023] A gap is left between two adjacent reset instructions to ensure that the memory chip receives the reset instruction when it is operating normally.

[0024] The consistency verification method of the storage chip of the present application is applied to the second terminal device. The embodiment of the present application does not limit the types of the second terminal device and the first terminal device. They can both be PC terminals, one can be a PC terminal and the other can be a laptop computer, and so on.

[0025] It is understandable that the first terminal device and the test fixture are detachably connected, so that when the first terminal device is abnormal, the test fixture can be quickly replaced, thereby ensuring verification efficiency.

[0026] It is understandable that the tuning test component is loaded by the flashing instruction issued by the first terminal device; wherein, a plurality of different reset instructions are issued to the storage chip by the first terminal device, and the execution results of each reset instruction are obtained, including: Sending a restart instruction to the storage chip through the first terminal device to obtain an execution result of the restart instruction; A recovery instruction is sent to the storage chip through the first terminal device to obtain an execution result of the recovery instruction.

[0027] Among them, according to each tuning log and each execution result, the test results are obtained, including: The test results are obtained based on the tuning logs corresponding to the flashing instructions, restart instructions, and recovery instructions and the execution results corresponding to the flashing instructions, restart instructions, and recovery instructions.

[0028] It is understandable that the flash command (also known as the fastboot command) can be used to reinstall the system; the restart command (also known as the reboot command) is used for soft reset, and the recovery command (also known as the recovery command) can be used for backup and recovery. Since the storage chip is initially a blank chip without an operating system, the software package can be loaded by issuing the flash command to load the tuning test component and load the program for the normal operation of the storage chip. Then, the reset can be triggered in sequence by the restart command and the recovery command, thereby simulating the actual application process, improving the verification efficiency while ensuring the reliability of the verification effect.

[0029] It is understandable that the first terminal device sends a plurality of different reset instructions to the storage chip to obtain the execution results of each reset instruction, including: Obtaining a preset number of tests and a test script, wherein the test script defines a plurality of different reset instructions sent to the storage chip by the first terminal device; According to the number of tests, the test script is repeatedly executed to obtain the execution results of each reset instruction; When the number of test script executions is equal to the number of tests, stop executing the test steps on the memory chip.

[0030] By repeatedly executing the reset instruction multiple times, the reliability of the execution result can be further improved.

[0031] Exemplarily, assuming that the number of tests is set to 10, executing the flash command, restart command, and recovery command once each means completing a test, and the number of executions is increased by 1. When the cumulative number of executions reaches 10, the test of the next memory chip is started.

[0032] It is understandable that the steps of stopping execution of the memory chip include: During a first preset time period, stop issuing instructions to the storage chip, wherein the first preset time period is greater than the time period for the robot arm to replace the storage chip.

[0033] It is understandable that the number of tests and the first preset duration can be selectively set according to actual conditions, and the present application embodiment does not limit this. For example, it can be determined by historical experience data.

[0034] By setting the first preset time length, it can be ensured that when the mechanical arm is replacing the storage chip, the second terminal device is in a state of suspending the test, so as to ensure the accuracy of the test result.

[0035] It is understandable that the memory chip supports multiple rate modes, and multiple different reset instructions are sent to the memory chip by the first terminal device to obtain the execution result of each reset instruction, which also includes: Sending a plurality of different reset instructions to storage chips in different rate modes through the first terminal device to obtain the execution result of each reset instruction in each rate mode; According to each tuning log and each execution result, the test results are obtained, including: Collect statistics on tuning logs and execution results in each rate mode to determine the test results.

[0036] It is understandable that the tuning logs and execution results in each rate mode are counted separately to determine the test results, including: Create a blank table tab page corresponding to each rate mode; Match the tuning logs corresponding to each rate mode with the expected data, and write the matching results to the corresponding table tab; The test result is determined according to the updated table tab and each execution result.

[0037] By adding tests in different rate modes, the reliability of the test results can be further ensured, and by automatically matching and parsing the tuning logs, the efficiency of test result statistics can be further improved.

[0038] The expected data is used to indicate that the result in the tuning log is valid. The embodiments of the present application do not describe the expected data one by one, and those skilled in the art can selectively set it according to actual needs.

[0039] Exemplarily, taking eMMC as an example, the rate modes it supports include ddr50, hs200, hs400, hs401 and sdr25. Different reset instructions will be issued in the ddr50 rate mode to obtain the execution result and tuning log in the ddr50 rate mode. In the hs200 mode, the same reset instruction as the ddr50 rate mode is issued, and the execution result and tuning log in the ddr50 mode are obtained. In the hs400 mode, the same reset instruction as the ddr50 rate mode is issued, and the execution result and tuning log in the hs200 mode are obtained. In the hs401 mode, the same reset instruction as the ddr50 rate mode is issued, and the execution result and tuning log in the hs400 mode are obtained. In the sdr25 mode, the same reset instruction as the ddr50 rate mode is issued, and the execution result and tuning log in the hs401 mode are obtained. At this time, the results are shown in Table 1 below:

[0040] Table 1 As shown in Table 1 above, the column where particles 1 to particles n are located is used to record the matching result of a corresponding memory chip. The first row corresponds to the tab page of different rate modes, and particles 1 to particles n are chip identifiers of the memory chips.

[0041] It is understandable that the tuning log corresponding to each rate mode is matched with the expected data, and the matching results are written to the corresponding table tab, including: Starting from the first row for recording the matching results in each table tab page, the fill color of cells of a preset number of rows in each table tab page is initialized to a first color; Associating the row numbers of each table tab with the corresponding tuning log row numbers one by one; Get the chip ID corresponding to the tuning log; Traverse each row of each tuning log, match each row of log data with the expected data, and update the color of the corresponding target cell according to the matching result. The row number of the target cell is the same as the traversed row number and the column number of the target cell corresponds to the chip ID corresponding to the tuning log.

[0042] It is understandable that when the match is successful, the color of the target cell is set to the second color, and the first color and the second color are different. The embodiment of the present application does not limit the first color and the second color, such as the first color is set to red and the second color is set to green.

[0043] For example, referring to Table 1, assuming that the chip identifier is particle 1, and the tuning log rate mode is a log under ddr50, for the first row of log data traversed, the target cell is updated according to the matching result of the first row of log data, and the column of the target cell is the column where particle 1 is located, and the third row of the behavior data tab of the target cell.

[0044] Understandably, referring to Figure 2 As shown, a consistency verification system for a memory chip provided by the present application includes: Robotic arm 100; A first terminal device 200, wherein a detachable test fixture 300 is provided on the first terminal device 200, and the test fixture 300 is used to electrically connect the storage chip to the mainboard of the first terminal device; The second terminal device 400 executes the above method.

[0045] It is understandable that, in some embodiments, the consistency verification system for memory chips further includes a chip tray 500 , and the chip tray 500 is used for batch loading of memory chips.

[0046] For example, refer to Figure 3 As shown, assuming that N memory chips are tested, the specific steps are as follows: S1: Consistency verification system assembly, as follows: S1.1. Place multiple memory chips to be verified on a chip tray for fixing memory chips; S1.2. Install the test fixture on the first terminal device; S1.3, loading a program for moving and placing a memory chip to a test fixture into the robot arm; the program sets the configuration of the suction force of the robot arm to absorb the memory chip, and the program is used to drive the robot arm to move the memory chip from the chip tray to the test fixture; S2: Control the robot arm to take out a memory chip from the chip tray and place it on the test fixture; S3: The second terminal device sequentially sends a flashing instruction, a restart instruction, and a recovery instruction to the first terminal device through the serial port, so as to sequentially send a flashing instruction, a restart instruction, and a recovery instruction to the storage chip through the first terminal; wherein the program loaded in the flashing instruction includes a tuning test component; S4: Save the test results, which include the tuning log and execution results of each instruction in the flash instruction, the restart instruction, and the recovery instruction.

[0047] S5: Determine whether all the memory chips to be verified have been tested. If not, jump to step 2 to update the memory chips to be updated on the test fixture. S6: Statistically analyze the test results of each memory chip to obtain consistency verification data.

[0048] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the consistency verification method of the above storage chip when executing the computer program. The electronic device can be any smart terminal including a tablet computer, a car computer, etc.

[0049] See also Figure 4 , Figure 4 The hardware structure of an electronic device of another embodiment is illustrated, and the electronic device includes: The processor 601 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application; The memory 602 may be a NAND flash, and the relevant program code is stored in the memory 602, and the processor 601 calls and executes the consistency verification method of the memory chip according to the embodiment of the present application; Input / output interface 603, used to implement information input and output; Communication interface 604, used to realize communication interaction between the device and other devices, which can be realized through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.); A bus 605 that transmits information between various components of the device (e.g., processor 601, memory 602, input / output interface 603, and communication interface 604); The processor 601 , the memory 602 , the input / output interface 603 and the communication interface 604 are connected to each other in communication within the device via a bus 605 .

[0050] An embodiment of the present application also provides a computer-readable storage medium, which is a computer-readable storage medium that stores a computer program. When the computer program is executed by a processor, the consistency verification method of the above-mentioned storage chip is implemented.

[0051] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0052] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0053] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0054] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0055] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0056] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0057] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0058] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0059] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0060] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0061] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0062] The preferred embodiments of the present application are described above with reference to the accompanying drawings, but the scope of the rights of the present application is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present application should be within the scope of the rights of the present application.

Claims

1. A consistency verification method for a memory chip, characterized in that: The method comprises: Controlling the mechanical arm to place the multiple memory chips to be verified on a preset test fixture respectively; wherein the test fixture is detachably connected to the first terminal device, and the test fixture is used to electrically connect the memory chip to the mainboard of the first terminal device; Performing a test step on each memory chip placed on the test fixture to obtain a test result corresponding to each memory chip; Obtaining consistency verification data according to the test results of each of the memory chips; The test result of each memory chip is determined by the following steps: The storage chip is loaded with a preset tuning test component through the first terminal device; wherein the tuning test component is used to perform a tuning test on the storage chip during the startup process of the storage chip and save the result of the tuning test as a tuning log in a preset storage path; Sending a plurality of different reset instructions to the storage chip through the first terminal device to obtain execution results of the reset instructions, wherein the execution results are used to represent the execution status of the corresponding reset instructions; The test result is obtained according to each of the tuning logs and each of the execution results.

2. The consistency verification method of a memory chip according to claim 1, characterized in that: The tuning test component is loaded by the flashing instruction issued by the first terminal device; the first terminal device issues a plurality of different reset instructions to the storage chip to obtain the execution result of each reset instruction, including: Sending a restart instruction to the storage chip through the first terminal device to obtain an execution result of the restart instruction; Sending a recovery instruction to the storage chip through the first terminal device to obtain an execution result of the recovery instruction; The step of obtaining the test result according to each of the tuning logs and each of the execution results includes: The test result is obtained according to the tuning logs corresponding to the flashing instruction, the restart instruction, and the recovery instruction and the execution results corresponding to the flashing instruction, the restart instruction, and the recovery instruction.

3. The consistency verification method of a memory chip according to claim 1, characterized in that: The sending of a plurality of different reset instructions to the storage chip through the first terminal device to obtain the execution result of each of the reset instructions includes: Obtaining a preset number of tests and a test script, wherein the test script defines a plurality of different reset instructions sent to the storage chip by the first terminal device; According to the test number, repeatedly executing the test script to obtain the execution result of each reset instruction; When the execution times of the test script is equal to the test times, the execution of the test steps on the memory chip is stopped.

4. The consistency verification method of a memory chip according to claim 3, characterized in that: The step of stopping execution of the storage chip comprises: During a first preset time period, stop issuing instructions to the current storage chip, wherein the first preset time period is greater than the time period for the robot arm to replace the storage chip.

5. The consistency verification method of a memory chip according to claim 1, characterized in that: The storage chip supports multiple rate modes, and the first terminal device sends multiple different reset instructions to the storage chip to obtain the execution result of each reset instruction, and further includes: Sending a plurality of different reset instructions to the storage chip in different rate modes through the first terminal device to obtain the execution result of each reset instruction in each rate mode; The step of obtaining the test result according to each of the tuning logs and each of the execution results includes: The tuning logs and the execution results in each rate mode are counted respectively to determine the test result.

6. The consistency verification method of a memory chip according to claim 5, characterized in that: The respectively counting the tuning logs and the execution results in each rate mode to determine the test result includes: Create a blank table tab page corresponding to each of the rate modes; Match the tuning log corresponding to each rate mode with expected data, and write the matching result to the corresponding table tab; The test result is determined according to the updated table tab page and each of the execution results.

7. The consistency verification method of a memory chip according to claim 6, characterized in that: The step of matching the tuning log corresponding to each rate mode with expected data and writing the matching result to the corresponding table tab page includes: Starting from the first row for recording the matching results in each of the table tab pages, the fill colors of cells of a preset number of rows in each of the table tab pages are initialized to a first color; Associating the row number of each table tab page with the row number of the corresponding tuning log one by one; Obtain the chip identifier corresponding to the tuning log; Each row of each tuning log is traversed, each row of log data traversed is matched with the expected data, and the color of the corresponding target cell is updated according to the matching result, the row number of the target cell is the same as the traversed row number and the column number of the target cell corresponds to the chip identifier corresponding to the tuning log.

8. A consistency verification system for a storage chip, characterized in that: include: Robotic arm; A first terminal device, wherein a detachable test fixture is provided on the first terminal device, and the test fixture is used to electrically connect the storage chip to a mainboard of the first terminal device; A second terminal device, wherein the second terminal device executes the method according to claim 1.

9. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the consistency verification method of the storage chip according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the consistency verification method of the memory chip according to any one of claims 1 to 7 is implemented.

Images