Memory chip consistency verification method, system, device and storage medium

Abstract

The embodiment of the application provides a kind of consistency verification method, system, equipment and storage medium of storage chip, belong to memory technical field;Method includes: control robot to place the multiple storage chips to be verified in the test fixture of pre-set respectively;Each storage chip placed in test fixture is loaded by first terminal equipment with the tuning test component of pre-set and issues multiple different reset instructions, obtains the execution result of each reset instruction, obtains consistency verification data according to each tuning log and each execution result;Through robot, multiple storage chips can be realized in turn to be fed to test fixture, and make that storage chip can be detachably installed in first terminal equipment for testing by test fixture.Simultaneously by configuring tuning test component, it can be verified to the consistency of production process of storage chip while carrying out function verification by different reset instructions, and then the efficiency of consistency verification of storage chip is improved.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a method, system, device and storage medium for conformance verification of memory chips. Background Technology

[0002] In the field of memory technology, to ensure the quality of memory chips upon leaving the factory, conformance testing is often required to ensure the consistency of quality among individual memory chips during the production process. This conformance testing needs to verify the functional consistency and manufacturing process consistency of a batch of memory chips. However, in practice, memory chip conformance is often verified manually, resulting in low testing efficiency. Therefore, improving the efficiency of memory chip conformance verification is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] The main objective of this application is to provide a method, system, device, and storage medium for verifying the consistency of memory chips, which can improve the efficiency of verifying the consistency of memory chips.

[0004] To achieve the above objectives, a first aspect of this application proposes a consistency verification method for a memory chip, the method comprising:

[0005] The robotic arm is controlled to place multiple memory chips to be verified into a preset test fixture; wherein, the test fixture is detachably connected to the first terminal device, and the test fixture is used to electrically connect the memory chips to the motherboard of the first terminal device;

[0006] Perform test steps on each memory chip placed in the test fixture to obtain test results corresponding to each memory chip;

[0007] Based on the test results of each memory chip, consistency verification data is obtained;

[0008] The test results of each memory chip are determined through the following steps:

[0009] The first terminal device loads a preset tuning test component onto the storage chip; wherein, the tuning test component is used to perform a tuning test on the storage chip during the startup process of the storage chip and save the tuning test results as a tuning log in a preset storage path;

[0010] The first terminal device sends multiple different reset commands to the memory chip, and obtains the execution result of each reset command. The execution result is used to characterize the execution status of the corresponding reset command.

[0011] The test results are obtained based on the tuning logs and execution results.

[0012] To achieve the above objectives, a second aspect of this application proposes a consistency verification system for a memory chip, comprising:

[0013] robotic arm;

[0014] A first terminal device is provided with a detachable test fixture, which is used to electrically connect the memory chip to the motherboard of the first terminal device.

[0015] The second terminal device performs the method as described in the first aspect.

[0016] To achieve the above objectives, a third aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the consistency verification method for the memory chip described in the first aspect.

[0017] To achieve the above objectives, a fourth aspect of the present application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the consistency verification method for the memory chip described in any of the first aspects.

[0018] The present application proposes a method, system, device, and storage medium for verifying the conformance of memory chips. This method utilizes a robotic arm to sequentially load multiple memory chips onto a test fixture, which then allows the chips to be detachably mounted on a first terminal device for testing. Furthermore, by configuring a tuning test component, the manufacturing process conformance of the memory chips can be verified simultaneously with functional verification using different reset commands. Therefore, compared to related technologies, the embodiments of this application can improve the efficiency of memory chip conformance verification. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the consistency verification method for memory chips provided in an embodiment of this application;

[0020] Figure 2 This is a schematic diagram of the system corresponding to the consistency verification method for memory chips provided in the embodiments of this application;

[0021] Figure 3 This is a flowchart illustrating one embodiment of the consistency verification method for memory chips provided in this application.

[0022] Figure 4This is a schematic diagram of the hardware structure corresponding to the consistency verification method for the memory chip provided in this application embodiment. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0024] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit the scope of this application.

[0026] First, let's analyze some of the terms used in this application:

[0027] An embedded multimedia card, or eMMC for short, is an integrated memory chip that is typically used in embedded systems, smartphones, tablets, cameras, and other portable devices.

[0028] In the field of memory technology, to ensure the quality of memory chips before they leave the factory, conformance testing is often required to ensure the consistency of quality among individual chips during the production process. This conformance testing needs to verify the functional consistency and manufacturing process consistency of a batch of memory chips. However, in practical applications, the conformance of memory chips is often verified manually, resulting in low testing efficiency. Therefore, improving the efficiency of memory chip conformance verification is a pressing technical problem. Based on this, this paper proposes a conformance verification method, system, device, and storage medium for memory chips, which can improve the efficiency of memory chip conformance verification.

[0029] The consistency verification method, system, device, and storage medium for memory chips provided in this application are specifically described through the following embodiments. First, the consistency verification method for memory chips in this application is described.

[0030] The conformance verification method for memory chips described in this application can be used in numerous general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0031] The following reference Figure 1 As shown, the consistency verification method for a memory chip provided in the embodiments of this application includes:

[0032] Step S100: Control the robotic arm to place the multiple memory chips to be verified into a preset test fixture; wherein, the test fixture is detachably connected to the first terminal device, and the test fixture is used to electrically connect the memory chips to the motherboard of the first terminal device;

[0033] Step S200: Perform test steps on each memory chip placed in the test fixture to obtain test results corresponding to each memory chip.

[0034] Step S300: Obtain consistency verification data based on the test results of each memory chip;

[0035] The test results for each memory chip were determined through the following steps:

[0036] Step S210: Load a preset tuning test component onto the storage chip via the first terminal device; wherein, the tuning test component is used to perform a tuning test on the storage chip during the startup process and save the tuning test results as a tuning log in a preset storage path;

[0037] Step S220: Send multiple different reset commands to the memory chip through the first terminal device, and obtain the execution results of each reset command. The execution results are used to characterize the execution status of the corresponding reset command.

[0038] Step S230: Obtain the test results based on each tuning log and each execution result.

[0039] Therefore, a robotic arm can sequentially load multiple memory chips onto a test fixture, and the test fixture allows the memory chips to be detachably installed on a first terminal device for testing. Simultaneously, by configuring a tuning test component, functional verification can be performed using different reset commands while simultaneously verifying the consistency of the memory chip's manufacturing process. Therefore, compared to related technologies, the embodiments of this application can improve the efficiency of memory chip consistency verification.

[0040] Understandably, the memory chip can be an eMMC chip.

[0041] Understandably, the tuning test component performs tests based on the tuning interface supported by the memory chip. For example, it can sample data from the memory chip's bus (taking eMMC as an example, the bus includes command lines, data lines, and clock lines), such as sampling read / write operations and sampling device initialization. Furthermore, it can determine whether the manufacturing process parameters are consistent based on the log generated from the sampled data. This application does not elaborate on the specifics of the tuning test component; those skilled in the art can selectively configure it according to actual needs.

[0042] The consistency verification data indicates whether the test feedback of each memory chip for the same test item is consistent and whether the expected verification results are met. This application embodiment will not elaborate on how to obtain the consistency verification data in step S300.

[0043] In step S220, the reset instruction represents an instruction that can cause the memory chip to reset. It can be a soft reset (such as program restart) or a hard reset (such as simulated power failure). There is no limit to the number of times the same reset instruction can be issued on each memory chip.

[0044] A gap is left between two adjacent reset commands to ensure that the reset command is received when the memory chip is operating normally.

[0045] The consistency verification method for memory chips in this application is applied to a second terminal device. The embodiments of this application do not limit the types of the second terminal device and the first terminal device. They can both be PC terminals, one can be a PC terminal and the other can be a laptop computer, etc.

[0046] Understandably, the first terminal device and the test fixture are detachably connected, which allows for quick replacement of the test fixture in case of malfunction of the first terminal device, thereby ensuring verification efficiency.

[0047] Understandably, the tuning test component is loaded via flashing commands issued by the first terminal device; specifically, the first terminal device issues various reset commands to the storage chip, and the execution results of each reset command are obtained, including:

[0048] The first terminal device sends a restart command to the storage chip and obtains the execution result of the restart command;

[0049] The first terminal device sends a recovery command to the storage chip and obtains the execution result of the recovery command.

[0050] The test results, obtained from each tuning log and execution result, include:

[0051] The test results are obtained based on the tuning logs corresponding to the flashing, rebooting, and recovery commands, as well as the execution results of the flashing, rebooting, and recovery commands.

[0052] Understandably, the flashing command (i.e., the fastboot command) can be used to reinstall the system; the reboot command (i.e., the reboot command) is used for soft reset; and the recovery command (i.e., the recovery command) can be used for backup and recovery. Since the storage chip is initially a blank chip without an operating system, the flashing command can load the software package, enabling the loading of the tuning test components and the program that normally runs on the storage chip. Then, the reboot and recovery commands can be used to trigger a reset sequentially, thus simulating the actual application process. This improves verification efficiency while ensuring the reliability of the verification results.

[0053] Understandably, the first terminal device sends various reset commands to the memory chip, and the execution results of each reset command are obtained, including:

[0054] Obtain the preset number of tests and the test script, which defines a variety of different reset commands sent to the memory chip through the first terminal device;

[0055] Based on the number of tests, the test script is repeatedly executed to obtain the execution results of each reset instruction;

[0056] When the number of times the test script is executed equals the number of tests, stop performing the test steps on the memory chip.

[0057] By repeatedly executing the reset command multiple times, the reliability of the execution result can be further improved.

[0058] For example, assuming the number of tests is set to 10, executing the flashing command, the reboot command, and the recovery command once each represents completing one test, and the execution count is incremented by 1. When the cumulative execution count reaches 10, the test of the next storage chip begins.

[0059] Understandably, stopping the execution of steps on the memory chip includes:

[0060] Within a first preset duration, instructions to the memory chip are stopped, where the first preset duration is longer than the duration for which the robotic arm replaces the memory chip.

[0061] It is understood that the number of tests and the first preset duration can be selectively set according to actual conditions, and this application embodiment does not impose any restrictions on this. For example, it can be determined through historical experience data.

[0062] By setting a first preset duration, the second terminal device can be kept paused during the replacement of the memory chip by the robotic arm, thus ensuring the accuracy of the test results.

[0063] Understandably, memory chips support multiple speed modes. A first terminal device sends various reset commands to the memory chip, and the execution results of each reset command are obtained, including:

[0064] The first terminal device sends various reset commands to the memory chips in different rate modes, and obtains the execution results of each reset command in each rate mode.

[0065] Based on the tuning logs and execution results, the test results are obtained, including:

[0066] The tuning logs and execution results for each rate mode were analyzed separately to determine the test results.

[0067] Understandably, the testing results are determined by separately analyzing the tuning logs and execution results for each rate mode, including:

[0068] Create blank table tabs that correspond one-to-one with the rate patterns;

[0069] Match the tuning logs corresponding to each rate mode with the expected data, and write the matching results to the corresponding table tab;

[0070] The test results are determined based on the updated table tabs and the execution results.

[0071] By adding tests under different rate modes, the reliability of test results can be further ensured, and by automatically matching and parsing tuning logs, the efficiency of test result statistics can be further improved.

[0072] The expected data is used to characterize the results in the tuning log as valid. This application does not elaborate on the expected data in detail; those skilled in the art can selectively set it according to actual needs.

[0073] For example, taking eMMC as an example, its supported rate modes include ddr50, HS200, HS400, HS401, and SDR25. Different reset commands are issued in ddr50 rate mode, yielding execution results and tuning logs in that mode. The same reset command is issued in HS200 mode, yielding execution results and tuning logs in that mode as well. The same reset command is issued in HS400 mode, yielding execution results and tuning logs in that mode as well. The same reset command is issued in HS401 mode, yielding execution results and tuning logs in that mode as well. The same reset command is issued in SDR25 mode, yielding execution results and tuning logs in that mode as well as the same reset command as that of ddr50. The results are shown in Table 1 below.

[0074]

[0075] Table 1

[0076] As shown in Table 1 above, the columns containing particles 1 through n record the matching results for a single memory chip. The first row corresponds to the tabs for different rate modes, with particles 1 through n representing the chip identifiers of the memory chips.

[0077] Understandably, the tuning logs corresponding to each rate mode are matched with the expected data, and the matching results are written to the corresponding table tabs, including:

[0078] Starting from the first row in each table tab used to record matching results, initialize the fill color of the cells in the preset number of rows in each table tab to the first color;

[0079] Associate the row numbers of each table tab with the corresponding row numbers of the tuning log;

[0080] Obtain the chip identifier corresponding to the tuning log;

[0081] Iterate through each line of the tuning log, match each line of log data with the expected data, and update the color of the corresponding target cell based on the matching result. The row number of the target cell is the same as the row number of the traversed line and corresponds to the chip identifier of the tuning log.

[0082] Understandably, when a match is successful, the target cell's color will be set to the second color, which is different from the first color. This application's embodiments do not limit the first and second colors; for example, the first color can be set to red, and the second color to green.

[0083] For example, referring to Table 1, assuming the chip identifier is particle 1 and the tuning log is in ddr50 mode, then for the first row of log data encountered, the target cell is updated according to the matching result of the first row of log data. The column of the target cell is the column where particle 1 is located, and the row of the target cell is the third row of the data tab.

[0084] Understandably, referring to Figure 2 As shown, a conformance verification system for a memory chip according to this application includes:

[0085] 100 robotic arms;

[0086] The first terminal device 200 is provided with a detachable test fixture 300, which is used to electrically connect the memory chip to the motherboard of the first terminal device.

[0087] The second terminal device 400 performs the above method.

[0088] Understandably, in some embodiments, the conformance verification system for memory chips also includes a chip tray 500 for batch loading of memory chips.

[0089] For example, refer to Figure 3 As shown, assuming N memory chips are being tested, the specific steps are as follows:

[0090] S1: Assembly of the consistency verification system, as detailed below:

[0091] S1.1 Place multiple memory chips to be verified on the chip tray that holds the memory chips in place;

[0092] S1.2 Install the test fixture on the first terminal device;

[0093] S1.3 Load the program for moving and placing the memory chip onto the test fixture onto the robotic arm; the program sets the suction force and other configurations for the robotic arm to pick up the memory chip, and the program is used to drive the robotic arm to move the memory chip from the chip tray to the test fixture.

[0094] S2: Control the robotic arm to remove a memory chip from the chip tray and place it on the test fixture;

[0095] S3: The second terminal device sends flashing commands, restart commands, and recovery commands to the first terminal device sequentially via a serial port, so that the first terminal can send flashing commands, restart commands, and recovery commands to the storage chip sequentially; wherein, the program loaded in the flashing command contains a tuning test component;

[0096] S4: Save the test results, including the tuning logs and execution results of each command in the flashing command, reboot command, and recovery command.

[0097] S5: Determine whether all the memory chips to be verified have been tested. If not, proceed to step two and update the memory chips to be updated on the test fixture.

[0098] S6: Perform statistical analysis on the test results of each memory chip to obtain consistency verification data.

[0099] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the aforementioned consistency verification method for the memory chip. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0100] Please see Figure 4 , Figure 4 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes:

[0101] The processor 601 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0102] The memory 602 can be a NAND flash, and the relevant program code is stored in the memory 602 and called by the processor 601 to execute the consistency verification method of the memory chip in this application embodiment;

[0103] The input / output interface 603 is used to implement information input and output;

[0104] The communication interface 604 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0105] Bus 605 transmits information between various components of the device (e.g., processor 601, memory 602, input / output interface 603, and communication interface 604);

[0106] The processor 601, memory 602, input / output interface 603, and communication interface 604 are connected to each other within the device via bus 605.

[0107] This application also provides a computer-readable storage medium that stores a computer program that, when executed by a processor, implements the above-described consistency verification method for the memory chip.

[0108] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0109] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0110] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0111] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0112] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0113] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0114] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0116] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0117] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0118] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0119] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for verifying the consistency of a memory chip, characterized in that, The method includes: The robotic arm is controlled to place multiple memory chips to be verified into a preset test fixture; wherein, the test fixture is detachably connected to the first terminal device, and the test fixture is used to electrically connect the memory chips to the motherboard of the first terminal device; Perform test steps on each memory chip placed in the test fixture to obtain test results corresponding to each memory chip; Based on the test results of each memory chip, consistency verification data is obtained; the consistency verification data indicates whether the test feedback of each memory chip for the same test item is consistent and whether the expected verification results are met. The test results of each memory chip are determined through the following steps: The first terminal device loads a preset tuning test component onto the storage chip; wherein, the tuning test component is used to perform a tuning test on the storage chip during the startup process of the storage chip and save the tuning test results as a tuning log in a preset storage path; The first terminal device sends multiple different reset commands to the memory chip, and obtains the execution result of each reset command. The execution result is used to characterize the execution status of the corresponding reset command. The test results are obtained based on the tuning logs and execution results. The tuning test component is loaded via a flashing command issued by the first terminal device; the process of issuing multiple different reset commands to the storage chip via the first terminal device and obtaining the execution results of each reset command includes: After loading the tuning test component via the flashing command, a restart command is sent to the storage chip via the first terminal device, and the execution result of the restart command is obtained; After the restart command is issued, a recovery command is sent to the storage chip through the first terminal device, and the execution result of the recovery command is obtained; The process of obtaining the test results based on the tuning logs and execution results includes: The test results are obtained based on the tuning logs corresponding to the flashing command, the reboot command, and the recovery command, as well as the execution results corresponding to the flashing command, the reboot command, and the recovery command, so as to verify the function through different reset commands and verify the consistency of the manufacturing process of the memory chip.

2. The consistency verification method for memory chips according to claim 1, characterized in that, The step of sending multiple different reset commands to the memory chip through the first terminal device and obtaining the execution results of each reset command includes: Obtain the preset number of tests and the test script, wherein the test script defines a variety of different reset commands sent to the memory chip through the first terminal device; Based on the number of tests, the test script is repeatedly executed to obtain the execution results of each reset instruction; When the number of times the test script is executed equals the number of tests, the test steps on the memory chip are stopped.

3. The consistency verification method for memory chips according to claim 2, characterized in that, The step of stopping the execution of the memory chip includes: Within a first preset duration, instructions to the current memory chip are stopped, wherein the first preset duration is longer than the duration for which the robotic arm replaces the memory chip.

4. The consistency verification method for memory chips according to claim 1, characterized in that, The memory chip supports multiple rate modes, and the step of sending multiple different reset commands to the memory chip through the first terminal device and obtaining the execution results of each reset command further includes: The first terminal device sends multiple different reset commands to the memory chip in different rate modes, and obtains the execution result of each reset command in each rate mode; The process of obtaining the test results based on the tuning logs and execution results includes: The testing results are determined by statistically analyzing the tuning logs and execution results for each of the aforementioned rate modes.

5. The consistency verification method for a memory chip according to claim 4, characterized in that, The step of separately analyzing the tuning logs and execution results for each of the aforementioned rate modes to determine the test results includes: Create blank table tabs that correspond one-to-one with the rate patterns; The tuning logs corresponding to each rate mode are matched with the expected data, and the matching results are written to the corresponding table tab. The test results are determined based on the updated table tabs and the execution results.

6. The consistency verification method for a memory chip according to claim 5, characterized in that, The step of matching the tuning logs corresponding to each of the aforementioned rate modes with the expected data and writing the matching results to the corresponding table tab includes: Starting from the first row in each of the table tabs used to record the matching results, the fill color of the cells in the preset number of rows in each of the table tabs is initialized to the first color; Associate the row numbers of each of the table tabs with the corresponding row numbers of the tuning logs; Obtain the chip identifier corresponding to the tuning log; Each line of the tuning log is traversed, and each line of log data is matched with the expected data. The color of the corresponding target cell is updated according to the matching result. The row number of the target cell is the same as the row number of the traversed line and corresponds to the chip identifier of the tuning log.

7. A consistency verification system for a memory chip, characterized in that, include: robotic arm; A first terminal device is provided with a detachable test fixture, which is used to electrically connect the memory chip to the motherboard of the first terminal device. The second terminal device performs the method as described in claim 1.

8. An electronic device, characterized in that, The electronic device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the consistency verification method for the memory chip according to any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the consistency verification method for the memory chip according to any one of claims 1 to 6.

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