Method of manufacturing a semiconductor device

Abstract

This invention provides a method for manufacturing a semiconductor device. After performing chemical mechanical polishing on the interlayer dielectric layer, not only is the top of the dummy gate exposed, but a loading effect is also generated where the top of the second dummy gate in the long-channel device region is higher than the top of the first dummy gate in the short-channel device region. Then, when performing chemical mechanical polishing on the deposited metal gate material, the loading effect generated by the previous polishing and the reverse complementary effect of this polishing are utilized. This not only allows the first metal gate in the short-channel device region to maintain its original dummy gate height, but also ensures that the top of the second metal gate in the long-channel device region is not higher than the top of the first metal gate in the short-channel device region. Ultimately, this reduces or eliminates the loading effect between the metal gates in the short-channel and long-channel device regions, thereby improving the overall electrical performance and yield of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] As device dimensions continue to shrink to 45nm and below, high-k metal gate (HKMG) technology has become the mainstream advanced process to replace traditional silicon dioxide gate dielectrics and polysilicon gates in order to improve gate leakage current. Currently, the mainstream HKMG process at 28nm and below generally uses the gate-last method to form the high-k metal gate, and fabricates long-channel (LC) gate structures and short-channel (SC) gate structures on the same substrate in one pass.

[0003] However, current post-metal gate methods can produce severe loading effects (i.e., gate height difference) between long-channel and short-channel gate structures, and the formed metal gate and the surrounding dielectric layer surface are prone to scratch defects, which affect the electrical performance and yield of the device. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor device that can eliminate or improve the load effect between the metal gates of the short-channel device region and the long-channel device region, thereby improving electrical performance and yield.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0006] Multiple dummy gates are formed on a substrate and an interlayer dielectric layer is deposited on the substrate. The dummy gate formed on the short-channel element region of the substrate is the first dummy gate, and the dummy gate formed on the long-channel element region of the substrate is the second dummy gate. The gate length of the first dummy gate is shorter than the gate length of the second dummy gate, and the interlayer dielectric layer buries each dummy gate.

[0007] The interlayer dielectric layer is chemically and mechanically polished until the top surface of each of the dummy gates is exposed and the top of the interlayer dielectric layer of the long channel element region is higher than the top of the interlayer dielectric layer of the short channel element region.

[0008] Selective etching removes each dummy gate to form a first gate groove at the location of the first dummy gate, and simultaneously forms a second gate groove at the location of the second dummy gate;

[0009] A metal gate material is deposited, which fills each of the first gate recess and the second gate recess and buries the interlayer dielectric layer therein;

[0010] The metal gate material is chemically and mechanically polished until the top surface of the interlayer dielectric layer of the short-channel element region is exposed, so as to form a first metal gate filling the first gate groove and a second metal gate filling the second gate groove, and the top of the interlayer dielectric layer of the long-channel element region is not higher than the top of the interlayer dielectric layer of the short-channel element region.

[0011] Optionally, the step of forming a plurality of dummy gates on a substrate and burying the dummy gates in an interlayer dielectric layer includes:

[0012] A silicon dioxide layer, a polysilicon layer, and a hard mask layer are sequentially deposited on the substrate;

[0013] The hard mask layer is patterned using a combination of photolithography and etching processes.

[0014] Using the hard mask layer as a mask, the polysilicon layer and the silicon dioxide layer are etched sequentially to form the pseudo gate including the polysilicon layer and the silicon dioxide layer;

[0015] A sidewall is formed on the sidewall of the dummy gate;

[0016] An etch stop layer and an interlayer dielectric layer are sequentially deposited on the substrate, wherein the interlayer dielectric layer fills the gap between the dummy gates.

[0017] Optionally, when selectively etching away each dummy gate, only the polysilicon layer is removed, or the polysilicon layer and the underlying silicon dioxide layer are removed together.

[0018] Optionally, after forming the sidewalls and before depositing the interlayer dielectric layer, source / drain regions are also formed in the substrate on both sides of the dummy gate.

[0019] Optionally, during the selective etching process to remove individual dummy gates, the top of the interlayer dielectric layer in the long-channel element region is kept higher than the top of the interlayer dielectric layer in the short-channel region.

[0020] Optionally, after selectively etching away each dummy gate, the height difference between the top of the interlayer dielectric layer of the long-channel element region and the top of the interlayer dielectric layer of the short-channel region is reduced.

[0021] Optionally, after forming the first gate trench and the second gate trench and before depositing the metal gate material, a high-k dielectric layer with a dielectric constant K higher than that of silicon dioxide is deposited in the first gate trench and the second gate trench.

[0022] Optionally, the polishing slurry used when performing chemical mechanical polishing on the metal gate material has a selection ratio of more than 50:1 for the metal gate material and the interlayer dielectric layer.

[0023] Optionally, after chemical mechanical polishing of the metal gate material, the depth of the gate groove in the short channel element region remains unchanged, and the top of the second metal gate is lower than the top of the first metal gate by a required height difference.

[0024] Optionally, the process time for chemical mechanical polishing of the interlayer dielectric layer, the process time for selective etching to remove each dummy gate, and the process time for chemical mechanical polishing of the metal gate material are interrelated.

[0025] Optionally, the manufacturing method further includes increasing the process time for chemical mechanical polishing of the interlayer dielectric layer, reducing the process time for selective etching to remove each dummy gate, and reducing the process time for chemical mechanical polishing of the metal gate material.

[0026] Compared with the prior art, the technical solution of the present invention, after performing chemical mechanical polishing (i.e., ILD0-CMP) on the interlayer dielectric layer, not only exposes the top of the dummy gate, but also achieves a loading effect where the top of the second dummy gate in the long-channel device region is higher than the top of the first dummy gate in the short-channel device region. Then, when performing chemical mechanical polishing (i.e., MG-CMP) on the deposited metal gate material, by utilizing the reverse complementary effect of the previous loading effect and this polishing, not only can the first metal gate in the short-channel device region maintain the original height of the dummy gate, but the top of the second metal gate in the long-channel device region is also not higher than the top of the first metal gate in the short-channel device region. Ultimately, this achieves the effect of reducing or eliminating the loading effect between the metal gates in the short-channel device region and the long-channel device region, thereby improving the overall electrical performance and yield of the device.

[0027] Furthermore, compared to existing technologies, the technical solution of this invention essentially controls the process time for chemical mechanical polishing of the interlayer dielectric layer to be relatively increased, while the process time for chemical mechanical polishing of the deposited metal gate material to be relatively shortened (i.e., more polishing for ILD0-CMP and less polishing for MG-CMP). Therefore, the scratch defects on the surface of the metal gate and the interlayer dielectric layer can be significantly reduced, further improving the electrical performance and yield of the device. Attached Figure Description

[0028] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0029] Figure 1This is a schematic diagram of the cross-sectional structure of a semiconductor device in an existing manufacturing method.

[0030] Figure 2 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure of a semiconductor device in a manufacturing method shown. Detailed Implementation

[0032] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0033] Please refer to Figure 1 The current process for manufacturing semiconductor devices using the post-metal gate process includes the following steps:

[0034] First, please refer to Figure 1 In (A), through a series of processes such as thermal oxidation, polysilicon deposition, silicon nitride 102 deposition, silicon oxide 103 deposition, photolithography and etching, several dummy gates 101 are formed on the substrate 100. The gate length of the dummy gates 101 formed on the short channel device region SC of the substrate 100 is relatively short, and the gate length of the dummy gates 101 formed on the long channel device region LC of the substrate 100 is relatively long.

[0035] Next, please refer to Figure 1 In step (A), after forming a sidewall 104 on the sidewall of the dummy gate 101, an interlayer dielectric layer 105 (ILD0) is deposited, which is capable of filling the gaps between the dummy gates 101.

[0036] Next, please refer to Figure 1 In step (B), chemical mechanical polishing (ILDO-CMP) is performed on the interlayer dielectric layer 105. The purpose of this polishing is to remove silicon nitride 102 and silicon oxide 103 on the top surface of the dummy gate 101, exposing the top surface of the dummy gate 102. The overall drop in film height is mainly due to the stacking thickness of silicon nitride 102, silicon oxide 103, and interlayer dielectric layer 105 on the top surface of the dummy gate 101. After polishing, the loading effect between the short-channel device region SC and the long-channel device region LC is not significant, that is, the height difference between the top of the dummy gate 101 in the short-channel device region SC and the dummy gate 101 in the long-channel device region LC is not significant. However, due to the small amount of polishing, silicon nitride 102 residue may remain.

[0037] Then, please refer to Figure 1 In step (C), the dummy gate 101 (Dummy polyremove, DPR) is removed by selective etching to form the gate recess 106. This step typically has a long processing time, usually requiring an additional break-through (BT) time (equivalent to over-etching time) after removing the dummy gate 101 to eliminate any remaining silicon nitride 102 and ensure that the dummy gate 101 is completely removed and the gate recess 106 is fully opened. However, due to the long processing time of this step, the interlayer dielectric layer 105 is lost, and the loss in the long-channel device region LC is greater than that in the short-channel device region SC, resulting in a loading effect between the short-channel device region SC and the long-channel device region LC. In this case, the top of the interlayer dielectric layer 105 in the long-channel device region LC will be h1 lower than the top of the interlayer dielectric layer 105 in the short-channel device region SC.

[0038] Next, please refer to Figure 1 In (D), a high-K dielectric and a metal gate material are deposited sequentially, and the metal gate material 107 can fill the gate groove 106.

[0039] Next, please refer to Figure 1 In step (E), a polishing slurry with a polishing rate selection ratio of more than 50:1 between the metal gate material 107 and the interlayer dielectric layer 105 is generally used to perform chemical mechanical polishing (metal gate CMP, MG-CMP) on the metal gate material 107 to remove the metal gate material 107 on the top surface of the interlayer dielectric layer 105, thereby forming a metal gate.

[0040] In the aforementioned process, the MG-CMP process takes a relatively long time to achieve height control of the metal gate. During this process, the polishing rate of the metal gate material 107 is very high, while the polishing rate of the interlayer dielectric layer 105 is very slow. This results in a greater drop height (i.e., loss) of the metal gate material 107 and interlayer dielectric layer 105 in the long-channel device region LC than in the short-channel device region SC. Combined with the loading effect brought by the DPR-ET process, the loading effect between the short-channel device region SC and the long-channel device region LC will be further exacerbated after MG-CMP. At this point, the top of the interlayer dielectric layer 105 in the long-channel device region LC will be h2 lower than the top of the interlayer dielectric layer 105 in the short-channel device region SC, and h2 > h1. For example...

[0041]

[0042] In addition, due to the long polishing time of MG-CMP, scratches and other defects are easily generated on the surface of the metal gate and the surrounding interlayer dielectric layer 105, which directly affects the electrical performance and yield of the semiconductor device finally formed on the substrate 100.

[0043] The inventors believe that mastering the balance between ILD0-CMP and MG-CMP is crucial to the load effect between the final short-channel element region SC and long-channel element region LC of the formed semiconductor device, as well as the gate control capability and defect performance.

[0044] Based on this, the present invention provides a method for manufacturing semiconductor devices. On the basis of the original process, it fully combines the polishing characteristics of ILD0-CMP and MG-CMP. By using a reverse complementary method of more polishing with ILD0-CMP and less polishing with MG-CMP, and by adjusting the DPR-ET process time, the load effect between the short-channel device region SC and the long-channel device region LC is greatly reduced while keeping the final gate height unchanged. Furthermore, because MG-CMP polishes less, scratch defects and other problems are also significantly reduced, thereby improving the overall electrical performance and yield of the device.

[0045] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0046] Please refer to Figure 2 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps:

[0047] S1, a plurality of dummy gates are formed on a substrate and an interlayer dielectric layer is deposited on the substrate, wherein the dummy gate formed on the short-channel element region of the substrate is the first dummy gate, and the dummy gate formed on the long-channel element region of the substrate is the second dummy gate, the gate length of the first dummy gate is shorter than the gate length of the second dummy gate, and the interlayer dielectric layer buries each dummy gate therein.

[0048] S2, perform chemical mechanical polishing on the interlayer dielectric layer until the top surface of each of the dummy gates is exposed and the top of the interlayer dielectric layer of the long channel element region is higher than the top of the interlayer dielectric layer of the short channel element region.

[0049] S3, selectively etch away each dummy gate to form a first gate groove at the location of the first dummy gate, and simultaneously form a second gate groove at the location of the second dummy gate;

[0050] S4, depositing a metal gate material that fills each of the first gate recesses and the second gate recesses and buries the interlayer dielectric layer therein;

[0051] S5, perform chemical mechanical polishing on the metal gate material until the top surface of the interlayer dielectric layer of the short-channel element region is exposed, so as to form a first metal gate filling the first gate groove and a second metal gate filling the second gate groove, and the top of the interlayer dielectric layer of the long-channel element region is not higher than the top of the interlayer dielectric layer of the short-channel element region.

[0052] Please refer to Figure 3 In step (A), the substrate 100 provided in step S1 can be any suitable semiconductor substrate material, such as a silicon substrate, a silicon carbide substrate, a gallium arsenide substrate, etc. The substrate 100 has a short-channel element region SC and a long-channel element region LC, wherein the short-channel element region SC is used to form a metal gate with a shorter gate length (i.e., a shorter channel) (e.g.,...). Figure 3 As shown in (E) 107a), the long-channel element region LC is used to form a metal gate with a longer gate length (i.e., a longer channel) (as shown in the figure). Figure 3 (As shown in 107b of (E)). This step further includes the process of forming a first dummy gate 101a, a second dummy gate 101b and an interlayer dielectric layer 105 on the substrate 100, which includes:

[0053] First, a silicon dioxide layer (not shown), a polysilicon layer (not labeled), and a hard mask layer (not labeled) are sequentially deposited on a substrate 100. The silicon dioxide layer serves as a dummy gate dielectric layer and can be formed by any suitable process, such as thermal oxidation. The polysilicon layer and the hard mask layer can be formed by suitable deposition processes, such as chemical vapor deposition. The hard mask layer can be a single-layer film such as silicon oxide or silicon nitride, or it can be a multilayer film structure formed by stacking various different materials such as silicon oxide and silicon nitride. As an example, the hard mask layer includes silicon nitride 102 and silicon oxide 103 sequentially deposited on the polysilicon layer.

[0054] Next, the hard mask layer is patterned using a combination of photolithography and dry etching processes, thereby forming patterns of individual dummy gates in the hard mask layer.

[0055] Then, using the patterned hard mask layer as a mask, the polysilicon layer and the silicon dioxide layer are sequentially etched through any suitable etching process to form a dummy gate comprising the polysilicon layer and the silicon dioxide layer. The dummy gate formed on the short-channel device region SC is the first dummy gate 101a, and the dummy gate formed on the long-channel device region LC is the second dummy gate 101b. At this point, the tops of the second dummy gate 101b and the second dummy gate 101b are essentially the same height, for example, H (defined as the original height), and there is almost no load effect between them. However, the gate length of the first dummy gate 101a is shorter than the gate length of the second dummy gate 101b. Furthermore, the spacing between the first dummy gates 101a can be equal to, less than, or greater than the spacing between the second dummy gates 101b; this invention does not specifically limit this.

[0056] Subsequently, sidewalls 104 are formed on the sidewalls of the first dummy gate 101a and the second dummy gate 101b through deposition and etching processes of sidewall materials (such as silicon oxide, silicon nitride, etc., single-layer or multi-layer films).

[0057] Next, an etch stop layer (not shown, but may be a material such as silicon oxide) and an interlayer dielectric layer (i.e., ILD0) 105 are sequentially deposited on the substrate 100. The interlayer dielectric layer 105 may fill the gap between the first dummy gates 101a and the gap between the second dummy gates 101b. The material of the interlayer dielectric layer 105 can be any suitable dielectric material, such as tetraethyl orthosilicate or a low-k dielectric with a dielectric constant K less than that of silicon dioxide, etc.

[0058] Optionally, after forming the sidewall 104 and before depositing the interlayer dielectric layer 105, corresponding source / drain regions can be formed in the substrates on both sides of the first pseudo gate 101a and the second pseudo gate 101b respectively by commonly used processes in the art, such as source / drain ion implantation or embedded source / drain processes.

[0059] Please refer to Figure 3In step (B), in step S2, a suitable polishing slurry and a soft polishing pad are used to perform chemical mechanical polishing (i.e., ILD0-CMP process) on the interlayer dielectric layer 105. The purpose of this polishing is to remove silicon nitride 102 and silicon oxide 103 from the top surfaces of the first dummy gate 101a and the second dummy gate 101b, and to make the top of the remaining first dummy gate 101a lower than the top of the second dummy gate 101b.

[0060] In this embodiment, it can be achieved by maintaining and Figure 1 With other process conditions remaining unchanged in the original method, only the grinding time of the chemical mechanical grinding is relatively increased. Figure 1 In the original method shown, the polishing time of ILD0-CMP is defined as the first standard polishing time. In this embodiment, the polishing time of ILD0-CMP is extended relative to the first standard polishing time. The advantages are: (1) After removing most of the silicon nitride 102 and silicon oxide 103 and polishing to expose the top surface of the dummy gate, it is necessary to continue polishing downwards. Therefore, the residues of silicon nitride 102 and silicon oxide 103 can be removed by polishing, and the tops of the first dummy gate 101a and the second dummy gate 101b are fully exposed; (2) When the top surface of the dummy gate is exposed and polishing continues downwards, since the polishing fluid has a relatively small selectivity for the interlayer dielectric layer 105 and polysilicon, the polysilicon polishing rate of the long channel element region LC is less than that of the short channel element region SC. Therefore, the top of the second dummy gate 101b of the long channel element region LC will eventually be higher than the top of the first dummy gate 101b of the short channel element region SC. Obviously, by controlling the grinding time, the top height of the first pseudo gate 101a and the second pseudo gate 101b can be appropriately reduced as a whole (for example, the height of the first pseudo gate 101a is reduced from the original height H to H2, and the height of the second pseudo gate 101b is reduced from the original height H to H1). However, under the effect of the difference in grinding rate between the long channel element region LC and the short channel element region SC, a load reaction that can be reverse-complemented with the grinding in the subsequent step S5 can also be brought about. Even if the top of the second pseudo gate 101b in the long channel element region LC is higher than the top of the first pseudo gate 101a in the short channel element region SC and the height difference h0 = H1 - H2 reaches the required level, under the action of grinding, the top of the interlayer dielectric layer 105 in the long channel element region LC is also higher than the top of the interlayer dielectric layer 105 in the short channel element region SC (the height difference is also h0); (3) Since ILD0-CMP uses a soft grinding pad when grinding the pseudo gate, even if the grinding time is relatively Figure 1 The length of the solution will not increase the number of scratches or defects.

[0061] As an example, the grinding time of step S2 (i.e., ILD0-CMP) in this embodiment is 15 to 30% longer than the grinding time of the prior art ILD0-CMP (i.e., the first standard grinding time mentioned above).

[0062] As another example, in step S2 (i.e., ILD0-CMP) of this embodiment, by extending the polishing time relative to the prior art ILD0-CMP (i.e., the first standard polishing time mentioned above), the top height of the first dummy gate 101a of the short-channel element region SC after polishing is further reduced by 5% to 15% (i.e., H2 = 85% * H to 95% * H), or the top height of the second dummy gate 101b of the long-channel element region LC after polishing is further reduced by 5% to 15% (i.e., H1 = 85% * H to 95% * H), or the height difference h0 between the top height of the second dummy gate 101b of the long-channel element region LC and the top height of the first dummy gate 101a of the short-channel element region SC after polishing reaches 5% to 15% of the original height H.

[0063] Please refer to Figure 3 In step S3, the first dummy gate 101a and the second dummy gate 101b are removed by any suitable selective etching process (i.e., DPR-ET process) such as wet etching or dry etching followed by wet etching, thereby forming a first gate groove 106a at the position of the first dummy gate 101a and a second gate groove 106b at the position of the second dummy gate 101b.

[0064] Optionally, in step S3, when selectively etching away each dummy gate, only the polysilicon layer may be removed, or the polysilicon layer and the underlying silicon dioxide layer may be removed together.

[0065] It should be understood that, due to the relative... Figure 1 The ILD0-CMP method shown increases (i.e. prolongs) the polishing time, eliminating the risk of silicon nitride 102 residue. Therefore, step S3 can be relatively... Figure 1The DPR-ET method shown shortens the process time, for example, by omitting the BT time mentioned above, or even further shortening the time based on omitting the BT time. The advantages of doing so are: (1) On the basis of ensuring that the first dummy gate 101a and the second dummy gate 101b are completely removed (i.e., the first gate recess 106a and the second gate recess 106b are completely opened), the consumption of the interlayer dielectric layer 105 is reduced, so that after DPR-ET, the top of the interlayer dielectric layer 105 of the long channel device region LC is still higher than the top of the interlayer dielectric layer 105 of the short channel device region SC; (2) Over-etching is avoided, which would cause severe damage to the substrate 100 surface exposed at the bottom of the first gate recess 106a and the second gate recess 106b.

[0066] Furthermore, in step S3, the DPR-ET process time can be reasonably controlled to generate controllable consumption of the interlayer dielectric layer 105, so that after step S3, the top of the interlayer dielectric layer 105 of the long channel device region LC is higher than the top of the interlayer dielectric layer 105 of the short channel device region SC, and the height difference remains unchanged or decreases compared with the height difference h0 at the end of step S2.

[0067] Please refer to Figure 3 In step (D) of S4, firstly, a suitable high-k dielectric material with a dielectric constant K greater than silicon dioxide can be deposited on the inner surfaces of the first gate recess 106a and the second gate recess 106b using any suitable process such as atomic layer deposition or chemical vapor deposition to form a high-k dielectric layer (not shown). Then, a metal gate material 107 can be deposited on the high-k dielectric layer and its exposed device surfaces using any suitable process such as sputtering, evaporation, or chemical vapor deposition. This metal gate material 107 fills the remaining space in the first gate recess 106a and the second gate recess 106b. The metal gate material 107 may include the work function material and metal electrode material required for the metal gate of a PMOS transistor or an NMOS transistor.

[0068] Please refer to Figure 3 In step S5 (E), a polishing slurry with a selectivity ratio of more than 50:1 for the metal gate material 107 and the interlayer dielectric layer 105 can be used to perform chemical mechanical polishing (i.e., MG-CMP process) on the metal gate material 107. The main purpose of this step S5 is to remove the metal gate material 107 on top of the interlayer dielectric layer 105, so that the remaining metal gate material 107 fills the first gate recess 106a to form the first metal gate 107a and fills the second gate recess 106b to form the second metal gate 107b, while providing a flat process platform for subsequent processes.

[0069] In step S5, the polishing slurry polishes the metal gate material 107 very quickly, but the polishing rate of the interlayer dielectric layer 105 and sidewall 104 is very slow. Furthermore, the long-channel device region LC has a high polishing rate due to the lower density of the interlayer dielectric layer 105, while the short-channel device region SC has a low polishing rate due to the higher density of the interlayer dielectric layer 105. Therefore, in step S5, the polishing time can be controlled to maximize the utilization of the polishing rate difference between the long-channel device region LC and the short-channel device region SC, as well as the loading effect formed in the previous step S3. The reverse complementary effect of the height difference (h0) controls the grinding to stop at the top of the interlayer dielectric layer 105 in the short-channel element region SC, avoiding excessive loss in the interlayer dielectric layer 105. This allows the top height of the second metal gate 107b in the long-channel element region LC to be relatively reduced to no higher than the top height of the first metal gate 107a in the short-channel element region SC, while maintaining the top height of the first metal gate 107a in the short-channel element region SC at the end of step S3, and the height difference between the two is less than [a certain value]. Figure 1 As shown in h2, this improves the loading effect between the short-channel element region SC and the long-channel element region LC, thereby improving the overall device performance and yield.

[0070] Optionally, in step S5, during the MG-CMP process, the depth of the first gate groove in the short channel device region SC remains unchanged, and the top height of the second metal gate 107b is ultimately lower than the top height of the first metal gate 107a, and the height difference between the two meets the device design requirements.

[0071] As an example, the height difference between the top height of the second metal gate 107b in the long-channel element region LC and the top height of the first metal gate 107a in the short-channel element region SC is ultimately controlled to not exceed [a certain value]. Within the range.

[0072] It should be understood that, compared to Figure 1 In the scheme shown, the ILD0-CMP polishing time is appropriately lengthened in step S2 of this embodiment, and the depth of the first gate trench 106a is relatively reduced. Therefore, compared with step S5, the depth of the first gate trench 106a is relatively reduced in this embodiment. Figure 1 The proposed solution allows for a reduction in the grinding time of MG-CMP while maintaining the same thickness of the deposited metal gate material 107. This achieves the required metal gate height and significantly improves issues such as scratches caused by excessive grinding time.

[0073] In summary, the grinding time in step S5, the etching time in step S3, and the grinding time in step S2 are interrelated and mutually restrictive. Increasing the grinding time in step S2 requires relatively reducing the etching time in step S3 and the grinding time in step S5. Thus, by utilizing the complementary combination effect of steps S2, S3, and S5, the loading effect between the short-channel device region SC and the long-channel device region LC can be eliminated or improved, while also improving scratch defects, ultimately improving the overall electrical performance and yield of the device.

[0074] It is worth noting that the present invention does not specifically limit the grinding time in step S5, the etching time in step S3, or the grinding time in step S2. When applying the method of the present invention, those skilled in the art can make reasonable adjustments based on their original processes to achieve the expected technical effects.

[0075] It should be understood that after the grinding in step S2, the specific magnitude of the height difference h0 (i.e., the load effect) between the long-channel element region LC and the short-channel element region SC can be obtained by the following means: (1) directly measured by some film thickness measuring equipment and means; (2) the relationship between the height difference h0 and the grinding time is obtained in advance based on historical production data, and then the height difference h0 corresponding to this grinding time is obtained according to this relationship. Similarly, the specific magnitude of the height difference (i.e., the load effect) between the long-channel element region LC and the short-channel element region SC after step S3, and the specific magnitude of the height difference (i.e., the load effect) between the long-channel element region LC and the short-channel element region SC after step S5, can all be obtained by the above means. The present invention does not specifically limit the specific magnitude of the height difference (i.e., the load effect) formed in these steps.

[0076] In summary, the technical solution of this invention, after performing chemical mechanical polishing (i.e., ILD0-CMP) on the interlayer dielectric layer, not only exposes the top of the dummy gate, but also achieves a loading effect where the top of the second dummy gate in the long-channel device region is higher than the top of the first dummy gate in the short-channel device region. Therefore, when performing chemical mechanical polishing (i.e., MG-CMP) on the deposited metal gate material, the reverse complementary effect of this polishing and the previous loading effect can be utilized to not only maintain the original height of the first metal gate in the short-channel device region, but also ensure that the top of the second metal gate in the long-channel device region is not higher than the top of the first metal gate in the short-channel device region. This achieves the effect of reducing or eliminating the loading effect between the metal gates in the short-channel device region and the long-channel device region, thereby improving the overall electrical performance and yield of the device.

[0077] In addition, compared with existing technologies, the process time for chemical mechanical polishing of the interlayer dielectric layer is relatively longer, while the process time for chemical mechanical polishing of the deposited metal gate material is relatively shorter (i.e., ILD0-CMP polishes more, MG-CMP polishes less). Therefore, the scratch defects on the surface of the final metal gate and interlayer dielectric layer can be significantly reduced, further improving the overall electrical performance and yield of the device.

[0078] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: forming a plurality of dummy gates on a substrate and depositing an interlayer dielectric layer on the substrate, wherein the dummy gate formed on the short channel element region of the substrate is a first dummy gate, the dummy gate formed on the long channel element region of the substrate is a second dummy gate, the gate length of the first dummy gate is shorter than that of the second dummy gate, and the interlayer dielectric layer buries each dummy gate; chemically and mechanically polishing the interlayer dielectric layer until the top surface of each dummy gate is exposed; increasing and controlling the polishing time of the interlayer dielectric layer to remove the residue on the top surface of each dummy gate, reduce the height of the top surface of each dummy gate, and make the top of the interlayer dielectric layer of the long channel element region higher than that of the short channel element region to a required height difference; selectively etching and removing each dummy gate to form a first gate recess at the position of the first dummy gate and a second gate recess at the position of the second dummy gate; depositing a metal gate material, which fills each first gate recess and second gate recess and buries the interlayer dielectric layer; chemically and mechanically polishing the metal gate material to expose the top surface of the interlayer dielectric layer of the short channel element region to form a first metal gate filled in the first gate recess and a second metal gate filled in the second gate recess, and make the depth of the first gate recess of the short channel element region remain unchanged before and after the chemical and mechanical polishing of the metal gate material, and make the top of the second metal gate drop to not higher than the first metal gate and lower than the top of the first metal gate to a required height difference.

2. The production method according to claim 1, wherein The steps of forming a plurality of dummy gates on a substrate and depositing an interlayer dielectric layer to bury the dummy gates comprise: sequentially covering a silicon dioxide layer, a polysilicon layer and a hard mask layer on the substrate; patterning the hard mask layer by photolithography combined with etching process; etching the polysilicon layer and the silicon dioxide layer in sequence with the hard mask layer as a mask to form the dummy gates comprising the polysilicon layer and the silicon dioxide layer; forming a sidewall on the sidewall of the dummy gate; sequentially depositing an etching stop layer and the interlayer dielectric layer on the substrate, and the interlayer dielectric layer fills the space between the dummy gates.

3. The production method according to claim 2, wherein After forming the sidewall and before depositing the interlayer dielectric layer, source and drain regions are also formed in the substrate on both sides of the dummy gate.

4. The production method according to claim 1, wherein During the process of selectively etching and removing each dummy gate, the top of the interlayer dielectric layer of the long channel element region is kept higher than that of the short channel element region.

5. The production method according to claim 1, wherein After selectively etching and removing each dummy gate, the height difference between the top of the interlayer dielectric layer of the long channel element region and that of the short channel element region is reduced.

6. The production method according to claim 1, wherein After forming the first gate recess and the second gate recess and before depositing the metal gate material, a high-K dielectric layer with dielectric constant K higher than that of silicon dioxide is first deposited in the first gate recess and the second gate recess.

7. The production method according to claim 1, wherein A polishing liquid used in chemical mechanical polishing of the metal gate material, a selectivity of the polishing liquid to the interlayer dielectric layer is more than 50:

1.

8. The production method according to claim 1, wherein A process time of chemical mechanical polishing of the interlayer dielectric layer, a process time of selective etching to remove each dummy gate, and a process time of chemical mechanical polishing of the metal gate material are correlated with each other.

9. The production method according to claim 8, wherein It also includes increasing the process time of chemical mechanical polishing of the interlayer dielectric layer, decreasing the process time of selective etching to remove each dummy gate, and decreasing the process time of chemical mechanical polishing of the metal gate material.

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