Method for reducing reverse gate-source leakage current

Abstract

The application provides a method for reducing gate-source reverse leakage current, which comprises the following steps: providing a substrate, forming a groove on the substrate, forming an ONO layer on the groove, wherein the ONO layer is composed of a first oxide layer, a nitride layer and a second oxide layer stacked in sequence from bottom to top; forming a first polysilicon layer with a preset thickness in the groove, then forming an isolation medium layer on the first polysilicon layer, and the second oxide layer on the upside of the isolation medium layer is exposed; removing the exposed second oxide layer and the nitride layer; forming a third oxide layer on the first oxide layer, and the total thickness of the first and third oxide layers is a target thickness; forming a second polysilicon layer to fill the remaining groove, so that the bottom of the second polysilicon layer is smooth. While matching the reference process structure, the gate-source reverse leakage current parameter is reduced by at least one order of magnitude.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for reducing gate-source reverse leakage current. Background Technology

[0002] The SGT (trench gate) product exhibited an excessively high IGSSR (gate-source reverse leakage current), and failure analysis revealed a sharp corner at the bottom of the polysilicon gate.

[0003] The large curvature of the gate polysilicon corner results in a large electric field strength. Based on the Poole-Frenkel effect, the conductivity of the insulating material is proportional to the electric field strength. Electrons can easily flow through the oxide layer from the gate polysilicon corner, resulting in a high IGSSR.

[0004] To address the above problems, a novel method for reducing gate-source reverse leakage current is needed. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for reducing gate-source reverse leakage current, which solves the problem that the gate polysilicon corner has a large curvature and a large electric field strength, making it easy for electrons to flow through the oxide layer from the gate polysilicon corner, resulting in a high gate-source reverse leakage current.

[0006] To achieve the above and other related objectives, the present invention provides a method for reducing gate-source reverse leakage current, comprising:

[0007] Step 1: Provide a substrate, form trenches on the substrate, and form an ONO layer on the trenches. The ONO layer consists of a first oxide layer, a nitride layer, and a second oxide layer stacked sequentially from bottom to top.

[0008] Step 2: A first polysilicon layer of a predetermined thickness is formed in the trench, and then an isolation dielectric layer is formed on the first polysilicon layer, with the second oxide layer on the upper side of the isolation dielectric layer exposed.

[0009] Step 3: Remove the exposed second oxide layer and the nitride layer;

[0010] Step 4: Form a third oxide layer on the first oxide layer, wherein the total thickness of the first and third oxide layers is the target thickness;

[0011] Step 5: Form a second polysilicon layer to fill the remaining trenches, such that the bottom of the second polysilicon layer has a smooth morphology.

[0012] Preferably, the first oxide layer is formed in step one using a thermal oxidation method.

[0013] Preferably, the nitride layer is formed in step one using a low-pressure chemical vapor deposition method.

[0014] Preferably, the second oxide layer is formed in step one using a chemical vapor deposition method.

[0015] Preferably, in step one, the thickness of the first oxide layer is reduced and the thickness of the second oxide layer is increased, so that the thicknesses of the first and second oxide layers are consistent with the baseline process.

[0016] Preferably, in step two, the first polysilicon layer is formed using a deposition and polysilicon back-etching method.

[0017] Preferably, the isolation medium layer in step two is an oxide layer formed by thermal oxidation.

[0018] Preferably, in step three, the second oxide layer and the nitride layer are removed sequentially using a wet etching method.

[0019] Preferably, the third oxide layer is formed in step four using a low-pressure chemical vapor deposition method.

[0020] Preferably, in step five, the second polysilicon layer is formed using a deposition and polysilicon back-etching method.

[0021] As described above, the method for reducing gate-source reverse leakage current of the present invention has the following beneficial effects:

[0022] This invention reduces the gate-source reverse leakage current parameter by at least one order of magnitude while matching the baseline process structure. Attached Figure Description

[0023] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention.

[0024] Figure 2 The diagram shown illustrates the formation of the ONO layer according to the present invention.

[0025] Figure 3 The diagram shown illustrates the formation of the first polycrystalline silicon layer according to the present invention.

[0026] Figure 4 The diagram shown illustrates the formation of the isolation medium layer according to the present invention.

[0027] Figure 5 The diagram shown illustrates the removal of the exposed second oxide layer and nitride layer according to the present invention.

[0028] Figure 6 The diagram shown illustrates the formation of the third oxide layer according to the present invention.

[0029] Figure 7 The diagram shown illustrates the formation of the second polycrystalline silicon layer according to the present invention. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] Please see Figure 1 The present invention provides a method for reducing gate-source reverse leakage current, comprising:

[0032] Step 1: Provide a substrate 101, form trenches on the substrate 101, and form an ONO layer on the trenches. The ONO layer consists of a first oxide layer 102, a nitride layer 103, and a second oxide layer 104 stacked sequentially from bottom to top, forming as shown in the figure. Figure 2 The structure shown; typically the first and second oxide layers are made of silicon dioxide, and the nitride layer 103 is made of silicon nitride;

[0033] In some embodiments, the trench is formed in step one using photolithography and dry etching methods.

[0034] In some embodiments, the first oxide layer 102 is formed in step one by thermal oxidation.

[0035] In some embodiments, the nitride layer 103 is formed in step one using a low-pressure chemical vapor deposition method.

[0036] In some embodiments, the second oxide layer 104 is formed in step one using a chemical vapor deposition method.

[0037] In some embodiments, in step one, the thickness of the first oxide layer 102 is reduced and the thickness of the second oxide layer 104 is increased, so that the thicknesses of the first and second oxide layers are consistent with the field oxide layer thickness of the reference process. For example, in the reference process, the thickness of the first oxide layer 102 is 400 angstroms, the thickness of the nitride layer 103 is 200 angstroms, and the thickness of the second oxide layer 104 is 800 angstroms. In this embodiment of the invention, the thickness of the first oxide layer 102 is 100 angstroms, the thickness of the nitride layer 103 is 200 angstroms, and the thickness of the second oxide layer 104 is 1100 angstroms.

[0038] Step 2: Form a first polysilicon layer 105 of a predetermined thickness in the trench, forming a layer as shown in the figure. Figure 3 The structure shown is followed by the formation of an isolation dielectric layer 106 on the first polysilicon layer 105, forming a structure as shown. Figure 4 In the structure shown, the second oxide layer 104 on the upper side of the insulating dielectric layer 106 is exposed;

[0039] In some embodiments, the first polysilicon layer 105 is formed in step two using a deposition and polysilicon back etching method.

[0040] In some embodiments, the isolation medium layer 106 in step two is an oxide layer formed by thermal oxidation.

[0041] Step 3: Remove the exposed second oxide layer 104 and nitride layer 103 to form a structure as shown in the figure. Figure 5 The structure shown;

[0042] In some embodiments, in step three, the second oxide layer 104 and the nitride layer 103 are removed sequentially by wet etching. That is, the second oxide layer 104 is removed first by wet etching with a high selectivity of oxide layer to nitride layer 103, and then the nitride layer 103 is removed by wet etching with a high selectivity of nitride layer to oxide layer. This can reduce the loss of the first oxide layer 102 on the sidewall and avoid the appearance of sharp corner morphology at that location.

[0043] Step 4: Form a third oxide layer 107 on the first oxide layer 102, forming as shown in the figure. Figure 6 The structure shown has a total thickness of the first and trioxide layers that is the target thickness, ensuring that the gate oxide layer is consistent with the reference process structure (consistent with the reference process threshold voltage), while also improving the bottom morphology of the second polysilicon layer 108. For example, in the reference process, the thickness of the first oxide layer 102 is 400 angstroms, the thickness of the nitride layer 103 is 200 angstroms, and the thickness of the second oxide layer 104 is 800 angstroms. In this embodiment of the invention, the thickness of the first oxide layer 102 is 100 angstroms, the thickness of the nitride layer 103 is 200 angstroms, the thickness of the second oxide layer 104 is 1100 angstroms, and the thickness of the third oxide layer 107 is 300 angstroms.

[0044] In some embodiments, the third oxide layer 107 is formed in step four using a low-pressure chemical vapor deposition method.

[0045] Step 5: Form a second polysilicon layer 108 to fill the remaining trenches, making the bottom of the second polysilicon layer 108 have a smooth morphology, forming as shown in the figure. Figure 7 The structure shown.

[0046] In some embodiments, the second polysilicon layer 108 is formed in step five using a deposition and polysilicon back etching method.

[0047] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0048] In summary, this invention reduces the gate-source reverse leakage current parameter by at least one order of magnitude while matching the baseline process structure. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0049] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of reducing reverse gate-source leakage current, comprising: At least comprising: Step one, providing a substrate, forming a trench on the substrate, forming an ONO layer on the trench, the ONO layer is composed of a first oxide layer, a nitride layer and a second oxide layer stacked from bottom to top; here, the thickness of the first oxide layer is reduced, and the thickness of the second oxide layer is increased, so that the thickness of the first oxide layer and the second oxide layer is consistent with the reference process; Step two, forming a first polysilicon layer with a preset thickness in the trench, then forming an isolation medium layer on the first polysilicon layer, the second oxide layer on the top side of the isolation medium layer is exposed; Step three, removing the exposed second oxide layer and the nitride layer; Step four, forming a third oxide layer on the first oxide layer, the total thickness of the first oxide layer and the third oxide layer is the target thickness; Step five, forming a second polysilicon layer to fill the remaining trench, so that the bottom of the second polysilicon layer is smooth.

2. The method of reducing reverse gate-source leakage current of claim 1, wherein: The first oxide layer is formed by thermal oxidation in step one.

3. The method of reducing reverse gate-source leakage current of claim 1, wherein: The nitride layer is formed by low pressure chemical vapor deposition in step one.

4. The method of reducing reverse gate-source leakage current of claim 1, wherein: The second oxide layer is formed by chemical vapor deposition in step one.

5. The method of reducing reverse gate-source leakage current of claim 1, wherein: The first polysilicon layer is formed by deposition and polysilicon etching in step two.

6. The method of reducing reverse gate-source leakage current of claim 1, wherein: The isolation medium layer in step two is an oxide layer formed by thermal oxidation.

7. The method of reducing reverse gate-source leakage current of claim 1, wherein: The second oxide layer and the nitride layer are removed by wet etching in step three.

8. The method of reducing reverse gate-source leakage current of claim 1, wherein: The third oxide layer is formed by low pressure chemical vapor deposition in step four.

9. The method of reducing reverse gate-source leakage current of claim 1, wherein: The second polysilicon layer is formed by deposition and polysilicon etching in step five.

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