Method for improving back etching morphology of polycrystalline silicon

Abstract

The invention provides a method for improving back etching morphology of polycrystalline silicon, which comprises the following steps of: providing a substrate, forming an epitaxial layer on the substrate, forming a groove on a groove gate device region and a gate lead-out region on the epitaxial layer, forming a field oxide layer in the groove and on the surface of the epitaxial layer, and then forming a gate polycrystalline silicon layer covering the groove; performing first etching to etch the gate polysilicon layer to the upper surface of the trench, and then forming an etching protection layer on the gate lead-out region; second dry etching is carried out, the second dry etching is anisotropic polycrystalline silicon back etching, the thickness of the remaining grid polycrystalline silicon layer after etching is made to be higher than the preset thickness, and a V-shaped crack is formed in the upper surface of the grid polycrystalline silicon layer; and third dry etching is carried out, microwave type reaction etching is adopted in the third dry etching, and isotropic etching is achieved through the microwave type reaction etching, so that the grid polycrystalline silicon layer is etched to the preset thickness. According to the invention, the morphology of the gate polycrystalline silicon layer after back etching can be improved, and the surface of the gate polycrystalline silicon layer has no V-shaped crack.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for improving polysilicon back etching morphology. Background Art

[0002] The prior art polysilicon etching back method of SGT (trench gate) products includes:

[0003] Step 1: Provide a substrate 101, form an epitaxial layer 102 on the substrate 101, form a trench on the trench gate device region and the gate lead-out region on the epitaxial layer 102, form a field oxide layer 104 in the trench and on the surface of the epitaxial layer 102, and then form a gate polysilicon layer 105 covering the trench, so as to form Figure 1 The structure shown;

[0004] Step 2: Perform the first etching to etch the gate polysilicon layer 105 to the upper surface of the trench to form Figure 6 The structure shown in FIG. 1 is then formed on the gate lead-out region to form an etching protection layer 106. Figure 2 The structure shown;

[0005] Step 3: Perform a second dry etching, the second dry etching is anisotropic polysilicon back etching, so that the remaining gate polysilicon layer 105 after etching is a preset thickness, forming a Figure 3 The structure shown.

[0006] Due to process evolution and the need for product iteration and upgrading, pitch size (period size) and Trench CD (trench critical dimension) are gradually decreasing, and the challenge of polysilicon filling in the trench is also increasing.

[0007] When polysilicon filling density is insufficient, the prior art polysilicon back etching will produce polysilicon defects, such as Figure 3 The V-shaped crack shown results in device failure due to IDSS (saturated drain current) / BV (breakdown voltage).

[0008] In order to solve the above problems, it is necessary to propose a new method for improving the polysilicon etch-back morphology. Summary of the invention

[0009] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving the polysilicon back etching morphology, so as to solve the problem in the prior art that polysilicon back etching will produce polysilicon defects and form V-shaped cracks when the polysilicon filling density is insufficient.

[0010] To achieve the above-mentioned object and other related objects, the present invention provides a method for improving the morphology of polysilicon etching back, comprising:

[0011] Step 1, providing a substrate, forming an epitaxial layer on the substrate, forming a trench on the trench gate device region and the gate lead-out region on the epitaxial layer, forming a field oxide layer in the trench and on the surface of the epitaxial layer, and then forming a gate polysilicon layer covering the trench;

[0012] Step 2: performing a first etching to etch the gate polysilicon layer to the upper surface of the trench, and then forming an etching protection layer on the gate lead-out region;

[0013] Step 3, performing a second dry etching, wherein the second dry etching is anisotropic polysilicon back etching, so that the gate polysilicon layer remaining after etching is higher than a preset thickness, and a V-shaped crack is formed on the upper surface of the gate polysilicon layer;

[0014] Step 4: performing a third dry etching, wherein the third dry etching adopts microwave reactive etching and utilizes the microwave reactive etching to achieve isotropic etching, so as to etch the gate polysilicon layer to a preset thickness, so that there is no V-shaped crack on the gate polysilicon layer.

[0015] Preferably, before forming the trench in step one, the step further includes forming a well region by ion implantation.

[0016] Preferably, the method for forming the etching protection layer in step 2 comprises: forming a photoresist layer covering the gate polysilicon layer; and opening the photoresist layer on the trench gate device region by photolithography.

[0017] Preferably, the etching method in step 2 is dry etching.

[0018] Preferably, the remaining gate polysilicon layer in step three is 1800 to 2200 angstroms thicker than a preset thickness.

[0019] Preferably, the microwave reactive etching in step 4 has no radio frequency power and the chamber pressure is 0.4 to 0.6 Torr.

[0020] Preferably, the etching gases for the microwave reactive etching in step 4 are CF4 and O2, and the proportion of O2 is adjusted to control the reaction rate and etching selectivity.

[0021] Preferably, the gas flow rate of CF4 in step 4 is 25 to 35 sccm, and the gas flow rate of O2 in step 4 is 75 to 85 sccm.

[0022] Preferably, after etching the gate polysilicon layer to a preset thickness in step 4, the etching loss of the field oxide layer is less than 50 angstroms.

[0023] Preferably, the method is used for manufacturing a power device.

[0024] As described above, the method for improving the polysilicon etch-back morphology of the present invention has the following beneficial effects:

[0025] The present invention can improve the morphology of the gate polysilicon layer after back etching, and there is no V-shaped crack on the surface of the gate polysilicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of forming a gate polysilicon layer in the prior art is shown;

[0027] Figure 2 Shown is a schematic diagram of the first etching of the prior art;

[0028] Figure 3 Shown is a schematic diagram of the second etching of the prior art;

[0029] Figure 4 Shown is a schematic diagram of the process flow of the present invention;

[0030] Figure 5 It is a schematic diagram of forming a gate polysilicon layer according to the present invention;

[0031] Figure 6 Shown is a schematic diagram of the first etching of the present invention;

[0032] Figure 7 Shown is a schematic diagram of the second dry etching process of the present invention;

[0033] Figure 8 It is a schematic diagram of the third dry etching of the present invention. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] See also Figure 4 The present invention provides a method for improving the morphology of polysilicon back etching, comprising:

[0036] Step 1: Provide a substrate 201, form an epitaxial layer 202 on the substrate 201, form a trench on the trench gate device region and the gate lead-out region on the epitaxial layer 202, form a field oxide layer 204 in the trench and on the surface of the epitaxial layer 202, and then form a gate polysilicon layer 205 covering the trench, so as to form a Figure 5 The structure shown;

[0037] In some embodiments, before forming the trench in step 1, a step of forming the well region 203 by ion implantation is also included.

[0038] Step 2: Perform the first etching to etch the gate polysilicon layer 205 to the upper surface of the trench to form Figure 6 The structure shown in FIG. 1 is then formed on the gate lead-out region to form an etching protection layer 206. Figure 7 The structure shown;

[0039] In some embodiments, the method of forming the etching protection layer 206 in step 2 includes: forming a photoresist layer covering the gate polysilicon layer 205; and opening the photoresist layer on the trench gate device region by photolithography.

[0040] In some embodiments, the etching method in step 2 is dry etching.

[0041] Step 3: Perform a second dry etching, the second dry etching is anisotropic polysilicon back etching, so that the remaining gate polysilicon layer 205 after etching is higher than the preset thickness, forming Figure 8 The structure shown, for example, the preset thickness can be about half the height of the trench; compared with the prior art that directly etches the gate polysilicon to the preset thickness, the present invention etches less gate polysilicon layer 205 of a certain thickness;

[0042] In some embodiments, the remaining gate polysilicon layer 205 in step three is higher than a predetermined thickness of 1800 to 2200 angstroms, such as 2000 angstroms.

[0043] Step 4: Perform a third dry etching. The third dry etching adopts microwave reactive etching and uses microwave reactive etching to achieve isotropic etching to etch the gate polysilicon layer 205 to a preset thickness, which can improve the morphology of the gate polysilicon layer 205. There is no V-shaped opening on the surface of the gate polysilicon layer 205, so that there is no V-shaped crack on the gate polysilicon layer 205.

[0044] In some embodiments, the microwave reactive etching in step 4 is performed without radio frequency power, and the chamber pressure is 0.4 to 0.6 Torr, for example 0.5 Torr.

[0045] In some embodiments, the etching gases for microwave reactive etching in step 4 are CF4 and O2, and the proportion of O2 is adjusted to control the reaction rate and etching selectivity.

[0046] In some embodiments, the gas flow rate of CF4 in step 4 is 25 to 35 sccm, and the gas flow rate of O2 in step 4 is 75 to 85 sccm. For example, the gas flow rate of CF4 is 30 sccm, and the gas flow rate of O2 in step 4 is 80 sccm.

[0047] In some embodiments, after etching the gate polysilicon layer 205 to a predetermined thickness in step 4, the etching loss amount of the field oxide layer 204 is less than 50 angstroms.

[0048] In some embodiments, the method is used in the manufacture of a power device.

[0049] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0050] In summary, the present invention can improve the morphology of the gate polysilicon layer after back etching, and there is no V-shaped crack on the surface of the gate polysilicon layer. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0051] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving polysilicon back etching morphology, characterized in that: At least: Step 1, providing a substrate, forming an epitaxial layer on the substrate, forming a trench on the trench gate device region and the gate lead-out region on the epitaxial layer, forming a field oxide layer in the trench and on the surface of the epitaxial layer, and then forming a gate polysilicon layer covering the trench; Step 2: performing a first etching to etch the gate polysilicon layer to the upper surface of the trench, and then forming an etching protection layer on the gate lead-out region; Step 3, performing a second dry etching, wherein the second dry etching is anisotropic polysilicon back etching, so that the gate polysilicon layer remaining after etching is higher than a preset thickness, and a V-shaped crack is formed on the upper surface of the gate polysilicon layer; Step 4: performing a third dry etching, wherein the third dry etching adopts microwave reactive etching and utilizes the microwave reactive etching to achieve isotropic etching, so as to etch the gate polysilicon layer to a preset thickness, so that there is no V-shaped crack on the gate polysilicon layer.

2. The method for improving polysilicon etch-back morphology according to claim 1, characterized in that: Before forming the trench in step 1, the step also includes forming a well region by ion implantation.

3. The method for improving polysilicon etch-back morphology according to claim 1, characterized in that: The method for forming the etching protection layer in step 2 includes: forming a photoresist layer covering the gate polysilicon layer; and opening the photoresist layer on the trench gate device region by photolithography.

4. The method for improving polysilicon etch-back morphology according to claim 1, characterized in that: The etching method in step 2 is dry etching.

5. The method for improving polysilicon etch-back morphology according to claim 1, characterized in that: The remaining gate polysilicon layer in step three is 1800 to 2200 angstroms thicker than the preset thickness.

6. The method for improving polysilicon etch-back morphology according to claim 1, characterized in that: The microwave reactive etching in step 4 has no radio frequency power and the chamber pressure is 0.4 to 0.6 Torr.

7. The method for improving polysilicon etch-back morphology according to claim 1, characterized in that: The etching gases for the microwave reactive etching in step 4 are CF4 and O2, and the proportion of O2 is adjusted to control the reaction rate and etching selectivity.

8. The method for improving polysilicon etch-back morphology according to claim 7, characterized in that: The gas flow rate of CF4 in step 4 is 25 to 35 sccm, and the gas flow rate of O2 in step 4 is 75 to 85 sccm.

9. The method for improving polysilicon etch-back morphology according to claim 1, characterized in that: After the gate polysilicon layer is etched to a preset thickness in step 4, the etching loss of the field oxide layer is less than 50 angstroms.

10. The method for improving polysilicon etch-back morphology according to claim 1, characterized in that: The method is used for manufacturing a power device.

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