Monitoring structure, monitoring method and semiconductor device capacitance testing method

Abstract

The present invention relates to a monitoring structure, a monitoring method and a semiconductor device capacitance testing method. The monitoring structure is used to monitor the parasitic capacitance and carrier plate noise generated when the corresponding WAT test structure on the wafer is subjected to capacitance testing. The monitoring structure includes a plurality of monitoring pads formed on the surface of the wafer and at least one conductive channel formed in the wafer, wherein the first monitoring pad is connected to the corresponding conductive channel. The monitoring method adopts the above-mentioned monitoring structure to obtain and monitor the parasitic capacitance of the test equipment, the parasitic capacitance of the probes introduced by two adjacent probes, and the noise generated by the carrier plate, so as to obtain feedback in time when abnormalities occur in the parasitic capacitance and the carrier plate noise, thereby timely processing the abnormal information, reducing the impact of the abnormal information on the WAT test data, and helping to improve the accuracy of the WAT test data. The semiconductor device capacitance testing method adopts the above-mentioned monitoring structure and monitoring method.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a monitoring structure, a monitoring method and a semiconductor device capacitance testing method. Background Art

[0002] WAT (Wafer Acceptance Test) is a wafer acceptance test. Typically performed after wafer tape-out and before quality inspection, WAT conducts electrical tests on specific test structures (test keys) formed on the wafer to determine whether the wafer product meets the electrical specifications of the corresponding process technology platform and detect any process anomalies. WAT test data can be used to analyze and improve process and device performance. The accuracy of WAT test data affects the analysis of process and product performance.

[0003] Figure 1 This is a schematic diagram of using the WAT test structure to detect the capacitance of a semiconductor device. Figure 1 The test structure for performing WAT (hereinafter referred to as WAT test structure) generally includes a semiconductor device (such as Figure 1 MOS transistor shown in the figure), a test pad 120 (test key PAD) formed on the semiconductor device, and a metal connection 110 connecting the semiconductor device and the test pad 120, wherein the metal connection 110 includes all conductive lines electrically connected from the semiconductor device to the test pad 120, and is not limited to Figure 1 The metal layer closest to the semiconductor device is shown. When performing a capacitance test, the wafer is usually placed on a probe station (not shown), fixed by adsorption of a carrier plate (chuck) on the probe station, and a probe card (i.e., a test board) is used to make the probe 130 of the probe card contact the test pad, so that the terminal of the capacitance test device is connected to the corresponding probe, thereby, the electrical signal emitted by the capacitance test device can be transmitted to the connection end of the semiconductor device through the corresponding probe 130, the test pad 120, and the metal connection in the wafer, and the electrical signal generated by the capacitance of the semiconductor device can also be sent to the capacitance test device through the corresponding test pad 120 and the probe 130.

[0004] but, Figure 1 The capacitance measured by the capacitance test method shown includes not only the capacitance to be measured of the semiconductor device (the capacitance to be measured includes, for example, Figure 1The capacitance Cint formed by the MOS transistor electrode and the metal connection 110 also includes the test equipment parasitic capacitance Ccb introduced by the capacitance test equipment and the probe parasitic capacitance Cpin introduced by the probe card; and the parasitic capacitance may vary according to the differences between different capacitance test equipment and different probe cards, thereby affecting the accuracy of the capacitance test data; in addition, affected by the surrounding electrical signals, the carrier plate in contact with the wafer may also generate noise (chuck noise), which may cause large fluctuations in the WAT test data, especially in capacitance test and leakage current test, thereby affecting the accuracy of the test data.

[0005] Therefore, it is necessary to monitor the parasitic capacitance introduced by the capacitance test equipment and the probe card and the noise generated by the carrier plate, so as to obtain timely feedback when the parasitic capacitance and the noise are abnormal, thereby improving the accuracy of the WAT test data. Summary of the Invention

[0006] The present invention provides a monitoring structure that can monitor the parasitic capacitance of capacitance test equipment and probe cards, as well as the noise generated by the carrier plate. This facilitates timely feedback when abnormalities in the parasitic capacitance and noise occur, thereby improving the accuracy of WAT test data. The present invention also provides a monitoring method and a semiconductor device capacitance testing method.

[0007] In one aspect, the present invention provides a monitoring structure for monitoring parasitic capacitance and carrier plate noise generated when performing capacitance testing using a WAT ​​test structure on a wafer, the monitoring structure comprising:

[0008] A plurality of monitoring pads are formed on the surface of the wafer, wherein the monitoring pads and the test pads of the WAT test structure are located on the first surface of the wafer, and the monitoring pads are arranged according to the test pads in the WAT test structure;

[0009] At least one conductive channel is formed in the wafer, the conductive channel connecting the first surface and a second surface of the wafer opposite to the first surface, wherein the multiple monitoring pads include at least one first monitoring pad and at least one second monitoring pad, the first monitoring pad is connected to the conductive channel and the second monitoring pad is not connected to the conductive channel, and the monitoring pad adjacent to the first monitoring pad is the second monitoring pad.

[0010] Optionally, the multiple monitoring pads are arranged sequentially along the same direction.

[0011] Optionally, the monitoring structure includes a plurality of first monitoring pads, and the plurality of monitoring pads include a plurality of repeated monitoring pad combinations, each of the monitoring pad combinations consisting of an adjacent first monitoring pad and a second monitoring pad, or consisting of a first monitoring pad and two adjacent second monitoring pads, or consisting of a second monitoring pad and two adjacent first monitoring pads.

[0012] Optionally, the number of the monitoring pads in the monitoring structure is greater than or equal to the number of probes on a probe card used for performing capacitance testing on the WAT test structure.

[0013] Optionally, the wafer includes a substrate and a dielectric layer between the substrate and the monitoring pad, and the conductive path includes a first conductive path passing through the dielectric layer and a second conductive path passing through the substrate and connected to the first conductive path.

[0014] Optionally, the first conductive channel is composed of a wiring layer and a conductive through-hole formed in the dielectric layer.

[0015] Optionally, the second conductive channel is formed by a p-type doping region or an n-type doping region formed in the substrate.

[0016] In one aspect, the present invention provides a monitoring method, using the above-mentioned monitoring structure, the monitoring method comprising:

[0017] Placing the wafer with the monitoring structure formed thereon on a carrier plate of a probe station, and making each probe of the probe card contact one of the monitoring pads;

[0018] Measuring capacitance using a capacitance testing device for performing a capacitance test on the WAT test structure, wherein a signal excitation end of the capacitance testing device emits an excitation signal and a signal detection end receives a detection signal, a first capacitance is measured when the signal excitation end and the signal detection end are respectively connected to an adjacent second monitoring pad and a adjacent first monitoring pad through two adjacent probes, a second capacitance is measured when the signal excitation end and the signal detection end are disconnected from the probe card, and a third capacitance is measured when the signal excitation end and the signal detection end are connected to two adjacent probes and the probe card is disconnected from the monitoring pads;

[0019] Taking the first capacitance as the sum of the parasitic capacitance of the test device introduced by the capacitance test device, the parasitic capacitance of the probe introduced by the two adjacent probes, and the noise introduced by the carrier plate, taking the second capacitance as the parasitic capacitance of the test device, and taking the third capacitance as the sum of the parasitic capacitance of the test device and the parasitic capacitance of the probe, the parasitic capacitance of the test device, the parasitic capacitance of the probe introduced by the two adjacent probes, and the noise generated by the carrier plate are obtained; and

[0020] It is determined whether at least one of the parasitic capacitance of the test device, the parasitic capacitance of the probe, and the noise generated by the carrier plate exceeds a corresponding set range. If so, corresponding abnormal information is fed back; otherwise, no abnormal information is fed back.

[0021] Optionally, measuring capacitance using the capacitance testing device further includes:

[0022] selecting two other probes corresponding to two adjacent second monitoring pads, respectively, and when the signal excitation end and the signal detection end are respectively connected to the two adjacent second monitoring pads through the probes, sending an excitation signal through the signal excitation end and acquiring a detection signal through the signal detection end to measure a fourth capacitance; and

[0023] The fourth capacitance is taken as the sum of the parasitic capacitance of the test equipment and the parasitic capacitance of the probe introduced by the other two probes, and the parasitic capacitance of the probe introduced by the other two probes is obtained by using the second capacitance and the fourth capacitance.

[0024] In one aspect, the present invention provides a method for testing the capacitance of a semiconductor device, the method comprising:

[0025] Placing a wafer having the monitoring structure and the corresponding WAT test structure formed thereon on a carrier plate of a probe station, with the second surface of the wafer contacting the carrier plate, the test pads of the WAT test structure being arranged in the same manner as the monitoring pads of the monitoring structure, and the test pads of the WAT test structure being connected to semiconductor devices in the wafer;

[0026] Using the above detection method, the parasitic capacitance of the test equipment, the parasitic capacitance of the probes introduced by two adjacent probes, and the noise generated by the carrier plate are obtained;

[0027] making each probe of the probe card contact one of the test pads, connecting the signal excitation terminal and the signal detection terminal of the capacitance test device to two adjacent test pads respectively, sending an excitation signal through the signal excitation terminal, and receiving a detection signal through the signal detection terminal, so as to obtain a total capacitance; and

[0028] The parasitic capacitance of the test equipment, the parasitic capacitance of the probe, and the noise generated by the carrier plate are subtracted from the total capacitance to obtain a corresponding device capacitance test value.

[0029] The monitoring structure provided by the present invention is used to monitor the parasitic capacitance and carrier plate noise generated when the corresponding WAT test structure on the wafer is subjected to capacitance testing. The monitoring structure includes a plurality of monitoring pads formed on the surface of the wafer, and the monitoring pads are arranged according to the test pads in the WAT test structure. When the capacitance between two adjacent monitoring pads is tested using the same probe card and capacitance testing equipment as those used for capacitance testing of the WAT test structure, the obtained capacitance includes the parasitic capacitance of the test equipment introduced by the capacitance testing equipment and the parasitic capacitance of the probe introduced by the probe card probe. In addition, the monitoring structure also includes at least one conductive channel formed in the wafer, and the first monitoring pad is connected to the corresponding conductive channel, so that the capacitance measured by the first monitoring pad also includes the noise generated by the carrier plate on which the wafer is placed. Using the monitoring structure, the parasitic capacitance of the test equipment and the probe card and the noise generated by the carrier plate can be monitored.

[0030] The monitoring method provided by the present invention adopts the above-mentioned monitoring structure. By obtaining the parasitic capacitance of the test equipment, the parasitic capacitance of the probe introduced by the two adjacent probes, and the noise generated by the carrier plate, it is determined whether at least one of the parasitic capacitance of the test equipment, the parasitic capacitance of the probe, and the noise exceeds the corresponding set range. If exceeded, the corresponding abnormal information is fed back; if not exceeded, no abnormal information is fed back. This facilitates timely feedback when abnormalities occur in the parasitic capacitance and the carrier plate noise, thereby timely processing the abnormal information, reducing the impact of the abnormal information on the WAT test data, and helping to improve the accuracy of the WAT test data.

[0031] The semiconductor device capacitance testing method provided by the present invention adopts the above-mentioned monitoring structure and utilizes the above-mentioned monitoring method to obtain the parasitic capacitance of the test equipment, the parasitic capacitance of the probe and the noise generated by the carrier plate, and uses the WAT test structure to test to obtain the total capacitance including these parasitic capacitances, noise and device capacitance, and subtracts the parasitic capacitance of the test equipment, the parasitic capacitance of the probe and the noise generated by the carrier plate from the total capacitance to obtain the corresponding device capacitance test value. The device capacitance test value does not contain the parasitic capacitance of the test equipment, the parasitic capacitance of the probe and the noise generated by the carrier plate, and has high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a schematic diagram of using the WAT test structure to detect the capacitance of a semiconductor device.

[0033] Figure 2FIG. 1 is a schematic diagram of a monitoring structure according to an embodiment of the present invention.

[0034] Figure 3 4 is a flow chart of a monitoring method according to an embodiment of the present invention.

[0035] Figure 4A 2 is a schematic diagram of placing a wafer on a carrier and contacting a probe card probe with a monitoring pad according to a monitoring method according to an embodiment of the present invention.

[0036] Figure 4B Schematic diagram of measuring a first capacitance using a monitoring method according to an embodiment of the present invention.

[0037] Figure 4C FIG. 1 is a schematic diagram of measuring a second capacitance using a monitoring method according to an embodiment of the present invention.

[0038] Figure 4D FIG. 1 is a schematic diagram of measuring a third capacitance using a monitoring method according to an embodiment of the present invention.

[0039] Figure 5 The figure is a flow chart of a method for testing capacitance of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following is a further detailed description of the monitoring structure, monitoring method and semiconductor device capacitance testing method of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the terms "first" and "second" in the specification are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate. It should be understood that the drawings in the specification are all in a very simplified form and are not in precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention. In addition, spatially relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the drawing is inverted or positioned in other different ways (such as rotated), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0041] The embodiment of the present invention first relates to a monitoring structure. The monitoring structure can be arranged in a non-chip area (such as a cutting road area) of a wafer, and is used to monitor the parasitic capacitance and the carrier plate noise generated when the WAT test structure on the wafer is subjected to a capacitance test. The non-chip area can also be provided with a WAT ​​test structure, and the WAT test structure can be used to perform a WAT ​​test to obtain data such as resistance, capacitance, leakage current, threshold voltage and turn-on current of semiconductor devices formed in the wafer. According to an embodiment of the present invention, by monitoring the parasitic capacitance of a capacitance test device and a probe card and the noise generated by the carrier plate, the monitored parasitic capacitance and noise data can be used as reference data during a WAT ​​test (such as a capacitance test or a leakage current test), and feedback can be obtained in a timely manner when the parasitic capacitance and the noise are abnormal, so as to facilitate timely processing of abnormal information, thereby helping to improve the accuracy of the WAT test data.

[0042] Embodiments of the present invention Figure 2 Schematic diagram of a monitoring structure according to an embodiment of the present invention. Figure 2 The monitoring structure includes a plurality of monitoring pads (such as Figure 2 The exemplary PAD1, PAD2, PAD3, PAD4, PAD5, PAD6) and at least one conductive channel formed in the wafer 200 are shown.

[0043] The wafer 200 may include a first surface 200a and a second surface 200b facing each other. The monitoring pads, for example, and the test pads of the WAT test structure provided on the wafer 200 are both located on the first surface 200a. When performing the WAT test, the wafer 200 is fixed by adsorption by the carrier of the probe station, with the first surface 200a facing upward and the second surface 200b in contact with the carrier. The WAT test structure may have a structure as follows: Figure 1 The plurality of test pads 120 and the metal wires 110 connecting the test pads 120 and the semiconductor device to be tested are shown. Compared with the WAT test structure, the monitoring structure of the embodiment of the present invention can be used for the following Figure 1 The parasitic capacitance introduced by the capacitance test equipment and the probe card and the noise generated by the carrier plate are measured and monitored.

[0044] In order to obtain the same parasitic capacitance as when the semiconductor device capacitance is detected using the WAT test structure, the monitoring pad is arranged in accordance with the test pad in the corresponding WAT test structure. For example, the material, number and arrangement of the monitoring pads in the monitoring structure (such as the shape and size of each monitoring pad in each direction and the spacing between adjacent monitoring pads) are respectively consistent with the material, number and arrangement of the test pads in the corresponding WAT test structure, or in other words, the setting of the monitoring pads in the monitoring structure is completely copied from the setting of the test pads in the corresponding WAT test structure, so that the parasitic capacitance obtained by using the monitoring pad is the same as the parasitic capacitance introduced by the test pad in the corresponding WAT test structure. As an example, the multiple monitoring pads in the monitoring structure are arranged in sequence along the same direction, that is, the monitoring pads are arranged in a straight line. The number of monitoring pads in the monitoring structure is, for example, greater than or equal to the number of probes on the probe card used for capacitance testing of the WAT test structure.

[0045] The conductive path connects the first surface 200a and the second surface 200b of the wafer 200, i.e., the first surface 200a and the second surface 200b of the wafer 200 are electrically connected. As an example, the wafer 200 includes a substrate 210 and a dielectric layer 220 between the substrate 210 and the monitoring pad. The conductive path includes a first conductive path 221 passing through the dielectric layer 220 and a second conductive path 211 passing through the substrate 210 and connected to the first conductive path 221. The first conductive path 221 can be composed of a wiring layer and a conductive via formed in the dielectric layer 220. The second conductive path 211 is formed in the substrate 210. The substrate 210 can be a silicon substrate, a germanium (Ge) substrate, a silicon-germanium substrate, an SOI (Silicon On Insulator) substrate, a GOI (Germanium On Insulator) substrate, or other substrates that can support semiconductor devices. In this embodiment, for example, it is a silicon substrate. The silicon substrate can be doped to form a p-type doping region (such as doped boron or indium) and an n-type doping region (such as doped phosphorus or arsenic). The substrate 210 can be made conductive by being doped, so the second conductive channel 211 formed in the substrate 210 can be composed of a first doping type region (such as a p-type doping region) or a first doping type region (such as an n-type doping region) formed in the substrate 210. As an example, the second conductive channel 211 includes, for example, a p-type doping well (such as a doping well) extending from the upper surface of the substrate 210 to the inside of the substrate 210. Figure 2 The PW shown in FIG20 is a p-type doped region extending from the p-type doped well to the lower surface (i.e., the second surface 200b) of the substrate 210. The lower surface of the substrate 210 is the second surface 200b of the wafer 200, and the upper surface of the substrate 210 is away from the second surface 200b.

[0046] In this embodiment, the plurality of monitoring pads in the monitoring structure include at least one first monitoring pad (eg Figure 2 PAD2 and PAD5 shown) and at least one second monitoring pad (such as Figure 2 The PAD1, PAD3, PAD4, and PAD6 shown in the figure are connected to the conductive channel, and the second monitoring pad is not connected to the conductive channel. The monitoring pad adjacent to the first monitoring pad is the second monitoring pad. The settings of the first monitoring pad and the second monitoring pad can be set according to specific needs. For example, in one embodiment, the monitoring structure includes one first monitoring pad and a plurality of second monitoring pads. In another embodiment, the monitoring structure includes a plurality of first monitoring pads and a plurality of second monitoring pads. In order to avoid variable interference, the settings (including material, pattern, and size such as cross-sectional area, etc.) of the conductive channels connected to each of the first monitoring pads are the same.

[0047] As an example, the monitoring structure has a plurality of the first monitoring pads. The monitoring structure may include a plurality of repeated monitoring pad combinations, each of which is composed of one adjacent first monitoring pad and one adjacent second monitoring pad, or one adjacent first monitoring pad and two adjacent second monitoring pads (e.g. Figure 2 As shown in FIG), or composed of one second monitoring pad and two adjacent first monitoring pads. The monitoring pad combination can be tested as needed.

[0048] When using the monitoring structure to monitor the parasitic capacitance of the capacitance testing equipment and the probe card and the noise generated by the carrier plate, the same probe card and capacitance testing equipment as those used to perform capacitance testing on the corresponding WAT test structure can be used to test the capacitance of the capacitance structure connected to two adjacent monitoring pads. The capacitance data obtained includes the parasitic capacitance introduced by the capacitance testing equipment and the probe, which is convenient for monitoring the parasitic capacitance. Moreover, since the first monitoring pad is connected to the corresponding conductive channel, the noise signal generated by the carrier plate for carrying the wafer can be transmitted to the first monitoring pad through the conductive channel, and further transmitted to the capacitance testing equipment through the corresponding probe, which is convenient for monitoring the parasitic capacitance of the testing equipment and the probe card and the noise generated by the carrier plate.

[0049] The embodiment of the present invention also relates to a monitoring method. The monitoring method uses the monitoring structure described in the above embodiment to monitor the parasitic capacitance and carrier plate noise generated when the WAT test structure on the wafer is subjected to capacitance testing. Figures 3 to 4B The monitoring method is described.

[0050] Reference Figure 3 and Figure 4A According to the monitoring method of the embodiment of the present invention, step S11 is first performed to place the wafer 200 having the monitoring structure formed thereon on the carrier plate 300 of the probe station, and to make each probe PIN (such as Figure 4A The PIN1 to PIN6 shown in the figure are in contact with the corresponding monitoring pads respectively, wherein the first monitoring pad forms an electrical path with the carrier plate 300 through the conductive channel in the wafer 200, and the second monitoring pad does not form an electrical path with the carrier plate 300. The probe station can also, for example, perform electrical testing on the WAT test structure on the same wafer 200. The carrier plate 300, for example, vacuum-adsorbs the second surface 200b of the wafer 200 to fix the wafer 200. The probe card has the same structure and size as the probe card for performing capacitance testing on the WAT test structure, for example, it is a probe card of the same model from the same manufacturer, to ensure that the probe parasitic capacitance obtained by the monitoring method is the same as the probe parasitic capacitance generated when the WAT test structure is subjected to capacitance testing, thereby reducing variable interference.

[0051] Reference Figure 3 Then, step S12 is performed, using a capacitance test device for performing a capacitance test, sending an excitation signal through the signal excitation terminal of the capacitance test device and obtaining the corresponding capacitance through the monitoring signal of the signal detection terminal of the capacitance test device. Specifically, the following test may include testing the first capacitor C1, the second capacitor C2, and the third capacitor C3 described below. It should be noted that the following test is performed in the order of measuring the first capacitor C1, the second capacitor C2, and the third capacitor C3 in sequence for example only. The first capacitor C1, the second capacitor C2, and the third capacitor C3 may also be tested in other orders.

[0052] Reference Figure 4B For example, the first capacitor C1 is measured first, wherein the signal excitation end 10 and the signal detection end 20 of the capacitance test device are respectively connected to an adjacent second monitoring pad (for example, monitoring pad PAD1) and a first monitoring pad (for example, monitoring pad PAD2) through two adjacent probes (for example, probe PIN1 and probe PIN2).

[0053] According to the functional settings of the capacitance test equipment, the corresponding capacitance value can be obtained by sending an excitation signal from the signal excitation terminal 10 and obtaining a detection signal through the signal detection terminal 20. As needed, the signal excitation terminal 10 and the signal detection terminal 20 can be connected to two adjacent probes in sequence, so that the capacitance of the capacitor structure connected by each two probes can be measured. Each measured capacitance includes the probe parasitic capacitance introduced by the two connected probes during the test. As an example, the excitation signal emitted by the capacitance test equipment is the same each time the capacitance value is tested.

[0054] When measuring the first capacitor C1, the signal excitation end 10 is connected to the second monitoring pad (for example, monitoring pad PAD1), that is, connected to a plate of the capacitor structure being tested, which is used to send an excitation signal, and the signal detection end 20 is connected to the first monitoring pad (for example, monitoring pad PAD2), that is, connected to another plate of the capacitor structure being tested, which is used to form a detection signal, and the detection signal can be collected by the capacitor testing equipment and the data of the first capacitor C1 is obtained according to the collected signal. Since the first monitoring pad is also connected to the carrier plate 300 through the above-mentioned conductive channel in the wafer 200, the detection signal obtained by the signal detection end 20 is also related to the signal on the surface of the carrier plate 300, that is, the capacitor test loop formed by the capacitor testing equipment, probe, monitoring pad and capacitor structure also includes the noise generated by the carrier plate 300. The noise is reflected in the data fluctuation of the first capacitor C1.

[0055] like Figure 4B As shown, the first capacitance C1 measured by the above method is mainly composed of the parasitic capacitance Ccb of the test equipment introduced by the capacitance test equipment, the parasitic capacitance Cpin of the probe introduced by the two adjacent probes located in the capacitance test loop, the parasitic capacitance Cpad between the pads introduced by the two monitoring pads located in the capacitance test loop, and the capacitance change caused by the noise of the carrier plate 300. The study found that due to the small longitudinal cross-sectional area of ​​the monitoring pad, the parasitic capacitance Cpad between the pads in the first capacitance C1 can be ignored. Therefore, the first capacitance C1 can be regarded as the sum of the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe introduced by the two adjacent probes, and the noise of the carrier plate 300.

[0056] Reference Figure 4C Using the capacitance test equipment, the signal excitation terminal 10 and the signal detection terminal 20 are disconnected from the probe card. The excitation signal is emitted through the signal excitation terminal 10, and the detection signal is received through the signal detection terminal 20. The second capacitance C2 can be measured. When measuring the second capacitance C2, since the capacitance test equipment is not connected to any probe or monitoring pad, the second capacitance C2 is the parasitic capacitance Ccb of the test equipment.

[0057] Reference Figure 4DThen, using the capacitance test equipment, the signal excitation terminal 10 and the signal detection terminal 20 are connected to two adjacent probes, while the probe card is disconnected from the monitoring pad. An excitation signal is emitted through the signal excitation terminal 10, and a detection signal is received through the signal detection terminal 20, to measure the third capacitance C3. When measuring the third capacitance C3, the capacitance test equipment is electrically connected to the probes but not to the monitoring pad. The third capacitance C3 is the sum of the parasitic capacitance Ccb of the test equipment and the parasitic capacitance Cpin of the probes introduced by the two adjacent probes.

[0058] Reference Figure 3 , then execute step S13, taking the first capacitor C1 as the sum of the test device parasitic capacitance Ccb introduced by the capacitance test device, the probe parasitic capacitance Cpin introduced by the corresponding two probes, and the noise introduced by the carrier plate 300, taking the second capacitor C2 as the test device parasitic capacitance Ccb, and taking the third capacitor C3 as the sum of the test device parasitic capacitance Ccb and the probe parasitic capacitance Cpin, to obtain the test device parasitic capacitance Ccb, the probe parasitic capacitance Cpin, and the noise generated by the carrier plate 300.

[0059] Since the third capacitor C3 is the sum of the parasitic capacitance Ccb of the test device and the parasitic capacitance Cpin of the probe, and the second capacitor C2 is the parasitic capacitance Ccb of the test device, in step S13, the parasitic capacitance Cpin of the probe can be calculated by subtracting the third capacitor C3 from the second capacitor C2. In addition, since the first capacitor C1 is the sum of the parasitic capacitance Ccb of the test device, the parasitic capacitance Cpin of the probe, and the capacitance change caused by the noise of the carrier plate 300, the magnitude of the noise can be obtained by subtracting the first capacitor C1 from the third capacitor C3.

[0060] In some embodiments, when monitoring is performed using two adjacent probes, the two adjacent probes can be connected to two second monitoring pads (such as monitoring pads PAD3 and PAD4), and the monitoring method may further include: selecting two other probes corresponding to the two adjacent second monitoring pads, respectively, using the capacitance testing device, when the signal excitation end 10 and the signal detection end 20 of the capacitance testing device are respectively connected to the two adjacent second monitoring pads through the probes, sending an excitation signal through the signal excitation end 10, obtaining a detection signal through the signal detection end 20, and measuring the fourth capacitance C4. Since the second monitoring pad is not connected to the crystal The conductive path within circle 200 is connected, and the fourth capacitor C4 can be regarded as the sum of the parasitic capacitance Ccb of the test device, the probe parasitic capacitance Cpin introduced by the other two probes located in the capacitor test loop, and the parasitic capacitance Cpad between pads introduced by the two second monitoring pads located in the capacitor test loop. Here, the parasitic capacitance Cpad between pads can be ignored, and the fourth capacitor is the sum of the parasitic capacitance Ccb of the test device introduced by the capacitor test device and the parasitic capacitance of the probe introduced by the other two probes; then, the fourth capacitor C4 and the second capacitor C2 are used to obtain the parasitic capacitance Cpin of the probe introduced by the other two probes.

[0061] Reference Figure 3 Then, step S14 is executed to determine whether at least one of the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe, and the noise generated by the carrier plate 300 exceeds the corresponding set range. If exceeded, the corresponding abnormal information is fed back; if not exceeded, no abnormal information is fed back.

[0062] The setting ranges corresponding to the noise generated by the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe, or the carrier plate 300 can be set according to the actual test requirements. When the noise generated by the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe, or the carrier plate 300 does not exceed the corresponding setting ranges, it indicates that the test environment of the WAT test is normal. Under this test environment, the corresponding WAT test structure can be used to perform WAT testing (such as semiconductor device capacitance testing or leakage current testing). In addition, when performing the WAT test, the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe, or the noise generated by the carrier plate 300 obtained by the above method can be used as reference data. When the noise generated by the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe, or the carrier plate 300 exceeds the corresponding setting ranges, it indicates that the corresponding capacitance test equipment, probe, or carrier plate 300 is abnormal. In order not to affect the WAT test data, corresponding processing can be performed. For example, if the noise generated by the carrier plate 300 is abnormal, the charge of the probe and the carrier plate 300 can be released, and then the test is performed again. After processing, the above-mentioned monitoring method can be used again to monitor the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe or the noise generated by the carrier plate 300. If it no longer exceeds the corresponding set range, the corresponding WAT test structure can be used to test the capacitance of the semiconductor device. If the data of the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe or the noise generated by the carrier plate 300 still exceeds the corresponding set range, further investigation can be carried out based on the feedback abnormal information.

[0063] In the monitoring method described in the above embodiment, by obtaining the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe or the noise generated by the carrier plate 300, it is determined whether at least one of the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe and the noise generated by the carrier plate 300 exceeds the corresponding set range. If exceeded, the corresponding abnormal information is fed back; if not exceeded, no abnormal information is fed back. This facilitates timely feedback when abnormalities occur in the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe and the noise generated by the carrier plate 300, thereby timely processing the abnormal information to reduce the impact of the abnormal information on the WAT test data, thereby helping to improve the accuracy of the WAT test data.

[0064] The embodiment of the present invention further relates to a method for testing the capacitance of a semiconductor device, which adopts the monitoring structure described in the above embodiment and utilizes the above monitoring method.

[0065] Reference Figure 5 The semiconductor device capacitance testing method includes, for example, the following process.

[0066] First, in step S21, the wafer 200 having the monitoring structure described in the above embodiment and the corresponding WAT test structure is placed on the carrier plate 300 of the probe station, and the second surface 100b of the wafer 200 contacts the carrier plate 300. The test pads of the WAT test structure are the same as the settings of the monitoring pads of the monitoring structure (for example, the material, quantity and arrangement of the monitoring pads in the monitoring structure are respectively consistent with the material, quantity and arrangement of the test pads in the corresponding WAT test structure). In the WAT test structure, the test pads are connected to the semiconductor devices in the wafer. The monitoring structure is used to monitor the parasitic capacitance generated when the capacitance test is performed using the WAT test structure and the noise generated by the carrier plate 300.

[0067] Next, the above monitoring structure and the above monitoring method are used to obtain the parasitic capacitance Ccb of the test equipment introduced by the capacitance test equipment, the parasitic capacitance Cpin of the probes introduced by the two adjacent probes, and the noise generated by the carrier plate 300 .

[0068] Afterwards, each probe on the probe card is brought into contact with a test pad of the WAT test structure, and the signal excitation terminal 10 and the signal detection terminal 20 of the capacitance test device are respectively connected to two adjacent test pads. The excitation signal is sent through the signal excitation terminal 10, and the detection signal is obtained through the signal detection terminal 20 to obtain a total capacitance. Figure 1 The total capacitance is primarily composed of the capacitance of the semiconductor device connected to the corresponding test pad, the parasitic capacitance Ccb of the test equipment introduced by the capacitance test equipment, the parasitic capacitance Cpin of the probe introduced by the probe card, and the noise generated by the carrier plate 300. As an example, the excitation signal is the same as the excitation signal used to obtain the first capacitance C1, the second capacitance C2, and the third capacitance C3 in the monitoring method.

[0069] Then, the total capacitance is subtracted from the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe, and the noise generated by the carrier 300 to obtain the corresponding device capacitance test value. In this embodiment, the device capacitance test value includes, for example, Figure 1 The capacitances formed by different electrodes of the MOS transistor and the capacitance Cint formed by the metal wiring connecting the MOS transistor and the test pad 120 are shown.

[0070] In the semiconductor device capacitance testing method of an embodiment of the present invention, the monitoring structure in the above embodiment is adopted and the monitoring method in the above embodiment is used to obtain the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe and the noise generated by the carrier plate 300, and the corresponding WAT test structure is used to test to obtain the total capacitance including these parasitic capacitances, noise and semiconductor device capacitance. The total capacitance is subtracted from the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe and the noise generated by the carrier plate 300, and the corresponding device capacitance test value can be obtained. The device capacitance test value does not contain the parasitic capacitance Ccb of the test equipment, the parasitic capacitance Cpin of the probe and the noise generated by the carrier plate 300, and has high accuracy.

[0071] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A monitoring structure, characterized in that: Used to monitor parasitic capacitance and carrier plate noise generated when performing capacitance testing using a WAT ​​test structure on a wafer, the monitoring structure includes: A plurality of monitoring pads are formed on the surface of the wafer, wherein the monitoring pads and the test pads of the WAT test structure are located on the first surface of the wafer, and the monitoring pads are arranged according to the test pads in the WAT test structure; At least one conductive channel is formed in the wafer, the conductive channel connecting the first surface and a second surface of the wafer opposite to the first surface, wherein the multiple monitoring pads include at least one first monitoring pad and at least one second monitoring pad, the first monitoring pad is connected to the conductive channel and the second monitoring pad is not connected to the conductive channel, and the monitoring pad adjacent to the first monitoring pad is the second monitoring pad.

2. The monitoring structure according to claim 1, characterized in that: The multiple monitoring pads are arranged in sequence along the same direction.

3. The monitoring structure according to claim 1, wherein: The monitoring structure includes multiple repeated monitoring pad combinations, each of which is composed of one adjacent first monitoring pad and one adjacent second monitoring pad, or one first monitoring pad and two adjacent second monitoring pads, or one second monitoring pad and two adjacent first monitoring pads.

4. The monitoring structure according to claim 1, wherein: The number of the monitoring pads in the monitoring structure is greater than or equal to the number of probes on a probe card used for performing capacitance testing on the WAT test structure.

5. The monitoring structure according to claim 1, wherein: The wafer includes a substrate and a dielectric layer between the substrate and the monitoring pad. The conductive path includes a first conductive path passing through the dielectric layer and a second conductive path passing through the substrate and connected to the first conductive path.

6. The monitoring structure according to claim 5, characterized in that: The first conductive channel is composed of a wiring layer and a conductive through-hole formed in the dielectric layer.

7. The monitoring structure according to claim 5, characterized in that: The second conductive channel is formed by a p-type doping region or an n-type doping region formed in the substrate.

8. A monitoring method, characterized in that: Using the monitoring structure according to any one of claims 1 to 7, the monitoring method includes: Placing the wafer with the monitoring structure formed thereon on a carrier plate of a probe station, and making each probe of the probe card contact one of the monitoring pads; Measuring capacitance using a capacitance testing device for performing a capacitance test on the WAT test structure, wherein a signal excitation end of the capacitance testing device emits an excitation signal and a signal detection end receives a detection signal, a first capacitance is measured when the signal excitation end and the signal detection end are respectively connected to an adjacent second monitoring pad and a adjacent first monitoring pad through two adjacent probes, a second capacitance is measured when the signal excitation end and the signal detection end are disconnected from the probe card, and a third capacitance is measured when the signal excitation end and the signal detection end are connected to two adjacent probes and the probe card is disconnected from the monitoring pads; Taking the first capacitance as the sum of the parasitic capacitance of the test device introduced by the capacitance test device, the parasitic capacitance of the probe introduced by the two adjacent probes, and the noise introduced by the carrier plate, taking the second capacitance as the parasitic capacitance of the test device, and taking the third capacitance as the sum of the parasitic capacitance of the test device and the parasitic capacitance of the probe, the parasitic capacitance of the test device, the parasitic capacitance of the probe introduced by the two adjacent probes, and the noise generated by the carrier plate are obtained; and It is determined whether at least one of the parasitic capacitance of the test device, the parasitic capacitance of the probe, and the noise generated by the carrier plate exceeds a corresponding set range. If so, corresponding abnormal information is fed back; otherwise, no abnormal information is fed back.

9. The monitoring method according to claim 8, wherein: Measuring capacitance using the capacitance testing device further includes: selecting two other probes corresponding to two adjacent second monitoring pads, respectively, and when the signal excitation end and the signal detection end are respectively connected to the two adjacent second monitoring pads through the probes, sending an excitation signal through the signal excitation end and acquiring a detection signal through the signal detection end to measure a fourth capacitance; and The fourth capacitance is taken as the sum of the parasitic capacitance of the test equipment and the parasitic capacitance of the probe introduced by the other two probes, and the parasitic capacitance of the probe introduced by the other two probes is obtained by using the second capacitance and the fourth capacitance.

10. A method for testing the capacitance of a semiconductor device, characterized in that: include: placing a wafer having the monitoring structure according to any one of claims 1 to 7 and the corresponding WAT test structure on a carrier plate of a probe station, wherein the second surface of the wafer contacts the carrier plate, the test pads of the WAT test structure are arranged in the same manner as the monitoring pads of the monitoring structure, and in the WAT test structure, the test pads are connected to semiconductor devices in the wafer; Using the monitoring method according to claim 8 or 9, the parasitic capacitance of the test device, the parasitic capacitance of the probe introduced by two adjacent probes, and the noise generated by the carrier plate are obtained; Each probe of the probe card is brought into contact with one of the test pads, and the signal excitation terminal and the signal detection terminal of the capacitance test device are respectively connected to two adjacent test pads, an excitation signal is emitted through the signal excitation terminal, and a detection signal is received through the signal detection terminal to obtain a total capacitance; as well as The parasitic capacitance of the test equipment, the parasitic capacitance of the probe, and the noise generated by the carrier plate are subtracted from the total capacitance to obtain a corresponding device capacitance test value.

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