An on-chip integrated SiC MOSFET short-circuit protection circuit and chip

Abstract

This invention discloses an on-chip integrated SiC MOSFET short-circuit protection circuit and chip. The protection circuit includes: a logic control unit for processing input signal Vin and a short-circuit fault signal, the output of which is connected to a driving circuit, and inputs a fault signal to the driving circuit when a short-circuit fault occurs; a driving circuit for driving the SiC MOSFET; and a short-circuit protection circuit for sending a short-circuit fault signal to the logic control unit when a short-circuit fault occurs. ds A detection circuit is used to detect the drain-source current I of the SiC MOSFET. ds The value is then input to the short-circuit protection circuit along with the drain-source current I. ds A proportional voltage; a reset circuit for resetting the short-circuit protection circuit after it has completed its short-circuit protection action; this invention adds two comparators to the short-circuit protection circuit and sets different threshold voltages to determine whether an HSF or FUL fault has occurred. This invention can be widely applied in the field of short-circuit protection technology.

Description

Technical Field

[0001] This invention relates to the field of short-circuit protection technology for power devices, and more particularly to an on-chip integrated SiCMOSFET short-circuit protection circuit and chip. Background Technology

[0002] In recent years, SiC MOSFETs have been widely used in motor drives, new energy vehicles, photovoltaic power generation and other fields due to their high voltage resistance, high temperature resistance and low conduction loss. SiC MOSFETs have unsaturated drain-source current characteristics and can withstand very high currents under short-circuit conditions. Therefore, short-circuit protection circuits for SiC MOSFETs are crucial to ensure their high reliability.

[0003] Currently, short-circuit protection circuits for SiC MOSFETs are mainly divided into three categories. The first category is the desaturation overcurrent detection method, which detects the drain-source current I of the SiC MOSFET. ds and drain-source voltage V ds To determine a short circuit fault, when a short circuit fault occurs, I... ds It will rise rapidly and V ds Rise to bus voltage, by detecting I ds and V ds This method can determine whether HSF or FUL has occurred, but its response time is slow because it requires setting the leading-edge blanking time. The second type is based on source inductance detection, which detects I by connecting a sampling resistor and a sampling capacitor in parallel with the source parasitic inductance. ds This method is the easiest to integrate and offers the fastest protection speed. The third type is the gate voltage detection method. When an HSF occurs, the Miller plateau of the gate-source voltage disappears; when a FUL occurs, a voltage spike appears in the gate-source voltage. This spike is detected by measuring V... GS The state can indicate the occurrence of a short circuit fault, but this method has low detection accuracy and is difficult to integrate. Summary of the Invention

[0004] In order to at least partially solve one of the technical problems existing in the prior art, the purpose of this invention is to provide a fast, reliable, and easily integrated SiC MOSFET short-circuit protection circuit and chip.

[0005] The technical solution adopted in this invention is:

[0006] An on-chip integrated SiC MOSFET short-circuit protection circuit includes:

[0007] The logic control unit is used to process the input signal Vin and the short-circuit fault signal. Its output terminal is connected to the drive circuit. When a short-circuit fault occurs, it inputs a fault signal to the drive circuit. The first input terminal of the logic control unit is connected to the input signal Vin, the second input terminal is connected to the output terminal of the short-circuit protection circuit, and the third input terminal is connected to the output terminal of the reset circuit.

[0008] A driving circuit is used to drive a SiC MOSFET; the input terminal of the driving circuit is connected to the output terminal of the logic control unit, and the output terminal is connected to the gate of the SiC MOSFET.

[0009] A short-circuit protection circuit is used to send a short-circuit fault signal to the logic control unit when a short-circuit fault occurs; the first input terminal of the short-circuit protection circuit is connected to I... ds The output of the detection circuit is connected to the logic control unit; the short-circuit protection circuit has two comparators, which determine whether an HSF fault or a FUL fault has occurred by combining a preset threshold voltage.

[0010] I ds A detection circuit is used to detect the drain-source current I of the SiC MOSFET. ds The value is then input to the short-circuit protection circuit along with the drain-source current I. ds A voltage that is directly proportional to the voltage; the I ds The input terminal of the detection circuit is connected to the source of the SiC MOSFET;

[0011] A reset circuit is used to reset the short-circuit protection circuit that has completed the short-circuit protection action; the input terminal of the reset circuit is connected to the input signal Vin, and the output terminal is connected to the third input terminal of the logic control unit.

[0012] Furthermore, the logic control unit includes a first SR latch m1, a second inverter inv2, and a first AND gate and1;

[0013] The R input terminal of the first SR latch m1 is connected to the output terminal of the reset circuit, and the S input terminal is connected to the output terminal of the short-circuit protection circuit; the input terminal of the second inverter inv2 is connected to the Q output terminal of the latch m1, and the output terminal is connected to one input terminal of the first AND gate and1; the other input terminal of the first AND gate and1 is connected to the input signal Vin, and the output terminal of the first AND gate and1 is connected to the output terminal of the logic control unit.

[0014] Furthermore, the driving circuit includes a third inverter inv3, a first buffer buffer1, a second buffer buffer2, multiple parallel PLDMOS and multiple parallel NLDMOS;

[0015] The input terminal of the third inverter inv3 is connected to the output terminal of the logic control unit, and the output terminal is connected to the input terminal of the first buffer buffer1 and the input terminal of the second buffer buffer2. The output terminal of the first buffer buffer1 is connected to the gate of a plurality of parallel PLDMOS. The output terminal of the second buffer buffer2 is connected to the gate of a plurality of parallel NLDMOS. The source of the parallel NLDMOS is connected to ground GND, and the drain is connected to the drain of the parallel PLDMOS. The source of the parallel PLDMOS is connected to the power supply VDDH. The drain of the NLDMOS and the drain of the PLDMOS are connected as the output terminal for driving short circuit and connected to the gate of the SiC MOSFET.

[0016] Furthermore, the I ds The detection circuit includes a first diode D1, a first capacitor C1, a first resistor R1, a second diode D2, and a second resistor R2;

[0017] The cathode of the first diode D1 is connected to ground (GND), and the anode is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the cathode of the second diode D2; the anode of the diode D2 is connected to the source of the SiC MOSFET; the first capacitor C1 is connected in parallel with the first diode D1; and the second resistor R2 is connected in parallel with the second diode D2.

[0018] Furthermore, the short-circuit protection circuit includes a first comparator COM1, a second comparator COM2, a third comparator COM3, a first OR gate OR1, a first NAND gate NAND1, and a level shifter.

[0019] The non-inverting input of the first comparator com1 is connected to I. ds The output voltage Vo of the detection circuit is connected to the inverting input terminal of the first threshold voltage Vref1; the non-inverting input terminal of the second comparator com2 is connected to the voltage V. div The inverting input is connected to the second threshold voltage Vref2, where the voltage V... div The signal is sampled from a SiC MOSFET; the non-inverting input of the third comparator com1 is connected to I. ds The output voltage Vo of the detection circuit is connected to the third threshold voltage Vref3 at its inverting input terminal.

[0020] The two inputs of the first OR gate OR1 are connected to the outputs of the second comparator COM2 and the third comparator COM3, respectively, and the output is connected to one input of the first NAND gate NAND1; the other input of the first NAND gate NAND1 is connected to the output of the first comparator COM1, and the output is connected to the input of the level shifter; the output of the level shifter is connected to the S input of the latch M1.

[0021] Furthermore, the voltage V div The voltage V is obtained through a sampling circuit, which includes a second capacitor C2 and a third capacitor C3. The second capacitor C2 and the third capacitor C3 are connected in series between the drain and source of the SiC MOSFET. The voltage V is obtained at the connection point of the second capacitor C2 and the third capacitor C3. div .

[0022] Furthermore, the reset circuit includes a first inverter inv1 and a first NOR gate nor1;

[0023] The input terminal of the first inverter inv1 is connected to the input signal Vin, and the output terminal is connected to one input terminal of the first NOR gate nor1; the other input terminal of the first NOR gate nor1 is connected to the input signal Vin, and the output terminal is connected to the R input terminal of the latch m1.

[0024] Furthermore, the SiC MOSFET short-circuit protection circuit also includes a digital isolator;

[0025] The digital isolator is used to transmit and convert the digital signal at the input end, and its output end outputs the input signal Vin.

[0026] Furthermore, the SiC MOSFET short-circuit protection circuit is integrated using BCD technology.

[0027] Another technical solution adopted in this invention is:

[0028] A chip comprising an on-chip integrated SiC MOSFET short-circuit protection circuit as described above.

[0029] The beneficial effects of this invention are as follows: This invention improves upon the source parasitic inductance detection method by adding two comparators to the short-circuit protection circuit and setting different threshold voltages to determine whether an HSF or FUL fault has occurred. Furthermore, by reasonably setting different threshold voltages, the protection speed of HSF and FUL can be improved, and the required values ​​of capacitor C1, resistor R1, and resistor R2 can be significantly reduced, making this invention both fast protection and easy to integrate. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a block diagram illustrating the principle of the SiC MOSFET short-circuit protection circuit in an embodiment of the present invention.

[0032] Figure 2 This is a circuit diagram of the SiC MOSFET short-circuit protection circuit in an embodiment of the present invention.

[0033] Figure 3 This is the output waveform of the SiC MOSFET under normal operation during a dual-pulse test in an embodiment of the present invention.

[0034] Figure 4 This is the output waveform of HSF when the SiC MOSFET is not short-circuited in an embodiment of the present invention.

[0035] Figure 5 This is the output waveform of FUL when the SiC MOSFET is not short-circuited in an embodiment of the present invention.

[0036] Figure 6 This is a partial output waveform of HSF generated by the SiC MOSFET after the short-circuit protection circuit of the present invention is applied in an embodiment of the present invention.

[0037] Figure 7 This is a partial output waveform of the SiC MOSFET after the short-circuit protection circuit of the present invention is applied in an embodiment of the present invention, which results in FUL. Detailed Implementation

[0038] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0039] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0040] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first" or "second" is used, it is only for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features. Furthermore, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0041] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0042] Terminology Explanation:

[0043] HSF: refers to a fault that occurs when a switching transistor is turned on when the load is short-circuited.

[0044] FUL: refers to a fault caused by a sudden short circuit in the load when the switching transistor is fully turned on.

[0045] BCD process: BCD stands for Bipolar, CMOS, and DMOS. BCD process means that the same process includes all three processes: Bipolar, CMOS, and DMOS.

[0046] like Figure 1 As shown, this embodiment provides an on-chip integrated SiC MOSFET short-circuit protection circuit, the structure of which includes a logic control unit, a drive circuit, a reset circuit, a short-circuit protection circuit, and an I / O circuit. ds Detection circuit;

[0047] The logic control unit is used to process the input signal Vin and the short-circuit fault signal. Its output terminal is connected to the drive circuit. When a short-circuit fault occurs, it inputs a fault signal to the drive circuit. The first input terminal of the logic control unit is connected to the input signal Vin, the second input terminal is connected to the output terminal of the short-circuit protection circuit, and the third input terminal is connected to the output terminal of the reset circuit.

[0048] A driving circuit is used to drive a SiC MOSFET; the input terminal of the driving circuit is connected to the output terminal of the logic control unit, and the output terminal is connected to the gate of the SiC MOSFET.

[0049] A short-circuit protection circuit is used to send a short-circuit fault signal to the logic control unit when a short-circuit fault occurs; the first input terminal of the short-circuit protection circuit is connected to I... ds The output of the detection circuit is connected to the logic control unit; the short-circuit protection circuit has two comparators, which determine whether an HSF fault or a FUL fault has occurred by combining a preset threshold voltage.

[0050] I ds A detection circuit is used to detect the drain-source current I of the SiC MOSFET. ds The value is then input to the short-circuit protection circuit along with the drain-source current I. ds A voltage that is directly proportional to the voltage; the I ds The input terminal of the detection circuit is connected to the source of the SiC MOSFET;

[0051] A reset circuit is used to reset the short-circuit protection circuit that has completed the short-circuit protection action; the input terminal of the reset circuit is connected to the input signal Vin, and the output terminal is connected to the third input terminal of the logic control unit.

[0052] See Figure 2 In some embodiments, the logic control unit includes a first SR latch m1, a second inverter inv2, and a first AND gate and1;

[0053] The R input terminal of the first SR latch m1 is connected to the output terminal of the reset circuit, and the S input terminal is connected to the output terminal of the short-circuit protection circuit; the input terminal of the second inverter inv2 is connected to the Q output terminal of the latch m1, and the output terminal is connected to one input terminal of the first AND gate and1; the other input terminal of the first AND gate and1 is connected to the input signal Vin, and the output terminal of the first AND gate and1 is connected to the output terminal of the logic control unit.

[0054] See Figure 2 In some embodiments, the driving circuit includes a third inverter inv3, a first buffer buffer1, a second buffer buffer2, a plurality of parallel PLDMOS and a plurality of parallel NLDMOS;

[0055] The input terminal of the third inverter inv3 is connected to the output terminal of the logic control unit, and the output terminal is connected to the input terminal of the first buffer buffer1 and the input terminal of the second buffer buffer2. The output terminal of the first buffer buffer1 is connected to the gate of a plurality of parallel PLDMOS. The output terminal of the second buffer buffer2 is connected to the gate of a plurality of parallel NLDMOS. The source of the parallel NLDMOS is connected to ground GND, and the drain is connected to the drain of the parallel PLDMOS. The source of the parallel PLDMOS is connected to the power supply VDDH. The drain of the NLDMOS and the drain of the PLDMOS are connected as the output terminal for driving short circuit and connected to the gate of the SiC MOSFET.

[0056] See Figure 2 In some embodiments, the I ds The detection circuit includes a first diode D1, a first capacitor C1, a first resistor R1, a second diode D2, and a second resistor R2;

[0057] The cathode of the first diode D1 is connected to ground (GND), and the anode is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the cathode of the second diode D2; the anode of the diode D2 is connected to the source of the SiC MOSFET; the first capacitor C1 is connected in parallel with the first diode D1; and the second resistor R2 is connected in parallel with the second diode D2.

[0058] See Figure 2 In some embodiments, the short-circuit protection circuit includes a first comparator COM1, a second comparator COM2, a third comparator COM3, a first OR gate OR1, a first NAND gate NAND1, and a level shifter.

[0059] The non-inverting input of the first comparator com1 is connected to I. ds The output voltage Vo of the detection circuit is connected to the inverting input terminal of the first threshold voltage Vref1; the non-inverting input terminal of the second comparator com2 is connected to the voltage V. div The inverting input is connected to the second threshold voltage Vref2, where the voltage V... div The signal is sampled from a SiC MOSFET; the non-inverting input of the third comparator com1 is connected to I. ds The output voltage Vo of the detection circuit is connected to the third threshold voltage Vref3 at its inverting input terminal.

[0060] The two inputs of the first OR gate OR1 are connected to the outputs of the second comparator COM2 and the third comparator COM3, respectively, and the output is connected to one input of the first NAND gate NAND1; the other input of the first NAND gate NAND1 is connected to the output of the first comparator COM1, and the output is connected to the input of the level shifter; the output of the level shifter is connected to the S input of the latch M1.

[0061] Optionally, the voltage V div The voltage V is obtained through a sampling circuit, which includes a second capacitor C2 and a third capacitor C3. The second capacitor C2 and the third capacitor C3 are connected in series between the drain and source of the SiC MOSFET. The voltage V is obtained at the connection point of the second capacitor C2 and the third capacitor C3. div .

[0062] See Figure 2 In some embodiments, the reset circuit includes a first inverter inv1 and a first NOR gate nor1;

[0063] The input terminal of the first inverter inv1 is connected to the input signal Vin, and the output terminal is connected to one input terminal of the first NOR gate nor1; the other input terminal of the first NOR gate nor1 is connected to the input signal Vin, and the output terminal is connected to the R input terminal of the latch m1.

[0064] See Figure 2 As an optional implementation, the SiC MOSFET short-circuit protection circuit also includes a digital isolator; the digital isolator is used to transmit and convert the digital signal at the input terminal, and its output terminal outputs the input signal Vin.

[0065] The circuit described above will be explained in detail below with reference to the accompanying drawings and specific embodiments.

[0066] (1) The working mode of the logic control unit:

[0067] When the SiC MOSFET is operating normally, the overcurrent fault signal I... oc Since the level is low, the short-circuit fault signal Fault, latched by the m1 register, is also low, thus not affecting the drive signal driving the SiC MOSFET gate. When a short-circuit fault occurs, I... oc The signal will become a high-level pulse. After passing through the SR latch, the signal Fault will become high. After passing through the inverter inv2, Fault will be ANDed with the output Vin of the digital isolator to finally generate a low output level.

[0068] (2) Operating mode of the drive circuit:

[0069] The output of the logic control unit is inverted by inverter inv3 and then simultaneously connected to the input terminals of buffer1 and buffer2. Buffer1 and buffer2 are voltage buffers that drive parallel PLDMOS and parallel NLDMOS, respectively. In this example, there are many parallel PLDMOS and NLDMOS used to drive the SiC MOSFET, and their aspect ratios are also relatively large. Therefore, both buffer1 and buffer2 have strong current driving capabilities.

[0070] (3)I ds How the detection circuit works:

[0071] When the SiC MOSFET is turned on, I ds As the voltage rises, an induced voltage Vss will be generated at the source of the power supply due to the presence of the source parasitic inductance, where Vss = dI. ds / dt, Vss is negative relative to ground GND. Capacitor C1, resistor R1, and resistor R2 form an RC integrator that outputs the integrated voltage Vo, where Vo=∫{Vss / (R1+R2)C1}dt. Therefore, detecting Vo immediately determines whether a short-circuit fault has occurred. When the SiC MOSFET is normally turned on, I ds At normal levels, Vo is below the threshold voltage; when an HSF fault occurs while the SiC MOSFET is on, I... ds The voltage rises rapidly, and Vo will exceed the threshold voltage. When the SiC MOSFET is turned on normally without an HSF fault, Vss changes from a negative value to GND, and Vo discharges back to GND through D2. When an FUL fault occurs again, Vo will exceed the set threshold voltage.

[0072] (4) Operating mode of short circuit protection circuit:

[0073] The input terminals of the short-circuit protection circuit are respectively connected to I ds The output of the detection circuit is connected to the output of the reset circuit, and its output is connected to the logic control unit. It is used to send a fault signal to the logic control unit when a short-circuit fault occurs. The short-circuit protection circuit includes a second capacitor C2 and a third capacitor C3, and the voltage divider V between capacitors C2 and C3... div Connect to the non-inverting input of COM2.

[0074] When the SiC MOSFET is normally turned on, Vo does not exceed the first threshold voltage Vref1, and the Ioc output is low. When the SiC MOSFET experiences an HSF fault, Vo exceeds the first threshold voltage Vref1, COM1 outputs a low level, NAND1 outputs a high level, and after being converted by a level shifter, a high-level pulse Ioc is output. When the SiC MOSFET is normally turned on without an HSF fault, Vo returns to the normal level GND, and the voltage divider VC2 of C2 and C3... div When the voltage drops below the set second threshold voltage Vref2, com2 outputs a low level, indicating that the SiC MOSFET has been turned on normally. com3 is used to determine whether a FUL fault will occur. The third threshold voltage Vref3 is set relatively low, so it can take protective action more quickly when a FUL fault occurs.

[0075] See Figure 3 , Figure 3 The output waveform of the SiC MOSFET is shown when it is working normally under a double-pulse test. The SiC MOSFET used in this example has a rated continuous current of 32A. Therefore, this example is tested with a power supply voltage of 800V and a drain-source current of 32A as the standard.

[0076] See Figure 4 , Figure 4 This is the output waveform of a SiC MOSFET experiencing a short-circuit fault (HSF) when short-circuit protection is not implemented. In this example design, an HSF fault will occur at 22µs. It can be seen that without protection circuitry, the peak short-circuit current reaches as high as 188A, while the drain-source voltage remains at 477V. (See also...) Figure 5 , Figure 5 The output waveform of the SiC MOSFET when short-circuit protection is not enabled is FUL. The FUL fault occurs at 23us, at which time the peak short-circuit current is 189A and the drain-source voltage is maintained at around 481V.

[0077] See Figure 6 , Figure 6 The partial output waveform of HSF generated after applying the short-circuit protection circuit of this invention to a SiC MOSFET shows that the peak short-circuit current is suppressed to 107A and the short-circuit protection time is only 31ns; see also Figure 7 , Figure 7 The partial output waveform of FUL (Failure to Detect) was obtained after applying the short-circuit protection circuit of this invention to the SiC MOSFET. The results show that the peak short-circuit current was suppressed to 133A and the short-circuit protection time was only 40ns. Therefore, regardless of the type of short-circuit fault, the short-circuit protection circuit of this invention can quickly turn off the SiC MOSFET, ensuring its safe operation.

[0078] Furthermore, this example does not use capacitors with excessively large capacitance values, nor does it require any inductors. Therefore, the entire chip can be integrated using BCD technology, greatly improving its practicality.

[0079] In summary, this invention provides an on-chip integrated SiC MOSFET short-circuit protection circuit that can respond more quickly to short-circuit fault events, rapidly turn off the SiC MOSFET, effectively protect the SiC MOSFET, reduce power consumption during short circuits, and improve device reliability. It also features easy integration, making it more practical. Specifically, this invention can suppress the peak current to 107A when a hard-switching short-circuit fault (HSF) occurs in the SiC MOSFET, and suppress the peak current to 133A when a load short-circuit fault (FUL) occurs; the short-circuit protection times for HSF and FUL are 31ns and 40ns, respectively.

[0080] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0081] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0082] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A SiC MOSFET short-circuit protection circuit that can be integrated on-chip, characterized in that, include: The logic control unit is used to process the input signal Vin and the short-circuit fault signal. Its output is connected to the drive circuit. When a short-circuit fault occurs, it inputs a fault signal to the drive circuit. The first input terminal of the logic control unit is connected to the input signal Vin, the second input terminal is connected to the output terminal of the short-circuit protection circuit, and the third input terminal is connected to the output terminal of the reset circuit. A driving circuit for driving SiC MOSFETs; The input terminal of the driving circuit is connected to the output terminal of the logic control unit, and the output terminal is connected to the gate of the SiC MOSFET. A short-circuit protection circuit is used to send a short-circuit fault signal to the logic control unit when a short-circuit fault occurs; the first input terminal of the short-circuit protection circuit is connected to I... ds The output of the detection circuit is connected to the logic control unit; the short-circuit protection circuit has two comparators, which determine whether an HSF fault or a FUL fault has occurred by combining a preset threshold voltage. I ds A detection circuit is used to detect the drain-source current I of the SiC MOSFET. ds The value is then input to the short-circuit protection circuit along with the drain-source current I. ds A voltage that is directly proportional to the voltage; the I ds The input terminal of the detection circuit is connected to the source of the SiC MOSFET; A reset circuit is used to reset the short-circuit protection circuit that has completed the short-circuit protection action; the input terminal of the reset circuit is connected to the input signal Vin, and the output terminal is connected to the logic control unit.

2. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that, The logic control unit includes a first SR latch m1, a second inverter inv2, and a first AND gate and1; The R input terminal of the first SR latch m1 is connected to the output terminal of the reset circuit, and the S input terminal is connected to the output terminal of the short-circuit protection circuit; the input terminal of the second inverter inv2 is connected to the Q output terminal of the latch m1, and the output terminal is connected to one input terminal of the first AND gate and1; the other input terminal of the first AND gate and1 is connected to the input signal Vin, and the output terminal of the first AND gate and1 is connected to the output terminal of the logic control unit.

3. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that, The driving circuit includes a third inverter inv3, a first buffer buffer1, a second buffer buffer2, multiple parallel PLDMOS and multiple parallel NLDMOS; The input terminal of the third inverter inv3 is connected to the output terminal of the logic control unit, and the output terminal is connected to the input terminal of the first buffer buffer1 and the input terminal of the second buffer buffer2. The output terminal of the first buffer buffer1 is connected to the gate of a plurality of parallel PLDMOS. The output terminal of the second buffer buffer2 is connected to the gate of a plurality of parallel NLDMOS. The source of the parallel NLDMOS is connected to ground GND, and the drain is connected to the drain of the parallel PLDMOS. The source of the parallel PLDMOS is connected to the power supply VDDH. The drain of the NLDMOS and the drain of the PLDMOS are connected as the output terminal for driving short circuit and connected to the gate of the SiC MOSFET.

4. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that, The I ds The detection circuit includes a first diode D1, a first capacitor C1, a first resistor R1, a second diode D2, and a second resistor R2; The cathode of the first diode D1 is connected to ground (GND), and the anode is connected to one end of the first resistor R1; the other end of the first resistor R1 is connected to the cathode of the second diode D2; the anode of the diode D2 is connected to the source of the SiC MOSFET; the first capacitor C1 is connected in parallel with the first diode D1; and the second resistor R2 is connected in parallel with the second diode D2.

5. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that, The short-circuit protection circuit includes a first comparator COM1, a second comparator COM2, a third comparator COM3, a first OR gate OR1, a first NAND gate NAND1, and a level shifter. The non-inverting input of the first comparator com1 is connected to I. ds The output voltage Vo of the detection circuit is connected to the inverting input terminal of the first threshold voltage Vref1; the non-inverting input terminal of the second comparator com2 is connected to the voltage V. div The inverting input is connected to the second threshold voltage Vref2, where the voltage V... div The signal is sampled from a SiC MOSFET; the non-inverting input of the third comparator com1 is connected to I. ds The output voltage Vo of the detection circuit is connected to the third threshold voltage Vref3 at its inverting input terminal. The two inputs of the first OR gate OR1 are connected to the outputs of the second comparator COM2 and the third comparator COM3, respectively, and the output is connected to one input of the first NAND gate NAND1; the other input of the first NAND gate NAND1 is connected to the output of the first comparator COM1, and the output is connected to the input of the level shifter; the output of the level shifter is connected to the S input of the latch M1.

6. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 5, characterized in that, The voltage V div The voltage V is obtained through a sampling circuit, which includes a second capacitor C2 and a third capacitor C3. The second capacitor C2 and the third capacitor C3 are connected in series between the drain and source of the SiC MOSFET. The voltage V is obtained at the connection point of the second capacitor C2 and the third capacitor C3. div .

7. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that, The reset circuit includes a first inverter inv1 and a first NOR gate nor1; The input terminal of the first inverter inv1 is connected to the input signal Vin, and the output terminal is connected to one input terminal of the first NOR gate nor1; the other input terminal of the first NOR gate nor1 is connected to the input signal Vin, and the output terminal is connected to the R input terminal of the latch m1.

8. The on-chip integrated SiC MOSFET short-circuit protection circuit according to claim 1, characterized in that, The SiC MOSFET short-circuit protection circuit also includes a digital isolator; The digital isolator is used to transmit and convert the digital signal at the input end, and its output end outputs the input signal Vin.

9. A SiC MOSFET short-circuit protection circuit that can be integrated on-chip according to any one of claims 1-8, characterized in that, The SiC MOSFET short-circuit protection circuit is integrated using BCD technology.

10. A chip, characterized in that, Includes an on-chip integrated SiCMOSFET short-circuit protection circuit as described in any one of claims 1-9.

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