Oscillator with wide oscillation amplitude range

Abstract

The invention relates to an oscillator with a wide oscillation amplitude range. The oscillator with the wide oscillation amplitude range comprises an integrating circuit 110, a level conversion circuit 120 and an output driving circuit 130, wherein the integrating circuit 110 charges and discharges a capacitor C1 through a mirror image bias current IREF to generate a ramp voltage, and the power supply voltage VDD1 of the integrating circuit 110 can be reduced to 3.3 V to the minimum, so that the power consumption is reduced; the output voltage is converted by the level conversion circuit 120 and finally generates a clock frequency CLK by the output driving circuit 130, the output voltage range is related to VDD2, the maximum value can be 10V, the minimum value can be consistent with VDD1, and wide-range output can be realized; the clock frequency controls the on and off of an MOS tube in the integrating circuit so as to realize the charge and discharge loop control of the integrating capacitor. The oscillator is low in power consumption, wide in power supply voltage range and simple in structure, and can drive a large load and provide high-voltage output.

Description

Technical Field

[0001] The invention relates to the technical field of analog circuits, and in particular to an oscillator with a wide oscillation amplitude range. Background Art

[0002] Generally speaking, a relaxation oscillator usually generates a clock frequency CLK by integrating the circuit current charge and discharge. The integral capacitor C1 is used to integrate the bias current, generate a ramp voltage, and generate a clock frequency through the floating switch logic. In order to overcome the problem that the traditional medium and low precision RC relaxation oscillator requires a comparator and an op amp, which increases the chip area and has high power consumption, while taking into account the output of a high-voltage clock signal; a relaxation oscillator with a wide oscillation amplitude range, simple structure, and small area is designed. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides an oscillator with a wide oscillation amplitude range, which directly converts low-voltage frequency into high-voltage frequency and can drive light load or heavy load according to demand, including:

[0004] The integration circuit 110 includes current mirror PMOS transistors PM1, PM2 and NMOS transistors NM1, NM2, NM3, an integration capacitor C1, switch PMOS transistors PM3, PM4, PM5, PM6 and NMOS transistors NM4, NM5, NM6, NM7, an enable switch transistor NM8, shaping and driving inverters INV1, INV2, and a bias current source I REF ; Among them, NM1, NM2, NM3 and PM1, PM2 are proportional mirror bias currents, and by setting the bias current source I REF , adjust the size of the mirror current ratio of NM3 and PM2, speed up and down the ramp voltage, and then set the duty cycle of the frequency; by controlling the NMOS tubes NM4 and PM3 to turn on and off alternately, the integral capacitor is charged and discharged to generate a ramp voltage; the floating switch tubes PM5, PM6 and NM6, NM7 shape the generated frequency, and output a square wave through INV1 secondary shaping; NM8 is used as an enable switch to realize the control of circuit opening and closing;

[0005] The switch is turned on and off, and the proportional mirror bias current I REF , charging and discharging the integral capacitor C1, the capacitor charging and discharging generates a ramp voltage V B , control the suspended current mirror, and perform the initial shaping of the ramp voltage to obtain the voltage V C , after secondary shaping by inverter INV1, V A , clock frequency V AFeedback to the integration circuit 110 controls the gate voltage of the switching transistors PM3 and NM4, charges and discharges the capacitor C1 to generate a ramp voltage, and forms a complete loop; the voltage is shaped and the output waveform is as follows Figure 3 shown.

[0006] The level conversion circuit 120 converts the low-voltage frequency generated by the integration circuit, outputs a high-voltage signal, and transmits it to the subsequent drive circuit; it includes the level conversion circuit itself and a logic gate circuit; wherein the level conversion circuit 120 is connected to the output port of the inverter INV2, and the output port of the level conversion circuit 120 is connected to the output drive circuit 130, and the internal circuit is selected according to actual needs. The power supply voltage of the level conversion circuit is VDD2, and the logic gate circuit can be connected to the input port or output port of the level converter in the level conversion circuit itself according to circuit requirements or device characteristics;

[0007] The level conversion circuit needs to specifically suppress the switch leakage when the voltage is in the middle rail, so the logic circuit in the level conversion circuit is highly optional, including logic such as inverters, buffers, Schmitt triggers and comparators. There is no clear requirement for the type of level converter, which can only realize the conversion function or have other functions such as enable and clear; the logic gate circuit, whose structure is optional, such as inverters, buffers and comparators, realizes the functions of enable, latch, clear, and glitch suppression;

[0008] An output drive circuit 130, wherein the output drive circuit 130 is controlled by a clock signal and outputs a clock frequency CLK; at the same time, the voltage of the output drive circuit is VDD2, and an internal power supply or an external power supply is used to generate frequencies with different voltage amplitudes;

[0009] At the same time, the output drive circuit 130 has an optional structure, such as an inverter, a buffer, and a push-pull output circuit.

[0010] In one embodiment of the present invention, the sources of the PMOS transistors PM1, PM2, and PM4 are connected to the power supply voltage VDD1, the sources of the NMOS transistors NM1, NM2, NM3, and NM5 are connected to the ground potential GND, and the upper plate of the integrating capacitor C1 is connected to the power supply voltage.

[0011] In one embodiment of the present invention, the bias current source I REF The current input end is connected to the drain of NM1, the gate and drain of NM1 are connected to the gates of NM2 and NM3, the drain of NM2 is connected to the drain and gate of PM1, the gate of PM1 is connected to the gate of PM2, the drain of PM2 is connected to the source of PM3, the gate of PM3 is connected to the gate of NM4, the drain of NM4 is connected to the drain of PM3 and the lower plate of the integrating capacitor C1, the drain of NM8 is also connected to the lower plate of the integrating capacitor C1, and the source of NM8 is connected to GND.

[0012] In one embodiment of the present invention, the gates of PM4, PM5 and NM5, NM6 are connected to the lower plate of the integrating capacitor C1, the drain of PM4 is connected to the source of PM5, PM6, the drains of PM5, PM6 are connected to the drains of NM6, NM7, the drain of NM5 is connected to the source of NM6, NM7, the input of the inverter INV1 is connected to the drains of PM5, PM6 and the drains of NM6, NM7, and the output of the inverter INV1 is connected to the gates of PM3, PM6, NM4, NM7 and the input port of INV2.

[0013] The above technical solution of the present invention has the following advantages over the prior art: the oscillator with a wide oscillation amplitude range of the present invention has a simple and stable circuit structure, effectively reduces the use of high-voltage MOS tubes and capacitors, reduces the chip area, and has various optional capacitor types, level conversion structures and drive types to achieve special functions such as enabling and clearing; it can work with very small current and can effectively reduce static power consumption; the output frequency amplitude has a wide range, from a minimum of 0V to a maximum of 10V according to the required structure and voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0015] Figure 1 It is a circuit principle diagram of an oscillator with a wide oscillation amplitude range in the present invention.

[0016] Figure 2 It is a structural schematic diagram of the oscillator provided by the present invention.

[0017] Figure 3 It is a voltage waveform diagram of the oscillator provided by the present invention.

[0018] Figure 4 This is a diagram of an embodiment of the oscillator provided by the present invention.

[0019] Figure 5 This is a second diagram of an embodiment of the oscillator provided by the present invention. DETAILED DESCRIPTION

[0020] Embodiment 1

[0021] This embodiment provides an oscillator with a wide oscillation amplitude range, and its structure is as follows Figure 4 The oscillator includes an integration circuit 110 , a level conversion circuit 120 and an output drive circuit 130 .

[0022] Reference Figure 4 , the integrator circuit 110, according to the proportional mirror bias current I REF , charge and discharge the integral capacitor C1 to generate a ramp voltage VB The ramp voltage is shaped by the floating switch circuit to drive the level conversion circuit 120 to generate a high-voltage clock frequency. The high-voltage clock frequency is shaped by the internal logic gate of the output drive circuit 130 to control the gate voltage of the drive tubes M1 and M2 to generate a clock frequency CLK with driving capability.

[0023] Reference Figure 4 The connection mode of the integration circuit 110 is that the sources of the PMOS tubes PM1, PM2, and PM4 are connected to the power supply voltage VDD1, the sources of the NMOS tubes NM1, NM2, NM3, and NM5 are connected to the ground potential GND, the source of NM8 is connected to GND, the upper plate of the integration capacitor C1 is connected to the power supply voltage, and the lower plate is connected to the drain of NM4, the drain of PM3, the drain of NM8, the gates of PM4 and PM5, and the gates of NM5 and NM6; the bias current source I REF The current input end is connected to the drain of NM1, the gate and drain of NM1 are connected to the gates of NM2 and NM3, the drain of NM2 is connected to the drain and gate of PM1, the gate of PM1 is connected to the gate of PM2, the drain of PM2 is connected to the source of PM3, and the gate of PM3 is connected to the gate of the switch tube NM4; the drain of PM4 is connected to the source of PM5 and PM6, the drains of PM5 and PM6 are connected to the drains of NM6 and NM7, the drain of NM5 is connected to the source of NM6 and NM7, the input end of the inverter INV1 is connected to the drains of PM5 and PM6 and the drains of NM6 and NM7, and the output end of the inverter INV1 is connected to the gates of PM3, PM6, NM4, NM7 and the input port of INV2.

[0024] Reference Figure 4 The level conversion circuit 120 is connected in such a way that the sources of the PMOS tubes PM7 and PM8 are connected to the power supply voltage VDD2, the sources of the NMOS tubes NM9 and NM10 are connected to the ground GND, the gate of NM9 is connected to the output end of the inverter INV2, the gate of NM10 is connected to the output end of INV1, the drain of NM9 is connected to the gate of PM8 and the drain of PM7, the drain of NM10 is connected to the gate of PM7 and the drain of PM8, and the drain of NM10 is the output end of the level conversion circuit.

[0025] Reference Figure 4 The output drive circuit 130 is connected in such a way that the inverter INV3 is connected to the drain of the output port NM10 of the level conversion circuit, the output port of the inverter INV3 is connected to the input ends of the inverters INV4 and INV5, the output end of the inverter INV4 is connected to the gate of the power PMOS tube M1, the output end of the inverter INV5 is connected to the gate of the power NMOS tube M2, the drain of M1 is connected to the drain of M2, and the high-voltage clock frequency CLK is output.

[0026] Embodiment 2

[0027] This embodiment provides an oscillator with a wide oscillation amplitude range, and its structure is as follows Figure 5The oscillator comprises an integration circuit II 210 , a level conversion circuit II 220 and an output drive circuit II 230 .

[0028] Integrator circuit II210, according to the proportional mirror bias current I REF , charge and discharge the integral capacitor C1 to generate a ramp voltage V B The ramp voltage is shaped by the floating switch circuit to drive the level conversion circuit 120 to generate a high-voltage clock frequency. The high-voltage clock frequency is shaped by the output drive circuit II 230 to generate a clock frequency CLK with driving capability. The high level of the clock frequency is VDD2, and the low level is VDD1.

[0029] Reference Figure 5 The connection mode of the integration circuit II210 is that the sources of the PMOS tubes PM1, PM2, and PM4 are connected to the power supply voltage VDD1, the sources of the NMOS tubes NM1, NM2, NM3, and NM5 are connected to the ground potential GND, the source of NM8 is connected to GND, the upper plate of the integration capacitor C1 is connected to the power supply voltage, and the lower plate is connected to the drain of NM4, the drain of PM3, the drain of NM8, the gates of PM4 and PM5, and the gates of NM5 and NM6; the bias current source I REF The current input end is connected to the drain of NM1, the gate and drain of NM1 are connected to the gates of NM2 and NM3, the drain of NM2 is connected to the drain and gate of PM1, the gate of PM1 is connected to the gate of PM2, the drain of PM2 is connected to the source of PM3, and the gate of PM3 is connected to the gate of the switch tube NM4; the drain of PM4 is connected to the source of PM5 and PM6, the drains of PM5 and PM6 are connected to the drains of NM6 and NM7, the drain of NM5 is connected to the source of NM6 and NM7, the input end of the inverter INV1 is connected to the drains of PM5 and PM6 and the drains of NM6 and NM7, and the output end of the inverter INV1 is connected to the gates of PM3, PM6, NM4, NM7 and the input port of INV2.

[0030] Reference Figure 5The connection mode of the level conversion circuit II220 is that the source of the PMOS tubes PM7, PM8, PM9, PM10, PM11, and PM12 are connected to the power supply voltage VDD2, the source of the NMOS tubes NM9 and NM10 are grounded GND, and the source of the NMOS tubes NM11 and NM12 are connected to the power supply voltage VDD1; the gates of the MOS tubes PM7, PM8, and PM10 are connected to the drains of PM8 and PM9, and the drain of NM13 are connected together, the gates of the MOS tubes PM9, PM11, and PM12 are connected to the drains of PM10 and PM11, and the drain of NM14 are connected together; the gate of NM13 is connected to the drains of PM8 and PM9, and the drain of NM13 is connected together; the gate of NM13 is connected to the drains of PM8 and PM9, and the drain of PM14 ... The output terminal of inverter INV1 of integration circuit II 210 is connected, the gate of NM14 is connected to the output terminal of inverter INV2 of integration circuit II 210, the sources of NM13 and NM14 and the drain of NM10 are connected together, the gate of NM10 and the drain of NM9 are connected to the gate of NM1 of integration circuit II 210, the drain of NM10 is connected to the N terminal of Zener diode Z1, and the source of NM10 is connected to the P terminal of Zener diode Z1; the drain of NM11, the gate of NM12 and the drain of PM7 are connected together, the gate of NM11, the drain of NM12 and the drain of PM12 are connected in series, and this point is the output of the level conversion circuit.

[0031] Reference Figure 5 The connection mode of the output drive circuit II230 is that the gate of the PMOS drive tube M1 and the gate of the MOS drive tube M2 are connected to the gate of NM11, the drain of NM12, and the drain of PM12, the source of M1 is connected to the power supply voltage VDD2, the source of M2 is connected to the power supply voltage VDD1, and the drain of M1 is connected to the drain of M2. The output frequency CLK is at this point.

[0032] To sum up, the relaxation oscillator described in the two groups of embodiments has the advantages of simple structure, small chip area, low static current to achieve low power consumption, and can directly convert low-voltage frequency into high-voltage frequency. It has a wide operating voltage range and can drive light load or heavy load according to demand. When the bias of this structure is stably working, the clock frequency is generated.

[0033] Reference Figure 2 , a structural diagram of an oscillator with a wide oscillation amplitude range is provided, including an integration circuit 110, a level conversion circuit 120 and an output drive circuit 130. The structural diagram shows the working process of the oscillator, wherein when the bias current I REF The integrator integrates the current to charge the capacitor and then outputs a low-voltage clock frequency V A When the clock frequency V A The power is fed to the gates of PM3 and NM4 inside the integration circuit 110, so that the MOS tubes are switched on and off alternately, thereby realizing the charging and discharging of the integration capacitor and completing the periodic switching.

[0034] Reference Figure 1 ,for Figure 2The circuit schematic diagram shown includes an integration circuit 110 (PMOS transistors PM1, PM2, PM3, PM4, PM5, PM6, NMOS transistors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, an integration capacitor C1, inverters INV1, INV2), a level conversion circuit 120 and an output drive circuit 130. Figure 1 As shown, the bias current I REF After n times proportional adjustment, the integral capacitor is charged and discharged after mirroring, and the generated clock frequency is:

[0035]

[0036] In the above formula, the clock frequency is affected by the power supply voltage VDD1, the bias current I REF And the circuit delay time T delay The macroscopic influence of the optional zero temperature drift bias current I REF Reduce temperature influence. Delay time T delay It is greatly affected by temperature, but in circuits with medium and low precision requirements, this temperature effect on the clock frequency is acceptable.

[0037] In the present invention, words such as "connect", "connected", "connected", "connected", etc., which indicate electrical connection, indicate direct or indirect electrical connection unless otherwise specified. Figure 1 The direction is named for ease of expression.

[0038] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. An oscillator with a wide oscillation amplitude range, which directly converts low-voltage frequency into high-voltage frequency, and can drive light load or heavy load according to demand, characterized in that: include: The integration circuit (110) comprises current mirror PMOS transistors PM1, PM2 and NMOS transistors NM1, NM2, NM3, an integration capacitor C1, switch PMOS transistors PM3, PM4, PM5, PM6 and NMOS transistors NM4, NM5, NM6, NM7, an enabling switch transistor NM8, shaping and driving inverters INV1, INV2, and a bias current source I REF ; Among them, NM1, NM2, NM3 and PM1, PM2 are proportional mirror bias currents, and by setting the bias current source I REF , adjust the size of the mirror current ratio of NM3 and PM2, speed up and down the ramp voltage, and then set the duty cycle of the frequency; by controlling the NMOS tubes NM4 and PM3 to turn on and off alternately, the integral capacitor is charged and discharged to generate a ramp voltage; the floating switch tubes PM5, PM6 and NM6, NM7 shape the generated frequency, and output a square wave through INV1 secondary shaping; NM8 is used as an enable switch to realize the control of circuit opening and closing; A level conversion circuit (120), comprising the level conversion circuit itself and a logic gate circuit; The level conversion circuit (120) is connected to the output port of the inverter INV2, the output port of the level conversion circuit (120) is connected to the output drive circuit (130), the power supply voltage of the level conversion circuit is VDD2, and the logic gate circuit is connected to the input port or output port of the level converter in the level conversion circuit itself; An output drive circuit (130) is controlled by a clock signal and outputs a clock frequency CLK; at the same time, the voltage of the output drive circuit is VDD2, and internal power supply or external power supply is used to generate frequencies with different voltage amplitudes.

2. The oscillator with a wide oscillation amplitude range according to claim 1, characterized in that: The sources of the PMOS tubes PM1, PM2 and PM4 are connected to the power supply voltage VDD1, the sources of the NMOS tubes NM1, NM2, NM3 and NM5 are connected to the ground potential GND, and the upper plate of the integrating capacitor C1 is connected to the power supply voltage.

3. The oscillator with a wide oscillation amplitude range according to claim 1, characterized in that: Bias current source I REF The current input end is connected to the drain of NM1, the gate and drain of NM1 are connected to the gates of NM2 and NM3, the drain of NM2 is connected to the drain and gate of PM1, the gate of PM1 is connected to the gate of PM2, the drain of PM2 is connected to the source of PM3, the gate of PM3 is connected to the gate of NM4, the drain of NM4 is connected to the drain of PM3 and the lower plate of the integrating capacitor C1, the drain of NM8 is also connected to the lower plate of the integrating capacitor C1, and the source of NM8 is connected to GND.

4. The oscillator with a wide oscillation amplitude range according to claim 1, characterized in that: The gates of PM4, PM5 and NM5, NM6 are connected to the lower plate of the integrating capacitor C1, the drain of PM4 is connected to the source of PM5, PM6, the drains of PM5, PM6 are connected to the drains of NM6, NM7, the drain of NM5 is connected to the source of NM6, NM7, the input of the inverter INV1 is connected to the drains of PM5, PM6 and the drains of NM6, NM7, and the output of the inverter INV1 is connected to the gates of PM3, PM6, NM4, NM7 and the input port of INV2.

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