A method for realizing the integration of frequency raising and lowering of incremental encoder

Abstract

A method for realizing the integrated frequency increase and decrease of an incremental encoder, comprising: an adjustment circuit filters and shapes the output signal of the incremental encoder, and processes the adjusted signal through an FPGA module. The host computer data receiving module in the FPGA module receives the frequency conversion parameters, output standard position and number parameters bound by the host computer; the frequency conversion coefficient generation module classifies the frequency conversion parameters bound by the host computer, and generates corresponding enable signals and parameters; the A / B edge acquisition module collects the adjustment A signal and the adjustment B signal, and generates corresponding input cycle information and forward and reverse information; the frequency conversion submodule generates and outputs the frequency conversion cycle corresponding to the adjustment A signal and the adjustment B signal respectively; the Z signal output module processes and outputs the adjustment Z signal according to the output standard position and number parameters bound by the host computer. The present application adjusts the output signal multiplication coefficient of the incremental encoder through the frequency conversion submodule to meet the requirements of increasingly rich application scenarios.

Description

Technical Field

[0001] The present invention belongs to the technical field of incremental encoders, and in particular relates to a method for realizing the integration of frequency raising and lowering of incremental encoders. Background Art

[0002] Incremental encoders are one of the most commonly used sensors in CNC systems. In order to obtain accurate data information, CNC systems need to be equipped with high-precision incremental encoders. Therefore, improving the resolution of incremental encoders plays a key role in the development of precision measurement and control technology.

[0003] The incremental encoder is used to output the motor position increment, and its output generally has three: A, B, and Z. Among them, A and B are two square wave signals with a phase difference of 90 degrees, which are used to mark the rotation distance of the motor. The Z signal is a zero position signal, which is used to mark a standard position information. Therefore, increasing the number of output pulses in a single cycle means reducing the moving step of the motor and improving the resolution of the encoder.

[0004] In the prior art, the output frequency multiplication method of the incremental encoder is generally a fixed 4-fold frequency multiplication coefficient. The 4-fold frequency multiplication is achieved by collecting the 90-degree phase difference edge jumps of the two paths A and B, converting one cycle of the sine and cosine signals into 4 pulses. Every time a pulse is generated, the pulse count value is increased by 1, thereby completing the four-fold frequency subdivision and phase detection of the sine and cosine signals. The four-fold frequency subdivision method increases the number of counted pulses by 4 times, that is, the encoder resolution is increased by 4 times.

[0005] In the prior art, the output frequency multiplication method of the incremental encoder adopts a fixed frequency multiplication coefficient, which has a narrow design application range and is not conducive to the requirements of increasingly diverse application scenarios. Summary of the invention

[0006] The present application provides a method for realizing integrated frequency increase and decrease of an incremental encoder. In the frequency conversion implementation module, a plurality of frequency conversion sub-modules corresponding to the classification of frequency conversion parameters in the frequency conversion coefficient generation module are set. The output signal multiplication coefficient of the incremental encoder is adjusted through the frequency conversion sub-module to adapt to the requirements of increasingly rich application scenarios.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] In order to achieve one, part or all of the above purposes or other purposes, the present invention provides a method for realizing the integration of frequency increase and decrease of an incremental encoder.

[0009] A method for realizing integrated frequency raising and lowering of an incremental encoder, comprising:

[0010] The adjustment circuit filters and shapes the A signal, B signal and Z signal output by the incremental encoder, and outputs the adjustment A signal, the adjustment B signal and the adjustment Z signal to the FPGA module;

[0011] The FPGA module processes the received signal, and the FPGA module includes a host computer data receiving module, a frequency conversion coefficient generating module, an A / B edge acquisition module and a frequency conversion realization module;

[0012] The input end of the host computer data receiving module is controlled by the host computer, receives the frequency conversion parameters, output standard position and number parameters bound by the host computer, and the output end is connected to the frequency conversion coefficient generation module and the A / B edge acquisition module;

[0013] The frequency conversion coefficient generation module classifies the frequency conversion parameters bound by the host computer, generates corresponding enable signals and parameters, and outputs them to the frequency conversion implementation module;

[0014] The A / B edge acquisition module acquires the adjustment A signal and the adjustment B signal, generates corresponding input cycle information and forward and reverse rotation information and outputs them to the frequency conversion implementation module;

[0015] The frequency conversion implementation module includes a frequency conversion module and a Z signal output module;

[0016] The frequency conversion module includes a plurality of frequency conversion submodules corresponding to the classification of the frequency conversion parameters in the frequency conversion coefficient generation module, and the frequency conversion submodules process and output the adjustment A signal and the adjustment B signal respectively according to the corresponding frequency conversion period;

[0017] The Z signal output module processes and outputs the adjusted Z signal according to the output standard position and number parameters of the upper computer binding.

[0018] The frequency conversion coefficient generation module classifies the frequency conversion parameters bound by the host computer based on whether the multiplication frequency is a decimal, odd number, even number and the frequency reduction coefficient, generates corresponding enable signals and parameters, and outputs them to the frequency conversion submodule corresponding to the frequency conversion implementation module.

[0019] The frequency conversion submodule corresponds to the classification of the frequency conversion parameters in the frequency conversion coefficient generation module, and the frequency conversion submodule includes a fractional frequency conversion submodule, an odd frequency conversion submodule, an even frequency conversion submodule and a frequency reduction coefficient frequency conversion submodule.

[0020] The frequency conversion parameters bound by the host computer represent the period multiple relationship between the output A / B signal and the input A / B signal. The output standard position and number parameters determine the number of output Z signals in one cycle and the alignment relationship between the Z signal and the output A / B signal edge.

[0021] The A signal and the B signal are two square wave signals with a phase difference of 90 degrees, and the Z signal is a zero position signal.

[0022] The adjustment circuit includes a filter circuit and a shaping circuit;

[0023] The filtering circuit selects the frequency of the output signal through a multi-order RC filter, filters out the signal outside the frequency spectrum range of the target signal, and outputs the target signal;

[0024] The shaping circuit shapes the target signal, and the shaping circuit includes three transistors connected in series with a common base, wherein the collectors of the transistors are all connected to the input resistor of the shaping circuit, and the emitters are all connected to the output resistor of the shaping circuit.

[0025] The incremental encoder outputs an A signal, a B signal and a Z signal to a multi-order RC filter in the adjustment circuit;

[0026] The multi-order RC filter filters out the signal outside the frequency spectrum range of the target signal in the output signal, and outputs the target signal;

[0027] The first transistor of the shaping circuit performs primary shaping on the target signal and outputs a primary shaped signal, the primary shaped signal enters the second transistor for secondary shaping, the second transistor outputs the secondary shaped signal to the third transistor, the third transistor performs tertiary shaping on the secondary shaped signal and outputs an adjustment signal.

[0028] The input resistor, the output resistor and the transistor connected to the transistor form a current loop to adjust the duty cycle of the shaped signal.

[0029] The A / B edge acquisition module detects the input of the adjustment Z signal, and outputs the adjustment Z signal to the Z signal output module of the frequency conversion implementation module.

[0030] A Flash chip is provided to store relevant information of the FPGA module.

[0031] Compared with the prior art, the beneficial effects of the present invention mainly include:

[0032] The present application provides a method for realizing integrated frequency increase and decrease of an incremental encoder. In the frequency conversion implementation module, a plurality of frequency conversion sub-modules corresponding to the classification of frequency conversion parameters in the frequency conversion coefficient generation module are set. The output signal multiplication coefficient of the incremental encoder is adjusted through the frequency conversion sub-module to adapt to the requirements of increasingly rich application scenarios.

[0033] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of the module structure provided for an embodiment of the present application.

[0036] Figure 2 A schematic diagram of a filter circuit provided in an embodiment of the present application.

[0037] Figure 3 A schematic diagram of a shaping circuit provided in an embodiment of the present application.

[0038] Figure 4 A schematic diagram of the FPGA module structure provided in an embodiment of the present application.

[0039] Figure 5 Schematic diagram of various outputs of the frequency conversion implementation module provided in the embodiment of the present application. DETAILED DESCRIPTION

[0040] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0041] The present application provides a method for realizing integrated frequency increase and decrease of an incremental encoder. In the frequency conversion implementation module, a plurality of frequency conversion sub-modules corresponding to the classification of frequency conversion parameters in the frequency conversion coefficient generation module are set. The output signal multiplication coefficient of the incremental encoder is adjusted through the frequency conversion sub-module to adapt to the requirements of increasingly rich application scenarios.

[0042] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0043] like Figure 1As shown, the adjustment circuit filters and shapes the A signal, B signal and Z signal output by the incremental encoder, and outputs the adjusted A signal, the adjusted B signal and the adjusted Z signal to the FPGA module; the FPGA module is controlled by the host computer, receives and processes the adjusted signals; and the Flash chip stores the relevant information of the FPGA module.

[0044] The output signals of the incremental encoder include A signal, B signal and Z signal. A signal and B signal are square wave signals with a phase difference of 90 degrees, and Z signal is a zero position signal.

[0045] Figure 2 Shown is a schematic diagram of a filtering circuit provided in an embodiment of the present application.

[0046] like Figure 2 As shown, the filter circuit selects the frequency of the output signal through a multi-order RC filter, filters out the signal outside the frequency spectrum range of the target signal, and outputs the target signal.

[0047] Specifically, the incremental encoder outputs A signal, B signal and Z signal to the multi-order RC filter in the adjustment circuit; the multi-order RC filter filters out the signal outside the frequency spectrum range of the target signal in the output signal, and outputs the target signal.

[0048] Figure 3 Shown is a schematic diagram of a shaping circuit provided in an embodiment of the present application.

[0049] The shaping circuit shapes the filtered target signal. The output signal of the incremental encoder may be distorted due to external reasons. The shaping circuit restores the distorted signal to a smooth signal by shaping it.

[0050] like Figure 3 As shown, the shaping circuit includes three transistors connected in series with a common base, the collectors of the transistors are all connected to the input resistor, and the emitters are all connected to the output resistor.

[0051] In the circuit, the transistor and the resistor can be directly connected. The transistor usually controls the collector current through the base-emitter current, and the resistor is used to limit the current and stabilize the circuit.

[0052] Specifically, the first transistor of the shaping circuit performs primary shaping on the target signal and outputs a primary shaped signal, the primary shaped signal enters the second transistor for secondary shaping, the second transistor outputs the secondary shaped signal to the third transistor, the third transistor performs tertiary shaping on the secondary shaped signal and outputs an adjustment signal.

[0053] Among them, the input resistor, output resistor and transistor connected to the transistor form a current loop to adjust the duty cycle of the shaped signal.

[0054] Figure 4 Shown is a schematic diagram of the FPGA module structure provided in an embodiment of the present application.

[0055] like Figure 4 As shown, the FPGA module processes the received signal, and the FPGA module includes a host computer data receiving module, a frequency conversion coefficient generating module, an A / B edge acquisition module, and a frequency conversion realization module;

[0056] The input end of the host computer data receiving module is controlled by the host computer, receives the frequency conversion parameters, output standard position and number parameters bound by the host computer, and the output end is connected to the frequency conversion coefficient generation module and the A / B edge acquisition module;

[0057] The frequency conversion parameter indicates the period multiple relationship between the output A / B signal and the input A / B signal, and the output standard position and number parameters determine the number of output Z signals in one period and the alignment relationship between the Z signal and the output A / B signal edge.

[0058] The frequency conversion coefficient generation module classifies the frequency conversion parameters based on whether the frequency multiplication is a decimal, an odd number, an even number, and a frequency reduction coefficient, generates corresponding enable signals and parameters, and outputs them to the frequency conversion submodule corresponding to the frequency conversion implementation module;

[0059] The A / B edge acquisition module acquires the adjustment A signal and the adjustment B signal, generates corresponding input cycle information and forward and reverse information, outputs them to the frequency conversion realization module, and detects the input of the adjustment Z signal;

[0060] The frequency conversion implementation module is the core module of this application, including a frequency conversion module and a Z signal output module;

[0061] The frequency conversion module includes a plurality of frequency conversion submodules corresponding to the classification of the frequency conversion parameters in the frequency conversion coefficient generation module, and the frequency conversion submodules include a fractional frequency conversion submodule, an odd frequency conversion submodule, an even frequency conversion submodule and a frequency reduction coefficient frequency conversion submodule; the frequency conversion submodule processes and outputs the adjustment A signal and the adjustment B signal according to the corresponding frequency conversion period;

[0062] The Z signal output module processes and outputs the adjusted Z signal according to the output standard position and number parameters of the upper computer binding.

[0063] Specifically, the fractional frequency conversion submodule is responsible for processing the case where the frequency conversion coefficient is non-integer. After counting the original frequency parameters, the non-integer frequency conversion coefficient is converted into an even number using a high-speed clock for processing, and then an output clock with a duty cycle close to 50% is generated;

[0064] Odd frequency conversion submodule: The odd frequency conversion submodule is responsible for processing the case where the frequency conversion coefficient is an odd number. After counting the original frequency parameters, the odd coefficient is converted into an even number for processing, and then an output clock with a 50% duty cycle is generated;

[0065] Even frequency conversion submodule: The even frequency conversion submodule is responsible for processing the case where the frequency increase coefficient is an even number. After obtaining the original frequency parameters through statistics, the output clock with a duty cycle of 50% is directly obtained according to the multiple relationship.

[0066] Down-frequency coefficient frequency conversion submodule: The down-frequency coefficient frequency conversion submodule is responsible for handling down-frequency situations. Since the time length of the output clock is greater than the input clock, a down-frequency clock of a corresponding multiple can be output according to the input clock cycle.

[0067] like Figure 5 As shown, the period multiple relationship between the output A / B signal and the input A / B signal can be adjusted to 2 times output or 4 times output.

[0068] As a preferred embodiment of the present invention, the FPGA module processing in this embodiment is performed based on a 50 MHz clock, ensuring sufficiently high accuracy.

[0069] The present application provides a method for realizing integrated frequency increase and decrease of an incremental encoder. In the frequency conversion implementation module, a plurality of frequency conversion sub-modules corresponding to the classification of frequency conversion parameters in the frequency conversion coefficient generation module are set. The output signal multiplication coefficient of the incremental encoder is adjusted through the frequency conversion sub-module to adapt to the requirements of increasingly rich application scenarios.

[0070] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0071] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A method for realizing the integration of frequency raising and lowering of incremental encoder, characterized in that: include: The adjustment circuit filters and shapes the A signal, B signal and Z signal output by the incremental encoder, and outputs the adjustment A signal, the adjustment B signal and the adjustment Z signal to the FPGA module; The FPGA module processes the received signal, and the FPGA module includes a host computer data receiving module, a frequency conversion coefficient generating module, an A / B edge acquisition module and a frequency conversion realization module; The input end of the host computer data receiving module is controlled by the host computer, receives the frequency conversion parameters, output standard position and number parameters bound by the host computer, and the output end is connected to the frequency conversion coefficient generation module and the A / B edge acquisition module; The frequency conversion coefficient generation module classifies the frequency conversion parameters bound by the host computer, generates corresponding enable signals and parameters, and outputs them to the frequency conversion implementation module; The A / B edge acquisition module acquires the adjustment A signal and the adjustment B signal, generates corresponding input cycle information and forward and reverse rotation information, and outputs them to the frequency conversion implementation module; The frequency conversion implementation module includes a frequency conversion module and a Z signal output module; The frequency conversion module includes a plurality of frequency conversion submodules corresponding to the classification of the frequency conversion parameters in the frequency conversion coefficient generation module, and the frequency conversion submodules process and output the adjustment A signal and the adjustment B signal respectively according to the corresponding frequency conversion period; The Z signal output module processes and outputs the adjusted Z signal according to the output standard position and number parameters of the upper computer binding.

2. A method for realizing the integration of frequency raising and lowering of incremental encoder according to claim 1, characterized in that: The frequency conversion coefficient generation module classifies the frequency conversion parameters bound by the host computer based on whether the multiplication is a decimal, odd, even number and the frequency reduction coefficient, generates corresponding enable signals and parameters, and outputs them to the frequency conversion submodule corresponding to the frequency conversion implementation module.

3. A method for realizing integrated frequency raising and lowering of an incremental encoder according to claim 2, characterized in that: The frequency conversion submodule corresponds to the classification of the frequency conversion parameters in the frequency conversion coefficient generation module, and the frequency conversion submodule includes a fractional frequency conversion submodule, an odd frequency conversion submodule, an even frequency conversion submodule and a frequency reduction coefficient frequency conversion submodule.

4. A method for realizing integrated frequency raising and lowering of an incremental encoder according to claim 1, characterized in that: The frequency conversion parameters bound by the host computer represent the period multiple relationship between the output A / B signal and the input A / B signal. The output standard position and number parameters determine the number of output Z signals in one cycle and the alignment relationship between the Z signal and the output A / B signal edge.

5. A method for realizing integrated frequency raising and lowering of an incremental encoder according to claim 1, characterized in that: The A signal and the B signal are two square wave signals with a phase difference of 90 degrees, and the Z signal is a zero position signal.

6. A method for realizing integrated frequency raising and lowering of an incremental encoder according to claim 1, characterized in that: The adjustment circuit includes a filter circuit and a shaping circuit; The filtering circuit selects the frequency of the output signal through a multi-order RC filter, filters out the signal outside the frequency spectrum range of the target signal, and outputs the target signal; The shaping circuit shapes the target signal, and the shaping circuit includes three transistors connected in series with a common base, wherein the collectors of the transistors are all connected to the input resistor of the shaping circuit, and the emitters are all connected to the output resistor of the shaping circuit.

7. A method for realizing integrated frequency raising and lowering of an incremental encoder according to claim 6, characterized in that: The incremental encoder outputs an A signal, a B signal and a Z signal to a multi-order RC filter in the adjustment circuit; The multi-order RC filter filters out the signal outside the frequency spectrum range of the target signal in the output signal, and outputs the target signal; The first transistor of the shaping circuit performs primary shaping on the target signal and outputs a primary shaped signal, the primary shaped signal enters the second transistor for secondary shaping, the second transistor outputs the secondary shaped signal to the third transistor, the third transistor performs tertiary shaping on the secondary shaped signal and outputs an adjustment signal.

8. A method for realizing integrated frequency increase and decrease of an incremental encoder according to claim 7, characterized in that: The input resistor, the output resistor and the transistor connected to the transistor form a current loop to adjust the duty cycle of the shaped signal.

9. A method for realizing integrated frequency raising and lowering of an incremental encoder according to claim 1, characterized in that: The A / B edge acquisition module detects the input of the adjustment Z signal, and outputs the adjustment Z signal to the Z signal output module of the frequency conversion implementation module.

10. A method for realizing integrated frequency raising and lowering of an incremental encoder according to claim 1, characterized in that: A Flash chip is provided to store relevant information of the FPGA module.

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