Switching circuit, selector and electronic chip
By designing a switching circuit that includes a transmission gate unit and a transistor, the overvoltage problem of the multiplexer when operating in the high-voltage domain is solved, achieving faster switching speed and lower nonlinear distortion.
Patent Information
- Application Number
- CN202411497637.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-24
- Publication Date
- 2025-01-24
AI Technical Summary
In the prior art, multiplexer is difficult to withstand high voltage signals when operating in the high voltage domain, resulting in increased circuit complexity and nonlinear distortion of sampled signals.
Design a switching circuit, including a first transmission gate unit, a second transmission gate unit, a first transistor, a first switching unit and a second switching unit. Through these components, a bootstrap signal is output to the control end of the sampling transistor of the selector. , using ordinary CMOS technology to reduce parasitic effects.
The effective output signal of the effective output under high -voltage domain reduces the nonlinear distortion of the sampling signal, and avoids the damage caused by the circuit caused by over pressure of the transistor.
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Figure CN119363082A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits and related technical fields, and in particular, to a switch circuit, a selector, and an electronic chip. Background Art
[0002] In many industries such as industry, instrumentation, optical communication and medical, multi-channel data acquisition systems are increasingly being used. To reduce costs, multiple input channels are usually multiplexed into an analog-to-digital conversion circuit through a multiplexer, and each channel shares one analog-to-digital conversion circuit, thereby reducing the overall circuit area. In order to improve the sampling linearity of the analog-to-digital conversion circuit, a gate voltage bootstrap circuit is usually set in the multiplexer to improve the sampling linearity of the analog-to-digital conversion circuit. According to the working principle of the gate voltage bootstrap circuit, it will generate a signal higher than the power supply voltage, so the front-end analog multiplexer of the ADC chip is required to be able to withstand high-voltage signals.
[0003] In the prior art, a high-voltage BCD process is usually used to design a multiplexer. The high-voltage BCD process integrates three main devices: Bipolar, CMOS, and DMOS. Among them, the DMOS device has CMOS-like characteristics and provides high-voltage resistance, but its area is much larger than that of the low-voltage device. The main circuit of the multiplexer designed based on the high-voltage BCD process is a high-voltage switch array composed of complementary DMOS devices and gate drive circuits, and the current bias and buffer circuits required for the normal operation of the switch are also required. The overall circuit is relatively complex. In this way, the chip needs to be manufactured using a specific high-voltage BCD process, which will proportionally increase the circuit area in a multi-channel input ADC and greatly increase the chip cost. At the same time, due to the limitations of the manufacturing process of the DMOS device, its parasitic bootstrap capacitance and on-resistance are both large. When it is used in the sampling circuit of the analog front end, the speed of turning on or off is slow, which will greatly increase the nonlinear distortion of the sampling signal. Summary of the invention
[0004] The embodiments described herein provide a switch circuit, a selector, and an electronic chip that can solve the overvoltage problem when working in a high voltage domain and can be implemented using a CMOS process.
[0005] In a first aspect, according to the present disclosure, there is provided a switch circuit for outputting a bootstrap signal generated by boosting a target signal by a bootstrap capacitor to a preset value, the switch circuit comprising a first transmission gate unit, a second transmission gate unit, a first transistor, a first switch unit, and a second switch unit;
[0006] The first end of the first transmission gate unit is used to connect to one end of the bootstrap capacitor for generating the bootstrap signal, the second end of the first transmission gate unit is connected to the first end of the first transistor, and the second end of the first transmission gate unit is also connected to the power supply voltage of the preset value through the first switch unit;
[0007] The first end of the second transmission gate unit is used to connect the target signal, the second end of the second transmission gate unit is connected to the control end of the first transistor, and the first end of the first transistor is also connected to the power supply voltage of the preset value through the second switch unit;
[0008] The second terminal of the first transistor is used as an output terminal of the switch circuit.
[0009] In some embodiments of the present disclosure, when the first transmission gate unit and the second transmission gate unit are both turned on, and the first switch unit and the second switch unit are both turned off, the switch circuit is turned on;
[0010] When the first transmission gate unit and the second transmission gate unit are both turned off, and the first switch unit and the second switch unit are both turned on, the switch circuit is turned off.
[0011] In some embodiments of the present disclosure, the first switch unit includes a seventh transistor, the second switch unit includes an eighth transistor, the first end of the seventh transistor and the first end of the eighth transistor are respectively electrically connected to the power supply voltage node of the preset value, the second end of the seventh transistor is electrically connected to the control end of the first transistor, and the second end of the eighth transistor is electrically connected to the first end of the first transistor.
[0012] In some embodiments of the present disclosure, the first transmission gate unit includes a fifth transistor and a sixth transistor, the first ends of the fifth transistor and the sixth transistor are connected to serve as the first end of the first transmission gate unit, and the second ends of the fifth transistor and the sixth transistor are electrically connected to the first end of the first transistor;
[0013] The second transmission gate unit includes a third transistor and a fourth transistor, wherein first terminals of the third transistor and the fourth transistor receive the target signal, and second terminals of the third transistor and the fourth transistor are electrically connected to the control terminal of the first transistor.
[0014] In a second aspect, according to the present disclosure, there is provided a selector, comprising: a control module and a passage module;
[0015] The path module includes a gate voltage bootstrap circuit, a bootstrap capacitor, a first switch circuit, a second switch circuit and a sampling transistor, wherein the first end of the bootstrap capacitor is connected to the first end of the sampling transistor through the first switch circuit, the second end of the bootstrap capacitor is connected to the control end of the sampling transistor through the second switch circuit, the first end of the sampling transistor is the input end of the path module to receive the target signal, and the second end of the sampling transistor is the output end of the path module;
[0016] The control module is used to control the first switch circuit and the second switch circuit to generate a bootstrap signal on the second end of the bootstrap capacitor and transmit the bootstrap signal to the control end of the sampling transistor to select the sampling transistor;
[0017] Wherein, the second switch circuit is any of the switch circuits mentioned above.
[0018] In some embodiments of the present disclosure, the path module further includes a third switch circuit, and the control end of the sampling transistor is further connected to a ground voltage signal through the third switch circuit;
[0019] When the second switch circuit is in an on state, the third switch circuit is in an off state;
[0020] When the second switch circuit is in an off state, the third switch circuit is in an on state.
[0021] In some embodiments of the present disclosure, the third switching circuit includes a ninth transistor, a tenth transistor, and an eleventh transistor, the first end of the ninth transistor is electrically connected to the power supply voltage node of the preset value, the second end of the ninth transistor and the second end of the tenth transistor are respectively electrically connected to the first end of the eleventh transistor, the second end of the eleventh transistor is electrically connected to the control end of the sampling transistor, and the first end of the tenth transistor receives a ground voltage signal.
[0022] In some embodiments of the present disclosure, a plurality of the pathway modules are included.
[0023] In some embodiments of the present disclosure, a plurality of the pass modules share the same gate voltage bootstrap circuit and the same bootstrap capacitor.
[0024] In a third aspect, according to the contents of the present disclosure, there is provided an electronic chip, comprising the switch circuit described in any one of the first aspects or the selector described in any one of the first aspects.
[0025] In the switch circuit, selector and electronic chip provided by the embodiment of the present disclosure, in the process of outputting the bootstrap signal to the control end of the sampling transistor of the selector based on the switch circuit, the switch circuit can adopt a common CMOS process, and the parasitic effect of the transistor device prepared by the CMOS process is less affected, so that the speed of opening or closing the switch circuit is faster, thereby reducing the nonlinear distortion of the sampling signal. In addition, in the process of outputting the bootstrap signal to the control end of the sampling transistor of the selector based on the switch circuit, the voltages at any two ends of the transistors included in the first transmission gate unit, the second transmission gate unit, the first switch unit and the second switch unit in the switch circuit are all within the power supply voltage range, avoiding damage to the circuit caused by overvoltage of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:
[0027] Figure 1 is a structural diagram of a selector provided by an embodiment of the present disclosure;
[0028] Figure 2 is a structural schematic diagram of a switch circuit provided by an embodiment of the present disclosure;
[0029] Figure 3 is a structural schematic diagram of another switch circuit provided by an embodiment of the present disclosure;
[0030] Figure 4 is a structural diagram of another selector provided by an embodiment of the present disclosure;
[0031] Figure 5 is a structural schematic diagram of a third switch circuit provided by an embodiment of the present disclosure;
[0032] Figure 6 is a structural schematic diagram of another third switch circuit provided by an embodiment of the present disclosure;
[0033] Figure 7-Figure 9 It is a state diagram of the second switch circuit and the third switch circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.
[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.
[0036] In all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).
[0037] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.
[0038] Based on the problems existing in the prior art, the present disclosure provides a switch circuit. Figure 1 is a schematic diagram of the structure of a selector provided in an embodiment of the present disclosure, Figure 2 is a schematic diagram of the structure of a switch circuit provided in an embodiment of the present disclosure, wherein the switch circuit is used to output Figure 1 The bootstrap capacitor shown in the figure boosts the target signal to a preset value to generate a bootstrap signal, combined with Figure 1 and Figure 2 , switching circuit (switching circuit is also called Figure 1The second switch circuit in the embodiment includes a first transmission gate unit 41, a second transmission gate unit 42, a first transistor M1, a first switch unit 43 and a second switch unit 44; the first end of the first transmission gate unit 41 is used to connect the end of the bootstrap capacitor for generating a bootstrap signal (i.e. Figure 1 A terminal of the bootstrap capacitor C shown in the figure), the second terminal of the first transmission gate unit 41 is connected to the first terminal of the first transistor M1, and the second terminal of the first transmission gate unit 41 is also connected to the power supply voltage Vdd with a preset value through the first switch unit 43; the first terminal of the second transmission gate unit 42 is used to connect the target signal IN, the second terminal of the second transmission gate unit 42 is connected to the control terminal of the first transistor M1, and the first terminal of the first transistor M1 is also connected to the power supply voltage Vdd with a preset value through the second switch unit 44; the second terminal of the first transistor M1 is used as the output terminal of the switch circuit.
[0039] As a specific implementation, when the first transmission gate unit 41 receives the bootstrap signal IN+Vdd and the second transmission gate unit 42 receives the target signal IN, when the first transmission gate unit 41 and the second transmission gate unit 42 are turned on and the first switch unit 43 and the second switch unit 43 are turned off, the first transmission gate unit 41 outputs the bootstrap signal IN+Vdd to the first end of the first transistor M1, and the signal at the first end of the first transistor M1 is the bootstrap signal IN+Vdd, and the second transmission gate unit 42 outputs the target signal to the control end of the first transistor M1, and the signal at the first end of the first transistor M1 is the target signal IN. At this time, the gate-source voltage of the first transistor M1 is greater than the threshold voltage of the transistor, the first transistor M1 is turned on, and the first transistor M1 outputs the bootstrap signal IN+Vdd to the control end of the sampling transistor M.
[0040] By setting a switch circuit in the selector, the bootstrap signal generated by the bootstrap capacitor boosting the target signal to a preset value is output to the control end of the sampling transistor M of the selector based on the switch circuit, and in the process of outputting the bootstrap signal to the control end of the sampling transistor of the selector based on the switch circuit, the switch circuit adopts a common CMOS process, and the parasitic effect of the transistor device prepared by the CMOS process is less affected, so that the opening or closing speed of the switch circuit is faster, thereby reducing the nonlinear distortion of the sampling signal. In addition, in the process of outputting the bootstrap signal to the control end of the sampling transistor of the selector based on the switch circuit, the voltages at any two ends of the transistors included in the first transmission gate unit, the second transmission gate unit, the first switch unit and the second switch unit in the switch circuit are all within the power supply voltage range, thereby avoiding damage to the circuit caused by transistor overvoltage.
[0041] In a specific embodiment, when the first transmission gate unit 41 and the second transmission gate unit 42 are both turned on and the first switch unit 43 and the second switch unit 44 are both turned off, the switch circuit is turned on; when the first transmission gate unit 41 and the second transmission gate unit 42 are both turned off and the first switch unit 43 and the second switch unit 44 are both turned on, the switch circuit is turned off.
[0042] Specifically, when the first transmission gate unit 41 and the second transmission gate unit 42 are turned on, and the first switch unit 43 and the second switch unit 44 are turned off, at this time, the first transmission gate unit 41 outputs the bootstrap signal IN+Vdd to the first end of the first transistor M1, and the second transmission gate unit 42 outputs the target signal IN to the control end of the first transistor M1. The gate-source voltage of the first transistor is Vdd, the first transistor M1 is turned on, and the first transistor M1 outputs the bootstrap signal IN+Vdd, that is, the switch circuit is turned on, and the switch circuit outputs the bootstrap signal IN+Vdd.
[0043] When the first transmission gate unit 41 and the second transmission gate unit 42 are turned off, and the first switch unit 43 and the second switch unit 44 are turned on, at this time, the first switch unit 43 outputs a preset value of the power supply voltage Vdd to the control end of the first transistor M1, and the second switch unit 44 outputs a preset value of the power supply voltage Vdd to the first end of the first transistor M1, the gate-source voltage of the first transistor M1 is 0, and the first transistor M1 is turned off, that is, the switch circuit is turned off.
[0044] In a specific embodiment, in combination with Figure 2 The first transmission gate unit 41 includes a fifth transistor M5 and a sixth transistor M6, the first ends of the fifth transistor M5 and the sixth transistor M6 are connected to serve as the first end of the first transmission gate unit, and the second ends of the fifth transistor M5 and the sixth transistor M6 are electrically connected to the first end of the first transistor M1. The second transmission gate unit 42 includes a third transistor M3 and a fourth transistor M4, the first ends of the third transistor M3 and the fourth transistor M4 receive the target signal IN, and the second ends of the third transistor M3 and the fourth transistor M4 are electrically connected to the control end of the first transistor M1.
[0045] In a specific implementation manner, see Figure 2 The first switch unit 43 includes a seventh transistor M7, the second switch unit 44 includes an eighth transistor M8, the first end of the seventh transistor M7 and the first end of the eighth transistor M8 are respectively electrically connected to the power supply voltage node of the preset value, the second end of the seventh transistor M7 is electrically connected to the control end of the first transistor M1, and the second end of the eighth transistor M8 is electrically connected to the first end of the first transistor M1.
[0046] In an exemplary embodiment, the first transmission gate unit 41 and the second transmission gate unit 42 are turned on under the control signal output by the control module 100 of the selector, the first switch unit 43 and the second switch unit 44 are turned off under the control signal output by the control module 100, the first end of the third transistor M3 and the fourth transistor M4 receives the target signal IN, the first end of the fifth transistor M5 and the sixth transistor M6 receives the bootstrap signal Vdd+IN, the first end of the seventh transistor M7 and the eighth transistor M8 receives the power supply voltage Vdd, the voltage of the control signal output by the control module 100 to the control end of the third transistor M3 is 0, the voltage of the control signal output by the control module 100 to the control ends of the fourth transistor M4, the fifth transistor M5, the seventh transistor M7 and the eighth transistor M8 is Vdd, The voltage of the control signal output by the control module 100 to the control end of the sixth transistor M6 is 2Vdd. At this time, the gate-source voltage of the third transistor M3 and the fifth transistor M5 is less than the transistor threshold voltage, the gate-source voltage of the fourth transistor M4 and the sixth transistor M6 is greater than the transistor threshold voltage, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned on, the gate-source voltage of the seventh transistor M7 and the eighth transistor M8 is 0, the seventh transistor M7 and the eighth transistor M8 are turned off, the first end of the first transistor M1 receives the bootstrap signal Vdd+IN, the control end of the first transistor M1 receives the target signal IN, the first transistor is turned on, the switch circuit is turned on, and the voltage output by the switch circuit to the control end of the connected sampling transistor M is the bootstrap signal IN+Vdd.
[0047] In another exemplary embodiment, the first transmission gate unit 41 and the second transmission gate unit 42 are turned off under the control signal output by the control module, the first switch unit 43 and the second switch unit 44 are turned on under the control signal output by the control module, the first end of the third transistor M3 and the fourth transistor M4 receives the target signal IN, the first end of the fifth transistor M5 and the sixth transistor M6 receives the bootstrap signal Vdd+IN, the first end of the seventh transistor M7 and the eighth transistor M8 receives the power supply voltage Vdd, the voltage of the control signal output by the control module to the control end of the third transistor M3 and the sixth transistor is Vdd, the voltage of the control signal output by the control module to the control end of the fourth transistor M4 and the seventh transistor M7 is 0, and the control module outputs to the fifth transistor The voltage of the control signal of the control end of the third transistor M5 and the eighth transistor M8 is 2Vdd. At this time, the gate-source voltage of the third transistor M3 and the fifth transistor M5 is greater than the transistor threshold voltage, the gate-source voltage of the fourth transistor M4 and the sixth transistor M6 is less than the transistor threshold voltage, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned off, the gate-source power supply of the seventh transistor M7 is less than the transistor threshold voltage, the gate-source voltage of the eighth transistor M8 and the tenth transistor M10 is greater than the transistor threshold voltage, the seventh transistor M7 and the eighth transistor M8 are turned on, the first end of the first transistor M1 receives the power supply voltage Vdd, the control end of the first transistor M1 also receives the power supply voltage Vdd, the first transistor M1 is turned off, and the switch circuit is turned off.
[0048] In the disclosed embodiment, the voltages at either end of each transistor included in the switch circuit are within the range of the power supply voltage Vdd, thereby avoiding the risk of burning out the chip and fully ensuring the reliability and service life of the chip.
[0049] Based on the above embodiment, the present disclosure also provides a selector, Figure 1 The selector includes: a control module 100 and a path module 200; the path module 200 includes a gate voltage bootstrap circuit 30, a bootstrap capacitor C, a first switch circuit 20, a second switch circuit 40 and a sampling transistor M, the first end of the bootstrap capacitor C is connected to the first end of the sampling transistor M through the first switch circuit 20, the second end of the bootstrap capacitor C is connected to the control end of the sampling transistor M through the second switch circuit 40, the first end of the sampling transistor M is the input end of the path module 200 to receive the target signal, and the second end of the sampling transistor M is the output end of the path module 200; the control module 100 is used to control the first switch circuit 20 and the second switch circuit 40 to generate a bootstrap signal Vdd+IN on the second end of the bootstrap capacitor C, and transmit it to the control end of the sampling transistor M to select the sampling transistor M; wherein the second switch circuit 40 is the switch circuit described in any one of the above embodiments.
[0050] In a specific embodiment, Figure 1 The exemplary representation shows that the selector includes four path modules 200, and any one of the path modules includes a first switch circuit 20, a gate voltage bootstrap circuit 30, a second switch circuit 40, a bootstrap capacitor C and a sampling transistor M, that is, the number of channels of the selector input channel is 4. The embodiment of the present disclosure does not specifically limit the number of channels of the selector input channel.
[0051] In a specific implementation, if the selector is in the charging phase, the control module 100 controls the gate voltage bootstrap circuit 30 to be turned on, and the control module 100 controls the first switch circuit 20 and the second switch circuit 40 to be turned off. At this time, the bootstrap capacitor C is charged through the gate voltage bootstrap circuit 30. At this time, the voltage at the second end of the bootstrap capacitor C is charged to a preset value (i.e., the power supply voltage Vdd). If the selector is in the charging phase, the control module 100 controls the gate voltage bootstrap circuit 30 to be turned off, and the control module 100 controls the first switch circuit 20 and the second switch circuit 40 to be turned on. The first switch circuit 20 outputs the target signal IN to the first end of the bootstrap capacitor C. In combination with the characteristics of the voltage at both ends of the capacitor changing suddenly, the voltage at the second end of the bootstrap capacitor C increases the target signal IN on the basis of the preset value to obtain the bootstrap signal Vdd+IN, and is transmitted to the control end of the sampling transistor M through the turned-on second switch circuit 40, thereby turning on the sampling transistor M.
[0052] Since the second switch circuit 40 in the selector provided in the embodiment of the present disclosure adopts a common CMOS process, the parasitic effect of the transistor device formed based on the CMOS process is less affected, so the speed of opening or closing the second switch circuit is faster, thereby reducing the nonlinear distortion of the sampling signal. In addition, in the process of the selector outputting the bootstrap signal to the control end of the sampling transistor of the selector based on the second switch circuit, the voltages at any two ends of the transistors included in the first transmission gate unit, the second transmission gate unit, the first switch unit and the second switch unit in the switch circuit are all within the power supply voltage range, thereby avoiding damage to the circuit caused by overvoltage of the transistor.
[0053] Based on the above embodiments, Figure 4 As shown, the path module 200 also includes a third switch circuit 50, and the control end of the sampling transistor M is also connected to the ground voltage signal through the third switch circuit 50; when the second switch circuit 40 is in the on state, the third switch circuit 50 is in the off state; when the second switch circuit 40 is in the off state, the third switch circuit 50 is in the on state.
[0054] By setting the third switch module 50 in the path module, when the second switch circuit 40 is in the off state, the control module controls the third switch circuit 50 to be in the on state, so that the third switch circuit 50 outputs a ground voltage signal to the control end of the sampling transistor to control the sampling transistor to be turned off. When the second switch circuit 40 is in the on state, the control module controls the third switch circuit 50 to be in the off state, so that the bootstrap signal output by the second switch circuit acts on the control end of the sampling transistor.
[0055] Among them, the third switch circuit includes a ninth transistor M9, a tenth transistor M10 and an eleventh transistor M11, the first end of the ninth transistor M9 is electrically connected to the power supply voltage node of the preset value, the second end of the ninth transistor M9 and the second end of the tenth transistor M10 are respectively electrically connected to the first end of the eleventh transistor M11, the second end of the eleventh transistor M11 is electrically connected to the control end of the sampling transistor M, and the first end of the tenth transistor M10 receives a ground voltage signal.
[0056] An exemplary combination Figure 5 When the second switch circuit is in the on state, the voltage applied by the control module to the control ends of the ninth transistor M9 and the tenth transistor M10 is 0, and the voltage applied by the control module to the control end of the eleventh transistor M11 is Vdd. At this time, the gate-source voltage of the ninth transistor is less than the transistor threshold voltage, the gate-source voltage of the tenth transistor is 0, the ninth transistor is turned on, the ninth transistor M9 outputs the power supply voltage to the first end of the eleventh transistor M11, and when the eleventh transistor M11 receives the power supply voltage output by the ninth transistor M9, the gate-source voltage of the eleventh transistor M11 is 0, and the eleventh transistor M11 is turned off, that is, the third switch circuit is turned off.
[0057] Another exemplary method, combined with Figure 6 When the second switch circuit is in the off state, the voltage applied by the control module to the control ends of the ninth transistor M9 and the tenth transistor M10 is Vdd, and the voltage applied by the control module to the control end of the eleventh transistor M11 is Vdd. At this time, the gate-source voltage of the ninth transistor M9 is 0, the gate-source voltage of the tenth transistor M10 is greater than the threshold voltage of the transistor, the tenth transistor M10 is turned on, and the tenth transistor M10 outputs a ground voltage signal to the first end of the eleventh transistor M11. When the eleventh transistor M11 receives the ground voltage signal output by the tenth transistor M10, the gate-source voltage of the eleventh transistor M11 is greater than the transistor threshold voltage, and the eleventh transistor M11 is turned on, that is, the third switch circuit is turned on, and the third switch unit outputs a ground voltage signal to the control end of the sampling transistor.
[0058] It should be noted that the first transistor M1, the third transistor M3, the fifth transistor M5, and the seventh transistor M7 are PMOS transistors, and the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are NMOS transistors.
[0059] It should be noted that in the above embodiments, corresponding to the NMOS type transistor, the end with a lower potential between the first and second ends of the transistor is the source end, and corresponding to the PMOS type transistor, the end with a higher potential between the first and second ends of the transistor is the source end.
[0060] In the disclosed embodiment, each sampling transistor is an NMOS transistor.
[0061] In addition, in the embodiments of the present disclosure, each sampling transistor is exemplified as an NMOS transistor for specific illustration. In other possible implementations, when each sampling transistor is a PMOS transistor, the transistor types of other transistors except the third transistor, the fourth transistor, the fifth transistor and the sixth transistor in the second switch circuit need to be interchanged, and the control signal acting on the second switch circuit is modified accordingly. The embodiments of the present disclosure do not specifically limit this.
[0062] As a specific implementation, the selector includes a plurality of pathway modules.
[0063] The number of path modules included in the selector is the same as the number of input terminals of the selector. One path module corresponds to one input terminal. The control module in the selector selects the sampling transistor in the path module corresponding to the target input terminal to output the voltage input to the target input terminal (the voltage input to the target input terminal is also the target signal in this application).
[0064] Specifically, Figure 1 The exemplary representation selector includes four path modules, one path module corresponding to one input terminal.
[0065] As a preferred embodiment, continue to refer to Figure 1 , multiple pass modules share the same gate voltage bootstrap circuit and the same bootstrap capacitor.
[0066] By arranging a plurality of path modules to share a gate voltage bootstrap circuit and a same bootstrap capacitor, the overall circuit area of the selector is reduced.
[0067] In the disclosed embodiment, the first switch circuit, the second switch circuit and the third switch circuit in the selector all adopt conventional, non-high-voltage CMOS technology, the circuit layout area is greatly reduced, and the parasitic effects of transistor devices are less affected.
[0068] For example, the outputs of multiple path modules are connected to the same ADC (such as a SAR ADC);
[0069] When the ADC is in the sampling state, that is, the gate voltage bootstrap circuit is in the sampling phase, assuming that the input signal of the IN1 path module is to be selected, the states of the second switch circuit and the third switch circuit of the IN1 path module are as follows: Figure 7 As shown, at this time, the second transmission gate unit composed of the third transistor M3 and the fourth transistor M4 transmits the input signal IN1 to the control end of the first transistor M1, and the first transmission gate unit composed of the fifth transistor M5 and the sixth transistor M6 transmits the bootstrap signal IN1+Vdd to the first end of the first transistor M1. Therefore, the first transistor M1 is turned on, and the first transistor M1 transmits the bootstrap signal IN1+Vdd to the control end of the sampling transistor M. At the same time, the ninth transistor M9 is turned on, and the power supply voltage is transmitted to the first end of the eleventh transistor M11, and the eleventh transistor M11 is turned off. It can be seen that the voltage difference between any two ends of all transistors is within the range of the power supply voltage Vdd, and there is no overvoltage problem in the entire signal path.
[0070] When the gate voltage bootstrap circuit is in the sampling phase, the states of the unselected IN0 path module, the IN2 path module, and the second switch circuit and the third switch circuit of the IN2 path module are as follows: Figure 8 As shown, the first transmission gate unit and the second transmission gate unit are both turned off, the voltages of the control terminal and the first terminal of the first transistor M1 are both the power supply voltage Vdd, and the first transistor M1 is turned off. At this time, the tenth transistor M10 and the eleventh transistor M11 are turned on, so that the voltage of the control terminal of the sampling transistor is 0V. It can be seen that when it is not selected, each MOS tube has no overvoltage problem.
[0071] When the ADC is in a non-sampling state, that is, the gate voltage bootstrap circuit is in a charging phase, the states of the second switch circuit and the third switch circuit of all the path modules are as follows: Fig. 9 As shown, at this time, the first terminal voltage of the fifth transistor M5 and the sixth transistor M6 is the power supply voltage Vdd, and the states of the other MOS tubes and the node voltages are Figure 8 Consistent, and no overvoltage problem.
[0072] The embodiment of the present disclosure further provides an electronic chip, which includes a selector and a switch circuit according to the embodiment of the present disclosure.
[0073] The embodiments of the present disclosure also provide an electronic device. The electronic device includes an electronic chip according to the embodiments of the present disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer, a smart phone, etc.
[0074] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.
[0075] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, the serial numbers of the embodiments of the present application mentioned above are only for description and do not represent the advantages and disadvantages of the embodiments.
[0076] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0077] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A switch circuit for outputting a bootstrap signal generated by boosting a target signal by a bootstrap capacitor to a preset value, characterized in that: The switch circuit includes a first transmission gate unit, a second transmission gate unit, a first transistor, a first switch unit and a second switch unit; The first end of the first transmission gate unit is used to connect to one end of the bootstrap capacitor for generating the bootstrap signal, the second end of the first transmission gate unit is connected to the first end of the first transistor, and the second end of the first transmission gate unit is also connected to the power supply voltage of the preset value through the first switch unit; The first end of the second transmission gate unit is used to connect the target signal, the second end of the second transmission gate unit is connected to the control end of the first transistor, and the first end of the first transistor is also connected to the power supply voltage of the preset value through the second switch unit; The second terminal of the first transistor is used as an output terminal of the switch circuit.
2. The switch circuit according to claim 1, characterized in that: When the first transmission gate unit and the second transmission gate unit are both turned on, and the first switch unit and the second switch unit are both turned off, the switch circuit is turned on; When the first transmission gate unit and the second transmission gate unit are both turned off, and the first switch unit and the second switch unit are both turned on, the switch circuit is turned off.
3. The switch circuit according to claim 1, characterized in that: The first switch unit includes a seventh transistor, and the second switch unit includes an eighth transistor. The first end of the seventh transistor and the first end of the eighth transistor are respectively electrically connected to the power supply voltage node of the preset value, the second end of the seventh transistor is electrically connected to the control end of the first transistor, and the second end of the eighth transistor is electrically connected to the first end of the first transistor.
4. The switch circuit according to claim 1, characterized in that: The first transmission gate unit includes a fifth transistor and a sixth transistor, wherein the first ends of the fifth transistor and the sixth transistor are connected to each other as the first end of the first transmission gate unit, and the second ends of the fifth transistor and the sixth transistor are electrically connected to the first end of the first transistor; The second transmission gate unit includes a third transistor and a fourth transistor, wherein first terminals of the third transistor and the fourth transistor receive the target signal, and second terminals of the third transistor and the fourth transistor are electrically connected to the control terminal of the first transistor.
5. A selector, characterized in that: include: Control module and access module; The path module includes a gate voltage bootstrap circuit, a bootstrap capacitor, a first switch circuit, a second switch circuit and a sampling transistor, wherein the first end of the bootstrap capacitor is connected to the first end of the sampling transistor through the first switch circuit, the second end of the bootstrap capacitor is connected to the control end of the sampling transistor through the second switch circuit, the first end of the sampling transistor is the input end of the path module to receive the target signal, and the second end of the sampling transistor is the output end of the path module; The control module is used to control the first switch circuit and the second switch circuit to generate a bootstrap signal on the second end of the bootstrap capacitor and transmit the bootstrap signal to the control end of the sampling transistor to select the sampling transistor; Wherein, the second switching circuit is the switching circuit described in any one of claims 1-4.
6. The selector according to claim 5, characterized in that The path module further includes a third switch circuit, and the control end of the sampling transistor is further connected to a ground voltage signal through the third switch circuit; When the second switch circuit is in an on state, the third switch circuit is in an off state; When the second switch circuit is in an off state, the third switch circuit is in an on state.
7. The selector according to claim 5, characterized in that The third switch circuit includes a ninth transistor, a tenth transistor and an eleventh transistor, the first end of the ninth transistor is electrically connected to the power supply voltage node of the preset value, the second end of the ninth transistor and the second end of the tenth transistor are electrically connected to the first end of the eleventh transistor respectively, the second end of the eleventh transistor is electrically connected to the control end of the sampling transistor, and the first end of the tenth transistor receives a ground voltage signal.
8. The selector according to claim 5, characterized in that It comprises a plurality of said pathway modules.
9. The selector according to claim 8, characterized in that A plurality of the pass modules share the same gate voltage bootstrap circuit and the same bootstrap capacitor.
10. An electronic chip, characterized in that: It comprises the switch circuit described in any one of claims 1 to 4 or the selector described in any one of claims 5 to 9.