Interface circuit with hysteresis and level shift characteristics

Abstract

The invention discloses an interface circuit with hysteresis and level shift characteristics. The interface circuit comprises a VCC power supply end, a COM end, an amplification circuit, a load circuit and a bias generation circuit, wherein the amplification circuit and the load circuit are sequentially arranged between the VCC power supply end and the COM end, and the bias generation circuit is connected with the amplification circuit and the load circuit. The bias generation circuit is also connected with the VCC power supply end and the COM end; the amplifying circuit and the load circuit are both connected with the output node VO, the output node VO is connected with the input end of the phase inverter or the Schmitt trigger, and the output end of the phase inverter or the Schmitt trigger is both connected with the amplifying circuit and the load circuit. According to the invention, the hysteresis characteristic of the interface circuit can be realized, and the noise tolerance and interference resistance of the interface circuit are improved; the high-voltage gate drive chip interface circuit is simple in structure, can directly realize level shift operation of signals, does not need extra Regulator and level shift circuits compared with a traditional high-voltage gate drive chip interface circuit, greatly simplifies the circuit structure, and improves the circuit reliability; the circuit has the characteristics of simple structure, few required devices and low circuit design difficulty.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor high-voltage gate drive IC design, and in particular to an interface circuit with hysteresis and level shift characteristics. Background Art

[0002] High-voltage gate driver chips are an important bridge between controllers and power transistors (MOSFET, IGBT, GaN, SiCet.al.). The control chip sends PWM switching signals to the power transistors. Since the operating voltage of the controller chip is low (usually 3.3V or 5V), the output current capability is weak, and the controller is difficult to tolerate the electrical noise (dv / dt, di / dt, etc.) during the switching process of the power device, a high-voltage gate driver chip is required to amplify the switching signal to drive the switching of the power device, and at the same time provide intelligent protection for the power device (including undervoltage protection, overtemperature protection, anti-shoot-through protection, etc.).

[0003] The operating voltage of the high-voltage gate driver chip VCC is 10-20V (commonly 15V), and the HIN and LIN input ports are compatible with 3.3V, 5V and 15V logic levels. The commonly used interface circuit solution is to use a Schmitt trigger (SMT) and a 15V to 5V voltage regulator (15V to 5V Regulator) to read the input signal, such as Figure 1 In this circuit scheme, the hysteresis characteristic of the Schmitt trigger enables the interface circuit to have a certain noise resistance. At the same time, in order to be compatible with 3.3V logic input, the forward trigger voltage (VSMT, T+) of the Schmitt trigger is required to be lower than 3.3V. Since the forward trigger voltage of the Schmitt trigger changes with the chip power supply voltage, it is difficult to achieve compatibility with the 3.3V logic level within the voltage range of 10 to 20V. Therefore, a 15V to 5V regulator circuit is required. After the input PWM signal is read into the gate drive chip by the interface circuit, the 0 to 5V voltage rail signal needs to be converted to the 0 to VCC voltage rail through a level shift circuit.

[0004] Since the circuit involves operations such as power supply voltage conversion and signal level shifting, it has problems such as complex structure, large number of required components, slow circuit response and large delay. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects in the prior art and provide an interface circuit with hysteresis and level shift characteristics, which has the characteristics of simple structure, few required components and low circuit design difficulty.

[0006] To achieve the above-mentioned purpose, the technical solution of the present invention is to design an interface circuit with hysteresis and level shift characteristics, including a VCC power supply terminal, a COM terminal, an amplifier circuit and a load circuit sequentially arranged between the VCC power supply terminal and the COM terminal, and a bias generating circuit connected to both the amplifier circuit and the load circuit; the bias generating circuit is also connected to both the VCC power supply terminal and the COM terminal; the amplifier circuit and the load circuit are both connected to an output node VO, the output node VO is connected to the input terminal of an inverter or a Schmitt trigger, and the output terminal of the inverter or the Schmitt trigger is connected to both the amplifier circuit and the load circuit.

[0007] A further technical solution is that the voltage of the VCC power supply terminal is VCC; and the voltage swing of the output node VO of the amplifier circuit and the load circuit is 0 to VCC.

[0008] A further technical solution is that the amplifier circuit is a common-source amplifier circuit or a common-gate amplifier circuit.

[0009] A further technical solution is that the common-source amplifier circuit is a simple common-source amplifier, including a first common-source amplifier tube and a second common-source amplifier tube respectively connected to the VIN terminal, the first common-source amplifier tube and the second common-source amplifier tube are connected in parallel; the feedback switch tube is connected to the second common-source amplifier tube, the feedback switch tube is also connected to the output node VO, the output node VO is also connected to the first common-source amplifier tube; the first common-source amplifier tube and the second common-source amplifier tube are both connected to the COM terminal.

[0010] A further technical solution is that the common source amplifier circuit is a common source single-stage amplifier circuit with a source resistor Rs; it includes a first common source amplifier tube connected to the VIN terminal, the first common source amplifier tube is respectively connected to the output node VO and the feedback switch tube, the source of the first common source amplifier tube is connected to the COM terminal through the resistor Rs, and the feedback switch tube is connected to the COM terminal.

[0011] A further technical solution is that the load circuit includes a first current mirror load tube PM1 arranged between the output node VO and the VCC power supply end, a second current mirror load tube PM2 and a hysteresis switch tube PM3 connected in parallel with the first current mirror load tube PM1, and the second current mirror load tube PM2 and the hysteresis switch tube PM3 are connected in sequence.

[0012] A further technical solution is that the load circuit includes a first load resistor RL1 and a second load resistor RL2 which are connected in sequence and arranged between the output node VO and the VCC power supply terminal, and a hysteresis switch PM4 which is connected in parallel with the first load resistor RL1.

[0013] The advantages and beneficial effects of the present invention are:

[0014] 1. According to the interface circuit design architecture proposed in the present invention, the hysteresis characteristics of the interface circuit can be realized, thereby improving the interface circuit's ability to tolerate noise and resist interference.

[0015] 2. According to the interface circuit design architecture proposed in the present invention, the level shift operation of the signal can be directly realized. Compared with the interface circuit of the traditional high-voltage gate drive chip, no additional regulator and level shifter circuits are required, which greatly simplifies the circuit structure and improves the circuit reliability.

[0016] 3. The interface circuit design architecture proposed in the present invention includes Amplifier, Load and Bias circuit modules. Each module has low design difficulty and diverse circuit structures. By optimizing the design of each module, higher circuit design indicators (such as low temperature drift, low PVT dependence and other excellent performance interface circuits) can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure of the interface circuit of the gate drive chip in the prior art;

[0018] Figure 2 It is a schematic diagram of the structure of an interface circuit with hysteresis and level shift characteristics of the present invention;

[0019] Figure 3 It is an amplifier circuit with hysteresis characteristics based on the common source amplifier design;

[0020] Figure 4 It is an amplifier circuit with hysteresis characteristics based on the common source amplifier design;

[0021] Figure 5 It is a load circuit with hysteresis characteristics;

[0022] Figure 6 It is a schematic diagram of a common-source amplifier with hysteresis and a current source load with hysteresis as an interface circuit with hysteresis and level shift characteristics according to the first embodiment of the present invention;

[0023] Figure 7 4 is a schematic diagram of an interface circuit with low PVT dependence and hysteresis and level shift characteristics according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The specific implementation of the present invention is further described below in conjunction with the accompanying drawings and embodiments. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0025] The present invention is an interface circuit with hysteresis and level shift characteristics. The circuit design scheme is as follows Figure 2 Considering that the input signal and the high-voltage gate driver chip share the same ground, and the input signal VIN has the characteristics of multiple amplitudes, under the power rails of VCC and COM, the switch signal is smoothly transmitted into the chip by adopting the combination design of the amplifier circuit (Amplifier) ​​and the load circuit (Load); the voltage swing of the output node VO of the amplifier and load circuit needs to be 0~VCC, and the VO point signal is transmitted to the FB point by the inverter or SMT. The FB signal is fed back to the amplifier and load circuit to change the state of the amplifier and load circuit (impedance, gain, bias current, etc.) to realize the positive feedback hysteresis characteristics of the interface circuit. The bias circuit is a bias generation circuit, which provides a static operating point for the amplifier and load. Based on the above working principle, the design purpose of interface circuit hysteresis and level shift can be achieved. It should be pointed out that the FB feedback needs to satisfy the hysteresis positive feedback polarity of the circuit, and the node of the FB feedback should be reasonably selected according to the actual circuit; in addition, the hysteresis characteristic can be generated by the load, or by the amplifier, or by both the amplifier and the load. The circuit design of the load and amplifier needs to select a suitable circuit structure according to the actual circuit design requirements.

[0026] Based on the above circuit design scheme, typical application design examples of Amplifier, Load, overall interface and Bias circuit modules will be described in detail below, but are not limited to the circuit scheme mentioned below.

[0027] Amplifier circuit design:

[0028] Since the output voltage swing of VO point is required to be between 0 and VCC, the amplifier needs to have sufficient pull-down capability to pull the voltage of VO point down to COM. Therefore, commonly used simple amplifiers, such as common source stage and common gate stage, can be used as the design of amplifier. Take the design of simple common source stage amplifier as an example. Figure 3 and Figure 4 .

[0029] like Figure 3, a common-source single-stage amplifier NM1 is used as the input tube of VIN, NM2 is also used as a common-source amplifier and connected in parallel with NM1, and NM3 is used as a feedback switch tube. When the high and low levels of VIN are transmitted to the circuit, the switch of NM3 tube is controlled by feedback FB. When VIN transmits the rising edge, FB is at a low level, and NM3 is cut off. As the VIN voltage increases and reaches VT+, NM1 pulls the VO voltage down to COM, and the FB voltage is then fed back to a high level. NM3 is turned on and further pulls VO down to stabilize the low-level state of VO. When the falling edge of VIN comes, since NM1 and NM2 tubes pull VO down together, VIN needs to drop to a voltage VT- lower than VT+ to close the pull-down loop. A hysteresis characteristic is formed.

[0030] like Figure 4 , another common-source single-stage amplifier circuit with source resistor Rs is provided. NM1 is a common-source amplifier tube, and NM4 is used as a feedback switch tube. Similarly, when the high and low levels of VIN are transmitted to the circuit, the switch of NM4 tube is controlled by feedback FB. When VIN transmits the rising edge, FB is required to be at a low level, NM4 is cut off, and Rs is connected in series to the ground loop of NM1. As the VIN voltage increases and reaches VT+, NM1 pulls the VO voltage down to COM, and the FB voltage is then fed back to a high level, NM4 is turned on, and the Rs resistor is short-circuited, and the VO impedance to ground is reduced, further stabilizing the VO low-level state. When the falling edge of VIN comes, since the source of NM1 is directly connected to COM, VIN needs to drop to a voltage VT- lower than VT+ to close the pull-down loop to form a hysteresis characteristic.

[0031] Load Circuit Design

[0032] Load is the load circuit of Amplifier. Different load types have different UI characteristics. Common loads include resistors, current mirrors, and diode-connected MOS. The hysteresis design of Load circuit is similar to the above. Figure 5 A current mirror and a resistor are given as a simple and typical hysteresis load; PM1 and PM2 are current mirror load tubes, PM3 and PM4 are hysteresis switch tubes for adjusting the load output current, RL1 and RL2 are load resistors, and the impedance of VO to VCC is changed by switching the feedback tube PM4.

[0033] Embodiment 1:

[0034] Typical design example of interface circuit based on the present invention

[0035] The present invention takes a common source amplifier with hysteresis characteristics and a current source load with hysteresis as a typical application circuit as an example. Figure 6As shown, NM1 and NM2 are common source input amplifiers, NM3 and PM3 are hysteresis switch tubes, PM1 and PM2 are current mirror loads, and PM4 is a current mirror replica tube. When VIN is at a low level, FB is at a low level, at which time NM3 is cut off, PM3 is turned on, and the VO node has a charging current of ID,PM1+ID,PM2. When VIN inputs a rising edge voltage signal, as the VIN voltage increases, NM1 changes from the cutoff region to saturated conduction. When the NM1 pull-down current is equal to the sum of the PM1 and PM2 currents, the VO node voltage will be pulled down from a high level to a low level. When VO flips, the current relationship satisfies Formula ①, where ID,PM1 and ID,PM2 are α and β times the Ib current, respectively, and ID,NM1 satisfies the square law, as shown in Formula ②. According to equations ① and ②, when VIN inputs a rising edge, the input flip threshold VT+ is obtained, as shown in equation ③; when the VO voltage flips to a low level, FB becomes a high level, at which time NM3 is turned on, PM3 is turned off, and the VO state is stabilized at a low level. When the falling edge inputs VIN, when the currents of NM1 and NM2 are equal to the current of PM1, the VO voltage is pulled up to VCC, as shown in equation ④. At this time, the corresponding low-level input flip threshold VT- of VIN, when NM1 and NM2 are at VGS=VT-, their currents obey the square law, as shown in equation ⑤. From equations ④ and ⑤, the expression of VT- can be solved, as shown in equation ⑥, and the hysteresis window VIN,hys=VT+-VT-, and the result is shown in equation ⑦. By reasonably adjusting parameters such as (W / L)NM1, (W / L)NM2, Ib, α and β, the required interface circuit can be designed.

[0036] I D，NM1 =I D，PM1 +I D，PM2 =αI b +βI b =(α+β)I b ①

[0037]

[0038] I D，NM1 +I D，NM2 =I D，PM1 =αI b ④

[0039]

[0040]

[0041] Through equations ③, ⑥, and ⑦, we can see that μnCox and Vth,n exist in the expressions of VT+, VT-, and VIN,hys, so the circuit characteristics are greatly affected by PVT (Process, Voltage and Temperature). The present invention can also reduce or immunize the dependence of VT+ and VT- on PVT by optimizing the design of the Bias circuit.

[0042] Embodiment 2: The difference from Embodiment 1 is that a typical design example of an interface circuit with low PVT dependence based on the present invention is

[0043] like Figure 7 , a typical design case of the interface circuit with low PVT dependence based on the present invention is provided, DZ is a Zener diode, PM7, PM8, DZ, R1, R2, R3, NM2, NM3, PM3, PM6 constitute a Bias circuit, and PM1, PM2, PM4, PM5 constitute a Load circuit. When VIN is at a low level, FB1 is also at a low level, FB2 is at a high level, PM2 is turned on, PM5 is turned off, and the VO node has a constant pull-up current of ID,PM1. If the width-to-length ratio of PM1 and PM3 is set equal, the width-to-length ratio of PM4 and PM6 is also equal, and the channel length modulation effect is ignored, then ID,PM1=ID,NM2, ID,PM4=ID,NM3, and the voltage at point Z is the Zener breakdown voltage VZ, then there are formulas ⑧ and ⑨. The rising edge flip condition is that when the current of NM1 is equal to the current of PM1, the VO voltage flips from high to low, as shown in formula ⑩. If the size of NM2, NM1, and NM3 is set to be the same, VT+ has After VO flips to low level, FB1 becomes high level, FB2 becomes low level, PM2 is turned off, PM5 is turned on, and the VO node has a constant pull-up current of ID,PM4. When VIN gives a falling edge signal, the VO flip condition is that the current of NM1 is equal to ID,PM4. Similarly, there is a formula and It can be seen that after optimizing the Bias design circuit, VT+ and VT- are immune to the influence of the process angle from MOS, and the resistance term exists in the expression in a proportional form, so it is basically immune to the threshold deviation caused by the resistor. The PVT deviation of the flip threshold is mainly affected by the Zener, which greatly reduces the dependence of the circuit characteristics on PVT.

[0044]

[0045] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An interface circuit with hysteresis and level shift characteristics, characterized in that: It includes a VCC power supply terminal, a COM terminal, an amplifier circuit and a load circuit arranged in sequence between the VCC power supply terminal and the COM terminal, and a bias generating circuit connected to both the amplifier circuit and the load circuit; the bias generating circuit is also connected to both the VCC power supply terminal and the COM terminal; both the amplifier circuit and the load circuit are connected to an output node VO, the output node VO is connected to an input terminal of an inverter or a Schmitt trigger, and the output terminal of the inverter or the Schmitt trigger is connected to both the amplifier circuit and the load circuit.

2. The interface circuit with hysteresis and level shift characteristics according to claim 1, characterized in that: The voltage of the VCC power supply terminal is VCC; the voltage swing of the output node VO of the amplifier circuit and the load circuit is 0-VCC.

3. The interface circuit with hysteresis and level shift characteristics according to claim 2, characterized in that: The amplifier circuit is a common-source amplifier circuit or a common-gate amplifier circuit.

4. The interface circuit with hysteresis and level shift characteristics according to claim 3, characterized in that: The common-source amplifier circuit is a simple common-source amplifier, including a first common-source amplifier tube and a second common-source amplifier tube respectively connected to the VIN terminal, the first common-source amplifier tube and the second common-source amplifier tube are connected in parallel; the feedback switch tube is connected to the second common-source amplifier tube, the feedback switch tube is also connected to the output node VO, the output node VO is also connected to the first common-source amplifier tube; the first common-source amplifier tube and the second common-source amplifier tube are both connected to the COM terminal.

5. The interface circuit with hysteresis and level shift characteristics according to claim 3, characterized in that: The common-source amplifier circuit is a common-source single-stage amplifier circuit with a source resistor Rs; It includes a first common-source amplifier tube connected to the VIN terminal, the first common-source amplifier tube is respectively connected to the output node VO and the feedback switch tube, the source of the first common-source amplifier tube is connected to the COM terminal through the resistor Rs, and the feedback switch tube is connected to the COM terminal.

6. An interface circuit with hysteresis and level shift characteristics according to claim 1, 4 or 5, characterized in that: The load circuit includes a first current mirror load tube PM1 arranged between the output node VO and the VCC power supply terminal, a second current mirror load tube PM2 and a hysteresis switch tube PM3 connected in parallel with the first current mirror load tube PM1, and the second current mirror load tube PM2 and the hysteresis switch tube PM3 are connected in sequence.

7. An interface circuit with hysteresis and level shift characteristics according to claim 1, 4 or 5, characterized in that: The load circuit includes a first load resistor RL1 and a second load resistor RL2 which are connected in sequence and are arranged between the output node VO and the VCC power supply terminal, and a hysteresis switch PM4 which is connected in parallel with the first load resistor RL1.

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