Assembly line analog-to-digital conversion chip with insensitive residual amplifier gain

Abstract

The invention relates to the technical field of integrated circuits, in particular to a residual amplifier gain insensitive assembly line analog-to-digital conversion chip which comprises a successive approximation analog-to-digital converter and a double-residual analog-to-digital converter module which are connected through a residual amplifier. The successive approximation analog-to-digital converter comprises a sampling switch and a capacitor array; the capacitor array adopts a structure of combining a binary capacitor array and an additional capacitor array; the double-residual analog-to-digital converter module comprises a plurality of double-residual analog-to-digital converters; the double-residual analog-to-digital converter is a residual self-generating double-residual analog-to-digital converter; the number of the double-residual analog-to-digital converters is N, and N is a positive integer greater than or equal to 2; the successive approximation analog-to-digital converter and each double-residual analog-to-digital converter are connected with the logic control unit. The assembly line analog-to-digital conversion chip with insensitive residual amplifier gain, provided by the invention, can be independently used as a sub-ADC in a multi-stage Pipeline ADC, and does not depend on a preceding stage sub-ADC.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a pipeline analog-to-digital conversion chip with insensitive residual amplifier gain. Background Art

[0002] Pipeline analog-to-digital converters (Pipeline ADCs) are widely used electronic components. Pipeline ADCs use residual amplifiers to cascade two or even multiple sub-ADCs. This structure reduces the requirements for noise and speed of each sub-ADC's comparator, and the overall cascade structure exhibits high-precision and high-speed characteristics, and is widely used in high-speed and high-precision scenarios. However, traditional Pipeline ADCs usually require residual amplifiers with precise gain to accurately amplify the residual voltages at each stage, so that the next-stage sub-ADC can perform high-precision analog-to-digital conversion on the residual. This will place high performance requirements on the residual amplifier, introduce large area and power consumption overhead, and greatly restrict the development and application of Pipeline ADCs towards higher precision and higher speed.

[0003] Successive approximation register (SAR) ADC is usually used as a sub-ADC in Pipeline ADC. Traditional SAR ADC usually requires an external reference voltage to measure the size of the residual, which requires high-precision amplification of the residual to achieve matching with the reference voltage. The use of a SAR-based dual-residual analog-to-digital converter avoids the requirement of precise amplification of the residual voltage. It uses the upper-level sub-ADC to generate an upward residual voltage and a downward residual voltage, and determines the voltage size by analyzing the relative size between the two residual voltages.

[0004] The prior art adopts non-binary capacitor interpolation technology in its dual residual analog-to-digital converter, and uses this dual residual analog-to-digital converter as the second stage in a two-stage Pipeline ADC structure to achieve insensitivity to the residual amplifier gain. However, the use of non-binary capacitor interpolation technology can only obtain the relative size relationship between the input dual residual voltages, and it is impossible to generate a new dual residual voltage based on the input dual residual voltage. In other words, the dual residual analog-to-digital converter of the prior art can only be used as the last-stage sub-ADC of the Pipeline ADC, and is usually only suitable for two-stage Pipeline ADC. However, the two-stage Pipeline ADC has a high number of conversion bits for each sub-ADC, which limits the overall conversion accuracy and speed of the Pipeline ADC. Summary of the invention

[0005] The embodiment of the present application provides a pipeline analog-to-digital conversion chip with an insensitive residual amplifier gain, which can be used independently as a sub-ADC in a multi-stage Pipeline ADC without relying on a previous-stage sub-ADC.

[0006] To solve the above technical problems, an embodiment of the present application provides a pipeline analog-to-digital conversion chip with insensitive residual amplifier gain, including: a successive approximation analog-to-digital converter and a dual residual analog-to-digital converter module; the successive approximation analog-to-digital converter and the dual residual analog-to-digital converter module are connected through a residual amplifier; the successive approximation analog-to-digital converter includes a sampling switch and a capacitor array; the capacitor array adopts a structure combining a binary capacitor array and an additional capacitor array; the dual residual analog-to-digital converter module includes multiple dual residual analog-to-digital converters; the dual residual analog-to-digital converter is a dual residual analog-to-digital converter with self-generated residuals; the number of dual residual analog-to-digital converters is N, and N is a positive integer greater than or equal to 2; the successive approximation analog-to-digital converter and each dual residual analog-to-digital converter are connected to a logic control unit.

[0007] In some exemplary embodiments, the successive approximation analog-to-digital converter is the first stage of the pipeline analog-to-digital conversion chip, which is used to determine the magnitude of the input double residual voltage and generate a new residual voltage.

[0008] In some exemplary embodiments, a dual-residue analog-to-digital converter is used to determine the relative size of the input residual and generate an upward residual and a downward residual for use by a next-stage circuit.

[0009] In some exemplary embodiments, a successive approximation analog-to-digital converter and N dual-residual analog-to-digital converters are connected in sequence to form an N+1-stage pipeline analog-to-digital conversion chip; the number of stages of each dual-residual analog-to-digital converter corresponds to the order of its input signals in all dual-residual analog-to-digital converters.

[0010] In some exemplary embodiments, the number of the dual-residue analog-to-digital converters is four; the successive approximation analog-to-digital converter and the four dual-residue analog-to-digital converters are sequentially connected to form a five-stage pipeline analog-to-digital conversion chip.

[0011] In some exemplary embodiments, the process of analog-to-digital conversion includes: a first-stage successive approximation analog-to-digital converter performs analog-to-digital conversion according to an input analog signal, and when its LSB bit is generated, samples the upper plate voltage as an upward residual voltage, recorded as Vres_U; further converts the capacitor array according to the positive and negative of Vres_U to generate a downward residual voltage, recorded as: Vres_L=LSB-Vres_U; a second-stage double residual analog-to-digital converter samples Vres_U and Vres_L generated by the previous stage, judges the relative size of the double residual and generates new upward residual and downward residual, recorded as: Vres_U1, Vres_L1, and transmits them to the third stage; the third-stage double residual analog-to-digital converter samples Vres generated by the previous stage s_U1 and Vres_L1, judge the relative size of the double residuals and generate new upward residuals and downward residuals, which are recorded as: Vres_U2, Vres_L2, and pass them to the fourth stage; the fourth-stage double-residue analog-to-digital converter samples Vres_U2 and Vres_L2 generated by the previous stage, judges the relative size of the double residuals and generates new upward residuals and downward residuals, which are recorded as: Vres_U3, Vres_L3, ​​and pass them to the fifth stage; the fifth-stage double-residue analog-to-digital converter samples Vres_U3 and Vres_L3 generated by the previous stage, judges the relative size of the double residuals and generates new double residuals, and processes the digital logic obtained at each stage to obtain the final digital signal.

[0012] In some exemplary embodiments, adjacent dual residual analog-to-digital converters are cascaded via residual amplifiers.

[0013] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0014] An embodiment of the present application provides a pipeline analog-to-digital conversion chip with insensitive residual amplifier gain, comprising: a successive approximation analog-to-digital converter and a dual residual analog-to-digital converter module; the successive approximation analog-to-digital converter and the dual residual analog-to-digital converter module are connected through a residual amplifier; the successive approximation analog-to-digital converter comprises a sampling switch and a capacitor array; the capacitor array adopts a structure combining a binary capacitor array and an additional capacitor array; the dual residual analog-to-digital converter module comprises a plurality of dual residual analog-to-digital converters; the dual residual analog-to-digital converter is a residual self-generated dual residual analog-to-digital converter; the number of dual residual analog-to-digital converters is N, and N is a positive integer greater than or equal to 2; the successive approximation analog-to-digital converter and each dual residual analog-to-digital converter are connected to a logic control unit.

[0015] The present application provides a multi-stage pipeline analog-to-digital conversion chip based on a residual self-generated dual residual analog-to-digital converter. The residual self-generated dual residual analog-to-digital converter realizes a multi-stage Pipeline ADC structure that is insensitive to the gain of the residual amplifier by adopting a unique capacitor charge sharing method. The present application adopts a structure combining a binary capacitor array and an additional capacitor array to realize the judgment of the size of the input dual residual voltage and the generation of a new residual voltage. Therefore, the present application is more suitable for a multi-stage Pipeline ADC than the prior art. Any sub-ADC of the Pipeline ADC can adopt the proposed residual self-generated dual residual analog-to-digital converter, and is insensitive to the gain of the residual amplifiers at each stage. Compared with a two-stage Pipeline ADC, a multi-stage Pipeline ADC can achieve higher precision and higher speed analog-to-digital conversion due to a lower number of conversion bits per stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0017] Figure 1 A schematic diagram of the structure of a pipeline analog-to-digital conversion chip (Pipeline ADC) with insensitive residual amplifier gain provided in one embodiment of the present application.

[0018] Figure 2 A 17-bit five-stage Pipeline ADC system structure is provided in an embodiment of the present application.

[0019] FIG. 3A to FIG. 3D The present invention provides a dual-residue analog-to-digital converter with 3-bit residual self-generation and conversion steps.

[0020] FIG. 4A to FIG. 4D Two special residual conversion steps of a dual residual analog-to-digital converter with self-generated 3-bit residual provided in an embodiment of the present application.

[0021] Figure 5 A 17-bits five-stage Pipeline ADC simulation model provided in an embodiment of the present application.

[0022] Figure 6 The simulation results of a 17-bit five-stage Pipeline ADC provided in an embodiment of the present application.

[0023] Figure 7 The invention discloses an application of a residual sub-generated ADC in Pipeline and Time-Interleaved. DETAILED DESCRIPTION

[0024] As can be seen from the background technology, the existing dual residual analog-to-digital converter can only be used as the last stage sub-ADC of the Pipeline ADC, and is usually only applicable to a two-stage Pipeline ADC. However, the two-stage Pipeline ADC has a high conversion bit number for each stage of the sub-ADC, which limits the overall conversion accuracy and speed of the Pipeline ADC.

[0025] Traditional SAR ADC usually requires an external reference voltage to measure the size of the residual, which requires high-precision amplification of the residual to achieve matching with the reference voltage. The use of a SAR-based dual-residual analog-to-digital converter avoids the requirement for precise amplification of the residual voltage. The related art uses a dual-residual analog-to-digital converter in the second stage of its two-stage Pipeline ADC, and uses a non-binary capacitor interpolation conversion array to determine the relative size of the input upward residual voltage and downward residual voltage, and finally quantizes the analog signal. Another related art proposes a two-stage Pipeline ADC in which the first stage uses a 6-bit SAR structure to generate upward and downward residuals; the second stage uses a 7-bit dual-residual analog-to-digital converter, and uses an open-loop calibration-free amplifier to amplify the upward residual voltage and the downward residual voltage generated by the first stage, respectively, and uses a floating capacitor switch conversion array to determine the relative size of the upward residual voltage and the downward residual voltage, and finally obtains the quantized value of the voltage.

[0026] The prior art adopts non-binary capacitor interpolation technology in its dual residual analog-to-digital converter, and uses this dual residual analog-to-digital converter as the second stage in the two-stage Pipeline ADC structure to achieve insensitivity to the residual amplifier gain. However, the use of non-binary capacitor interpolation technology can only obtain the relative size relationship between the input dual residual voltages, and it is impossible to generate a new dual residual voltage based on the input dual residual voltage. For example, the second-stage dual residual analog-to-digital converter of the Pipeline ADC structure proposed in a related art must rely on the first-stage sub-ADC to obtain the dual residual voltage. This dual residual analog-to-digital converter needs to rely on the previous stage, and therefore cannot be used as an independent sub-module. Therefore, the dual residual analog-to-digital converter mentioned in the related art can only be used as the last-stage sub-ADC of the Pipeline ADC, and is usually only suitable for two-stage Pipeline ADC. However, the two-stage Pipeline ADC has a high number of conversion bits per sub-ADC, which limits the overall conversion accuracy and speed of the Pipeline ADC.

[0027] To solve the above technical problems, the embodiment of the present application provides a pipeline analog-to-digital conversion chip with insensitive residual amplifier gain, including: a successive approximation analog-to-digital converter and a dual residual analog-to-digital converter module; the successive approximation analog-to-digital converter and the dual residual analog-to-digital converter module are connected through a residual amplifier; the successive approximation analog-to-digital converter includes a sampling switch and a capacitor array; the capacitor array adopts a structure combining a binary capacitor array and an additional capacitor array; the dual residual analog-to-digital converter module includes a plurality of dual residual analog-to-digital converters; the dual residual analog-to-digital converter is a dual residual analog-to-digital converter with self-generated residuals; the number of dual residual analog-to-digital converters is N, and N is a positive integer greater than or equal to 2; the successive approximation analog-to-digital converter and each dual residual analog-to-digital converter are connected to a logic control unit. The pipeline analog-to-digital conversion chip with insensitive residual amplifier gain provided by the present application can be used independently as a sub-ADC in a multi-stage Pipeline ADC, and does not rely on the previous sub-ADC.

[0028] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0029] refer to Figure 1 The embodiment of the present application provides a residual amplifier gain-insensitive pipeline analog-to-digital conversion chip, including: a successive approximation analog-to-digital converter (SAR ADC) and a dual residual analog-to-digital converter module; the successive approximation analog-to-digital converter and the dual residual analog-to-digital converter module are connected through a residual amplifier (RA); the successive approximation analog-to-digital converter includes a sampling switch and a capacitor array; the capacitor array adopts a structure combining a binary capacitor array and an additional capacitor array; the dual residual analog-to-digital converter module includes a plurality of dual residual analog-to-digital converters (Dual residue ADC); the dual residual analog-to-digital converter is a residual self-generated dual residual analog-to-digital converter; the number of dual residual analog-to-digital converters is N, and N is a positive integer greater than or equal to 2; the successive approximation analog-to-digital converter and each dual residual analog-to-digital converter are connected to a logic control unit (Control logic).

[0030] In some embodiments, adjacent dual residual analog-to-digital converters are cascaded via residual amplifiers.

[0031] like Figure 2 As shown, in some embodiments, a successive approximation analog-to-digital converter (SAR ADC) is the first stage of a pipeline analog-to-digital conversion chip, which is used to determine the magnitude of an input dual residual voltage and generate a new residual voltage.

[0032] In some embodiments, a dual residue analog-to-digital converter (Dual residue ADC) is used to determine the relative size of the input residual and generate an upward residual and a downward residual for use by the next stage circuit.

[0033] In some embodiments, a successive approximation ADC and N dual-residual ADCs are connected in sequence to form an N+1-stage pipeline ADC chip; the number of stages of each dual-residual ADC corresponds to the order of its input signals in all dual-residual ADCs.

[0034] like Figure 2 As shown, in some embodiments, the number of dual-residue analog-to-digital converters is four; the successive approximation analog-to-digital converter and the four dual-residue analog-to-digital converters are connected in sequence to form a five-stage pipeline analog-to-digital conversion chip.

[0035] In some embodiments, the process of analog-to-digital conversion includes: a first-stage successive approximation analog-to-digital converter performs analog-to-digital conversion according to an input analog signal, and when its LSB bit is generated, samples the upper plate voltage as an upward residual voltage, recorded as Vres_U; further converts the capacitor array according to the positive and negative of Vres_U to generate a downward residual voltage, recorded as: Vres_L=LSB-Vres_U; a second-stage double residual analog-to-digital converter samples Vres_U and Vres_L generated by the previous stage, judges the relative size of the double residual and generates new upward residual and downward residual, recorded as: Vres_U1, Vres_L1, and transmits them to the third stage; the third-stage double residual analog-to-digital converter samples Vres generated by the previous stage _U1 and Vres_L1, judge the relative size of the double residuals and generate new upward residuals and downward residuals, which are recorded as: Vres_U2, Vres_L2, and pass them to the fourth stage; the fourth-stage double-residue analog-to-digital converter samples Vres_U2 and Vres_L2 generated by the previous stage, judges the relative size of the double residuals and generates new upward residuals and downward residuals, which are recorded as: Vres_U3, Vres_L3, ​​and pass them to the fifth stage; the fifth-stage double-residue analog-to-digital converter samples Vres_U3 and Vres_L3 generated by the previous stage, judges the relative size of the double residuals and generates new double residuals, and processes the digital logic obtained at each stage to obtain the final digital signal.

[0036] The present application proposes a dual residual analog-to-digital converter that can be applied to the residual self-generation of each sub-ADC in a multi-stage Pipeline ADC, with the focus on a structure in which a binary capacitor array is used in combination with an additional capacitor array. This structure can obtain a new dual residual voltage for the next stage by only performing an additional operation after judging the relative magnitude of the input dual residual voltage. This structure can be applied to multi-stage Pipeline ADC and time-interleaved ADC by simply and low-costly configuring the capacitor array according to the resolution.

[0037] The residual amplifier gain-insensitive pipeline analog-to-digital conversion chip provided by the present application is introduced in detail below through specific embodiments.

[0038] Take the 17-bit five-stage Pipeline ADC as an example. Figure 2 As shown, the first-stage SAR ADC performs analog-to-digital conversion according to the input analog signal. When the least significant bit (LSB) is generated, the upper plate voltage is sampled as the upward residual voltage Vres_U, and the capacitor array is further converted according to the positive and negative of Vres_U to generate the downward residual voltage Vres_L=LSB-Vres_U. The second-stage 3-bit residual self-generated dual residual analog-to-digital converter samples the upward residual voltage Vres_U and the downward residual voltage Vres_L generated by the previous stage, judges the relative size of the dual residuals and generates new upward residual Vres_U1 and downward residual Vres_L1, and transmits them to the third stage. The following stages perform the same operation, and process the digital logic obtained at each stage to obtain the final digital signal.

[0039] FIG. 3A to FIG. 3D The residual self-generation process of the proposed double residual analog-to-digital converter is shown in Figure 2. When the upward residual Vres_U>0 and the downward residual Vres_L<0 generated by the input analog signal, the residual distribution is as follows: FIG. 3A to FIG. 3D As shown, similar to SAR ADC, the conversion capacitor array is used to compare the relative size of the residual. When (Vres_U+3·Vres_L) / 4>0, the lower two binary digital signals are 11; continue to increase the negative residual, when (Vres_U+7·Vres_L) / 8<0, the three binary digital signals are 011.

[0040] And there is an upward residual Vres_U1 = (Vres_U + 7·Vres_L) / 8, and at this time the downward residual Vres_L1 = (Vres_U + 3·Vres_L) / 4. This residual self-generated double residual analog-to-digital converter only needs to receive the double residual from the SAR ADC once, and then can generate the double residual independently.

[0041] FIG. 4A to FIG. 4D There are several special residual self-generation processes for the double residual analog-to-digital converter for residual self-generation. Figure 4A and Figure 4D In, Vres_L1 = Vres_L; in Figure 4B and Figure 4C In these cases, the generation of new residuals comes from resampling the input residuals.

[0042] This application proposes for the first time a dual residual analog-to-digital converter with self-generated residuals. By using a binary capacitor array in combination with an additional capacitor array, the upward residual and the downward residual can be independently generated for use by the next stage circuit after the relative size of the input residual is obtained. In a multi-stage Pipeline ADC structure, this dual residual analog-to-digital converter with self-generated residuals can be used as an independent submodule to implement each stage of sub-ADC, effectively avoiding the influence of the residual amplifier gain in the Pipeline ADC structure on the accuracy of the Pipeline ADC. At the same time, this structure can also be further expanded in time-interleaved ADCs.

[0043] The residual amplifier gain-insensitive pipeline analog-to-digital conversion chip provided in the present application has been tested, simulated and used. Figure 5 A 17-bit five-stage Pipeline ADC simulation model is provided for an embodiment of the present application. In the simulation experiment, the first-stage sub-ADC of the present application uses a 5-bit SAR ADC to generate double residuals, and the remaining four-stage sub-ADCs all use the double residual analog-to-digital converters with self-generated residuals proposed in the present application. Figure 6 The simulation results of a 17-bit five-stage Pipeline ADC provided in an embodiment of the present application. After simulation verification, the Pipeline ADC finally realized a 17-bit 1GHz five-stage Pipeline ADC with a signal-to-noise ratio of 97.53dB. Changing the gain of the residual amplifier in the Pipeline ADC has no effect on its signal-to-noise ratio result. This residual self-generated dual residual analog-to-digital converter realizes the insensitivity to the gain of the multi-stage Pipeline ADC residual amplifier.

[0044] Compared with the prior art, the residual amplifier gain-insensitive pipeline analog-to-digital conversion chip provided by the present application has the following advantages:

[0045] The prior art uses a dual residual analog-to-digital converter as the second-stage structure in a two-stage Pipeline ADC structure to achieve insensitivity to the residual amplifier gain. However, the dual residual analog-to-digital converter proposed in the prior art can only obtain the relative size relationship between the input dual residual voltages, and cannot generate a new dual residual voltage based on the input dual residual voltage, resulting in it being able to serve only as the last-stage sub-ADC of the Pipeline ADC, and not as a sub-ADC at each stage in the multi-stage Pipeline ADC. The present application utilizes a combination of a binary capacitor array and an additional capacitor array so that the dual residual analog-to-digital converter can independently generate an upward residual voltage and a downward residual voltage based on the input dual residual voltage and provide them to the next stage circuit for use, i.e., a residual self-generated dual residual analog-to-digital converter. Figure 7 The present invention provides an application of the residual sub-generated ADC in Pipeline and Time-Interleaved. This structure, when applied to a multi-stage Pipeline ADC, can greatly eliminate the influence of the gain of each stage residual amplifier on the accuracy of the Pipeline ADC.

[0046] Based on the above technical scheme, an embodiment of the present application provides a pipeline analog-to-digital conversion chip with insensitive residual amplifier gain, including: a successive approximation analog-to-digital converter and a dual residual analog-to-digital converter module; the successive approximation analog-to-digital converter and the dual residual analog-to-digital converter module are connected through a residual amplifier; the successive approximation analog-to-digital converter includes a sampling switch and a capacitor array; the capacitor array adopts a structure combining a binary capacitor array and an additional capacitor array; the dual residual analog-to-digital converter module includes multiple dual residual analog-to-digital converters; the dual residual analog-to-digital converter is a residual self-generated dual residual analog-to-digital converter; the number of dual residual analog-to-digital converters is N, and N is a positive integer greater than or equal to 2; the successive approximation analog-to-digital converter and each dual residual analog-to-digital converter are connected to a logic control unit.

[0047] The present application provides a multi-stage pipeline analog-to-digital conversion chip based on a residual self-generated dual residual analog-to-digital converter. The residual self-generated dual residual analog-to-digital converter realizes a multi-stage Pipeline ADC structure that is insensitive to the gain of the residual amplifier by adopting a unique capacitor charge sharing method. The present application adopts a structure combining a binary capacitor array and an additional capacitor array to realize the judgment of the size of the input dual residual voltage and the generation of a new residual voltage. Therefore, the present application is more suitable for a multi-stage Pipeline ADC than the prior art. Any sub-ADC of the Pipeline ADC can adopt the proposed residual self-generated dual residual analog-to-digital converter, and is insensitive to the gain of the residual amplifiers at each stage. Compared with a two-stage Pipeline ADC, a multi-stage Pipeline ADC can achieve higher precision and higher speed analog-to-digital conversion due to a lower number of conversion bits per stage.

[0048] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application, so the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A residual amplifier gain-insensitive pipeline analog-to-digital conversion chip, characterized in that: include: Successive approximation analog-to-digital converter and dual residual analog-to-digital converter modules; The successive approximation analog-to-digital converter and the dual residual analog-to-digital converter module are connected via a residual amplifier; The successive approximation analog-to-digital converter includes a sampling switch and a capacitor array; the capacitor array adopts a structure combining a binary capacitor array and an additional capacitor array; The dual-residual analog-to-digital converter module includes a plurality of dual-residual analog-to-digital converters; The dual residual analog-to-digital converter is a dual residual analog-to-digital converter with self-generated residuals; The number of the dual residual analog-to-digital converters is N, where N is a positive integer greater than or equal to 2; The successive approximation analog-to-digital converter and each dual-residual analog-to-digital converter are connected to a logic control unit.

2. The residual amplifier gain-insensitive pipeline analog-to-digital conversion chip according to claim 1, characterized in that: The successive approximation analog-to-digital converter is the first stage of the pipeline analog-to-digital conversion chip, and is used to determine the magnitude of the input double residual voltage and generate a new residual voltage.

3. The residual amplifier gain-insensitive pipeline analog-to-digital conversion chip according to claim 1, characterized in that: The dual-residue analog-to-digital converter is used to determine the relative size of the input residual and generate an upward residual and a downward residual for use by the next stage circuit.

4. The residual amplifier gain-insensitive pipeline analog-to-digital conversion chip according to claim 1, characterized in that: The successive approximation analog-to-digital converter and N dual-residual analog-to-digital converters are connected in sequence to form an N+1-stage pipeline analog-to-digital conversion chip; the stage number of each dual-residual analog-to-digital converter corresponds to the order of its input signal in all dual-residual analog-to-digital converters.

5. The residual amplifier gain-insensitive pipeline analog-to-digital conversion chip according to claim 4, characterized in that: The number of the dual-residue analog-to-digital converters is four; the successive approximation analog-to-digital converter and the four dual-residue analog-to-digital converters are connected in sequence to form a five-stage pipeline analog-to-digital conversion chip.

6. The residual amplifier gain-insensitive pipeline analog-to-digital conversion chip according to claim 5, characterized in that: The process of analog-to-digital conversion includes: the first-stage successive approximation analog-to-digital converter performs analog-to-digital conversion according to the input analog signal, and when its LSB bit is generated, the upper plate voltage is sampled as the upward residual voltage, recorded as Vres_U; according to the positive and negative of Vres_U, the capacitor array is further converted to generate a downward residual voltage, recorded as: Vres_L = LSB-Vres_U; The second-stage double-residue analog-to-digital converter samples Vres_U and Vres_L generated by the previous stage, determines the relative size of the double residuals and generates new upward residuals and downward residuals, which are recorded as: Vres_U1, Vres_L1, and pass them to the third stage; The third-stage double-residual analog-to-digital converter samples Vres_U1 and Vres_L1 generated by the previous stage, determines the relative size of the double residuals and generates new upward residuals and downward residuals, which are recorded as: Vres_U2, Vres_L2, and pass them to Level 4; The fourth-stage double-residue analog-to-digital converter samples Vres_U2 and Vres_L2 generated by the previous stage, determines the relative size of the double residuals and generates new upward residuals and downward residuals, which are recorded as: Vres_U3, Vres_L3, ​​and passes them to Level 5; The fifth-stage double-residue analog-to-digital converter samples Vres_U3 and Vres_L3 generated by the previous stage, determines the relative size of the double residuals and generates new double residuals, and processes the digital logic obtained at each stage to obtain the final digital signal.

7. The residual amplifier gain-insensitive pipeline analog-to-digital conversion chip according to claim 1, characterized in that: Adjacent dual residual analog-to-digital converters are cascaded via residual amplifiers.

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