Low-voltage sampling device and analog-to-digital converter

Abstract

The invention discloses a low-voltage sampling device and an analog-to-digital converter, and relates to the field of analog-to-digital conversion, and the low-voltage sampling device comprises a capacitor module, a charging and discharging control module, a sampling voltage holding module and an operational amplifier module. Wherein the input end of the charge-discharge control module is connected with a power supply, the output end of the charge-discharge control module is connected with a grounding end, and a first control interface of the charge-discharge control module is connected with the capacitor module. And the sampling voltage holding module comprises two NMOS (N-channel Metal Oxide Semiconductor) tubes. The operational amplifier module inputs the voltage of an input signal to the back gate of the first NMOS tube and the back gate of the second NMOS tube in a unit negative feedback mode. The charging and discharging control module charges the capacitor module to be the same as the power supply voltage when the clock signal is in the first phase, stops charging the capacitor module when the current clock signal is in the second phase, and enables the voltage between the grid electrode and the source electrode of the two NMOS tubes to be consistent with the power supply voltage, thereby reducing the nonlinearity of the sampling signal, and improving the sampling precision. The sampling precision is improved.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital conversion, and in particular to a low-voltage sampling device and an analog-to-digital converter. Background Art

[0002] The sampling circuit is a key module in the design of ADC (Analog Digital Converter). The sampling circuit can also be called a sampling switch. The linearity of the sampling switch seriously affects the dynamic performance of the ADC. The process of converting continuous input signals into DC signals in the ADC is called sampling and holding, which is achieved by controlling the closing and closing of the sampling switch. However, the sampling circuit currently used has a problem that the on-resistance of the input signal changes with the input signal, causing the on-resistance of the sampling switch to change, which in turn reduces the linearity of the switch and affects the sampling accuracy. Summary of the invention

[0003] In view of the above problems, the present application provides a low-voltage sampling device and an analog-to-digital converter to achieve the purpose of improving the linearity and sampling accuracy of the sampling signal. The specific scheme is as follows:

[0004] The first aspect of the present application provides a low-voltage sampling device, comprising: a capacitor module, a charge and discharge control module, a sampling voltage holding module and an operational amplifier module;

[0005] The input end of the charge and discharge control module is connected to a power supply, the output end of the charge and discharge control module is connected to a ground end, and the first control interface of the charge and discharge control module is connected to the capacitor module;

[0006] The sampling voltage holding module includes: two NMOS tubes, the source of the first NMOS tube is connected to the drain of the second NMOS tube as a signal input terminal, the drain of the first NMOS tube is connected to a control terminal of the second control interface of the charge and discharge control module, the gate of the first NMOS tube and the gate of the second NMOS tube are respectively connected to another control terminal of the second control interface, and the source of the second NMOS tube is used as a signal output terminal;

[0007] The operational amplifier module inputs the voltage of the input signal to the back gate of the first NMOS tube and the back gate of the second NMOS tube in the form of unit negative feedback;

[0008] The charge-discharge control module charges the capacitor module to the same voltage as the first voltage of the power supply when the current clock signal is in the first phase, and makes the voltage of the signal output end the same as the voltage input from the signal input end by the previous clock signal, wherein the previous clock signal is adjacent to the current clock signal and earlier than the current clock signal;

[0009] When the current clock signal is in the second phase, the charge and discharge control module stops charging the capacitor module, and makes the second voltage and the third voltage respectively the same as the first voltage, and the voltage of the signal output end is the same as the voltage currently input to the signal input end, the second voltage is the voltage between the gate and the source of the first NMOS tube, the second voltage is the voltage between the gate and the source of the second NMOS tube, and the first phase and the second phase are opposite.

[0010] In a possible implementation, the operational amplifier module includes: an operational amplifier, a first input terminal of the operational amplifier is connected to an input signal, a second input terminal of the operational amplifier is connected to an output terminal of the operational amplifier, and the output terminal of the operational amplifier is respectively connected to a back gate of the first NMOS tube and a back gate of the second NMOS tube.

[0011] In a possible implementation, the capacitor module includes: at least one capacitor, and the at least one capacitor is connected to the first control interface in parallel.

[0012] In a possible implementation, the charge and discharge control module includes: a first switch submodule and a second switch submodule;

[0013] The input end of the first switch submodule is connected in series with the capacitor module, the output end of the first switch submodule is connected with the ground end, and the control end of the first switch submodule is connected with a clock signal;

[0014] The first input end of the second switch submodule is connected to the power supply, the first control end of the second switch submodule is connected to the capacitor module, the second control end of the second switch submodule is connected to the input end of the first switch submodule, the third control end of the second switch submodule is connected to the drain of the first NMOS tube, the fourth control end of the second switch submodule is connected to the gate of the first NMOS tube, the second input end of the second switch submodule is connected to the clock signal, and the third input end of the second switch submodule is connected to the inverted signal of the clock signal.

[0015] In a possible implementation, the second switch submodule includes: a first switch unit, a first control unit, a second switch unit, and a second control unit;

[0016] The input end of the first switch unit is connected to the power supply, the output end of the first switch unit is connected to the capacitor module, and the control end of the second switch unit is connected to a common point;

[0017] The input terminal of the first control unit is connected to the common point, the output terminal of the first control unit is connected to the ground terminal, the first control terminal of the first control unit is connected to the power supply, and the second control terminal of the first control unit is connected to the clock signal;

[0018] The input end of the second switch unit is connected to the common point, the output end of the second switch unit is connected to the capacitor module, and the control end of the second switch unit is connected to the first input end of the second control unit;

[0019] The first control terminal of the second control unit is connected to the common point, the second input terminal of the second control unit is connected to the power supply, the second control terminal of the second control unit is connected to the inverted signal of the clock signal, and the output terminal of the second control unit is connected to the input terminal of the first switch submodule;

[0020] The gate of the first MOS transistor is connected to the common point, and the drain of the first MOS transistor is connected to the input end of the first switch submodule.

[0021] In a possible implementation, the first control unit includes: a third NMOS tube and a fourth NMOS tube, the gate of the third NMOS tube is connected to the power supply, the drain of the third NMOS tube is connected to the common point, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the clock signal, and the source of the fourth NMOS tube is connected to the ground terminal.

[0022] In a possible implementation, the second control unit includes: a fifth NMOS tube, a sixth NMOS tube and a first PMOS tube, the drain of the fifth NMOS tube is connected to the control end of the second switch unit, the source of the fifth NMOS tube is connected to the input end of the first switch submodule, and the gate of the fifth NMOS tube is connected to the common point;

[0023] The drain of the sixth NMOS tube is connected to the control end of the second switch unit, the source of the sixth NMOS tube is connected to the input end of the first switch submodule, and the gate of the sixth NMOS tube is connected to the inverted signal of the clock signal;

[0024] The source of the first PMOS tube is connected to the power supply, the gate of the first PMOS tube is connected to the inverted signal of the clock signal, and the drain of the first PMOS tube is connected to the drain of the sixth NMOS tube.

[0025] In a possible implementation, the first switch unit includes: a second PMOS tube, a drain of the second PMOS tube is connected to the capacitor module, a source of the second PMOS tube is connected to the power supply, and a gate of the second PMOS tube is connected to the common point.

[0026] In a possible implementation, the second switch unit includes: a third PMOS tube, the drain of the third PMOS tube is connected to the capacitor module, the source of the third PMOS tube is connected to the common point, and the gate of the third PMOS tube is connected to the drain of the fifth NMOS tube.

[0027] A second aspect of the present application provides an analog-to-digital converter, comprising the low-voltage sampling device described in the first aspect or any possible implementation of the first aspect.

[0028] By means of the above technical scheme, the low-voltage sampling device provided by the present application includes: a capacitor module, a charge and discharge control module, a sampling voltage holding module and an operational amplifier module. The input end of the charge and discharge control module is connected to the power supply, the output end of the charge and discharge control module is connected to the ground end, and the first control interface of the charge and discharge control module is connected to the capacitor module. The sampling voltage holding module includes: two NMOS tubes, the source of the first NMOS tube is connected to the drain of the second NMOS tube as a signal input end, the drain of the first NMOS tube is connected to a control end of the second control interface of the charge and discharge control module, the gate of the first NMOS tube is connected to the other control of the second control interface, and the source of the second NMOS tube is used as a signal output end. The operational amplifier module inputs the voltage of the input signal to the back gate of the first NMOS tube and the back gate of the second NMOS tube in the form of unit negative feedback. When the current clock signal is in the first phase, the charge and discharge control module charges the capacitor module to the same voltage as the first voltage of the power supply, and makes the voltage of the signal output end the same as the voltage input from the signal input end of the previous clock signal; when the current clock signal is in the second phase, the charge and discharge control module stops charging the capacitor module, and makes the second voltage and the third voltage respectively the same as the first voltage, and the voltage of the signal output end the same as the voltage currently input from the signal input end, the second voltage is the voltage between the gate and source of the first NMOS tube, and the second voltage is the voltage between the gate and source of the second NMOS tube. When the sampling voltage holding module samples the input signal, the voltage between the gate and source of the two NMOS tubes is kept consistent with the power supply voltage, which is independent of the input signal, effectively reducing the nonlinearity of the sampling signal and improving the sampling accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0030] Figure 1 A structural diagram of a low-pressure sampling device provided for this application;

[0031] Figure 2 Another structural diagram of a low-pressure sampling device provided by the present application;

[0032] Figure 3 A specific circuit schematic diagram of the low-voltage sampling device provided for this application;

[0033] Figure 4 A circuit schematic diagram of an operational amplifier module is provided for this application. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0035] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0036] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0037] Since there are various non-ideal factors in the sampling switch, this will affect the accuracy of the sampled signal, thereby introducing nonlinear errors. The error of the sampling signal directly affects the accuracy of the entire ADC (Analog-to-Digital Converter). Therefore, in the process of designing ADC, the design of the sampling switch is an extremely important part, and a switch with less impact on accuracy should be selected. The purpose of sampling is to sample the input signal according to a fixed gain. Nonlinearity means that the input signal cannot be sampled according to a fixed gain; because the on-resistance of the input signal changes with the input signal, it affects the on-resistance of the sampling switch. This leads to a decrease in the linearity of the sampling, resulting in a decrease in the accuracy of the sampled signal.

[0038] To solve the above problems, refer to Figure 1 As shown, the present application provides a low-voltage sampling device, including: a capacitor module, a charge and discharge control module, a sampling voltage holding module and an operational amplifier module;

[0039] The input end of the charge and discharge control module is connected to the power supply, the output end of the charge and discharge control module is connected to the ground end, and the first control interface of the charge and discharge control module is connected to the capacitor module;

[0040] The sampling voltage holding module includes: two NMOS tubes, the source of the first NMOS tube is connected to the drain of the second NMOS tube as a signal input terminal, the drain of the first NMOS tube is connected to a control terminal of the second control interface of the charge and discharge control module, the gate of the first NMOS tube and the gate of the second NMOS tube are respectively connected to another control terminal of the second control interface, and the source of the second NMOS tube is used as a signal output terminal;

[0041] The operational amplifier module inputs the voltage of the input signal to the back gate of the first NMOS tube and the back gate of the second NMOS tube in the form of unit negative feedback;

[0042] The charge and discharge control module charges the capacitor module to the same voltage as the first voltage of the power supply when the current clock signal is in the first phase, and makes the voltage of the signal output end the same as the voltage input from the signal input end by the previous clock signal, and the previous clock signal is adjacent to the current clock signal and earlier than the current clock signal;

[0043] When the current clock signal is in the second phase, the charge and discharge control module stops charging the capacitor module, and makes the second voltage and the third voltage respectively the same as the first voltage, and the voltage of the signal output end is the same as the voltage input at the current signal input end, the second voltage is the voltage between the gate and the source of the first NMOS tube, the second voltage is the voltage between the gate and the source of the second NMOS tube, and the first phase and the second phase are opposite.

[0044] Specifically, the specific working principle of the low-voltage sampling device is that when the clock signal is at a high level, the charge and discharge control module controls the connection circuit between the power supply, the ground terminal and the capacitor module to be turned on, charges the capacitor in the capacitor module to the same voltage as the power supply, and controls the first NMOS tube to be in a disconnected state, so that the sampling output signal of the second NMOS tube maintains the previously sampled voltage. When the clock signal is at a low level, the charge and discharge control module controls the connection circuit between the power supply, the ground terminal and the capacitor module to be disconnected, and controls the first NMOS tube and the second NMOS tube to be in a conductive state, and the second NMOS tube starts to sample the input signal, so that the output signal is the same as the input signal, and at this time, the voltage between the gate and the source of the first NMOS tube and the second NMOS tube is the same as the power supply voltage, which is independent of the input signal, thereby reducing the nonlinearity of the sampling circuit, and at the same time, it can reduce the area of ​​the first NMOS tube and the second NMOS tube.

[0045] The area here refers to the product of the length and width of the channel in the NMOS tube, where the channel width refers to the lateral size of the conductive channel in the MOS tube, that is, the length of the current flow path in the lateral direction. The larger the channel width, the more current can pass through at the same time. The channel length refers to the size of the conductive channel in the vertical direction, that is, the length of the current flow path in the vertical direction. The channel length affects the switching speed and frequency response of the MOS tube. A shorter channel length can provide faster switching speeds and higher operating frequencies. By ensuring that the on-resistance is small, the channel area is further reduced.

[0046] In addition, by connecting the input signal of the operational amplifier module to the back gates of the first NMOS tube and the second NMOS tube in the form of negative feedback, the liner effect can be effectively eliminated, and the linearity is further improved.

[0047] In one possible implementation, the operational amplifier module includes: an operational amplifier, a first input terminal of the operational amplifier is connected to an input signal, a second input terminal of the operational amplifier is connected to an output terminal of the operational amplifier, and the output terminal of the operational amplifier is respectively connected to a back gate of a first NMOS tube and a back gate of a second NMOS tube.

[0048] Specifically, refer to Figure 3 The operational amplifier opm1 shown in the figure makes the back gate of the second NMOS tube NM2 equal to Vi (input signal), thereby eliminating the lining effect and improving the linearity. The circuit principle of the operational amplifier is referred to in Figure 4As shown, M11 and M12 are the differential input pair of the op amp, PM11 / PM12 and PM13 / PM14 form a current mirror load structure, M13 / M14 form an N-type current mirror load, C11 is a load capacitor, which stabilizes the loop and reduces ripple, M15 is a tail current source, and VB is a fixed voltage bias to enable M15 to provide a stable current.

[0049] It is understandable that those skilled in the art may also use operational amplifiers of other models and structures to eliminate the liner effect, and this is not limited here.

[0050] In some possible implementations, the capacitor module may include: at least one capacitor connected to the first control interface in parallel.

[0051] Specifically, the number and connection method of the capacitors can be adjusted and selected according to the charging time requirement that needs to be met during the sampling process, and will not be described in detail here. Generally, only one capacitor is used.

[0052] Reference Figure 2 As shown, in a possible implementation, the charge and discharge control module may include: a first switch submodule and a second switch submodule;

[0053] The input end of the first switch submodule is connected in series with the capacitor module, the output end of the first switch submodule is connected with the ground end, and the control end of the first switch submodule is connected with the clock signal;

[0054] The first input end of the second switch submodule is connected to the power supply, the first control end of the second switch submodule is connected to the capacitor module, the second control end of the second switch submodule is connected to the input end of the first switch submodule, the third control end of the second switch submodule is connected to the drain of the first NMOS tube, the fourth control end of the second switch submodule is connected to the gate of the first NMOS tube, the second input end of the second switch submodule is connected to the clock signal, and the third input end of the second switch submodule is connected to the inverted signal of the clock signal.

[0055] Wherein, the second switch submodule includes: a first switch unit, a first control unit, a second switch unit and a second control unit;

[0056] The input end of the first switch unit is connected to the power supply, the output end of the first switch unit is connected to the capacitor module, and the control end of the second switch unit is connected to the common point;

[0057] An input terminal of the first control unit is connected to a common point, an output terminal of the first control unit is connected to a ground terminal, a first control terminal of the first control unit is connected to a power source, and a second control terminal of the first control unit is connected to a clock signal;

[0058] An input end of the second switch unit is connected to the common point, an output end of the second switch unit is connected to the capacitor module, and a control end of the second switch unit is connected to a first input end of the second control unit;

[0059] The first control terminal of the second control unit is connected to the common point, the second input terminal of the second control unit is connected to the power supply, the second control terminal of the second control unit is connected to the inverted signal of the clock signal, and the output terminal of the second control unit is connected to the input terminal of the first switch submodule;

[0060] The gate of the first MOS tube is connected to the common point, and the drain of the first MOS tube is connected to the input end of the first switch submodule.

[0061] Specifically, the first control unit includes: a third NMOS tube and a fourth NMOS tube, the gate of the third NMOS tube is connected to the power supply, the drain of the third NMOS tube is connected to the common point, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the clock signal, and the source of the fourth NMOS tube is connected to the ground terminal.

[0062] The second control unit includes: a fifth NMOS tube, a sixth NMOS tube and a first PMOS tube, the drain of the fifth NMOS tube is connected to the control end of the second switch unit, the source of the fifth NMOS tube is connected to the input end of the first switch submodule, and the gate of the fifth NMOS tube is connected to the common point;

[0063] The drain of the sixth NMOS tube is connected to the control end of the second switch unit, the source of the sixth NMOS tube is connected to the input end of the first switch submodule, and the gate of the sixth NMOS tube is connected to the inverted signal of the clock signal;

[0064] The source of the first PMOS tube is connected to the power supply, the gate of the first PMOS tube is connected to the inverted signal of the clock signal, and the drain of the first PMOS tube is connected to the drain of the sixth NMOS tube.

[0065] The first switch unit includes: a second PMOS tube, a drain of the second PMOS tube is connected to the capacitor module, a source of the second PMOS tube is connected to the power supply, and a gate of the second PMOS tube is connected to the common point.

[0066] The second switch unit includes: a third PMOS tube, the drain of the third PMOS tube is connected to the capacitor module, the source of the third PMOS tube is connected to the common point, and the gate of the third PMOS tube is connected to the drain of the fifth NMOS tube.

[0067] Corresponding reference Figure 3As shown, the capacitor module includes: capacitor C1, the first switch unit includes: PM1, i.e., the second PMOS tube, and the second switch unit includes: PM2, i.e., the third PMOS tube. The first control unit includes: M4, i.e., the third NMOS tube, and M5, i.e., the fourth NMOS tube. The second control unit includes: M2, i.e., the fifth NMOS tube, M3, i.e., the sixth NMOS tube, and PM3, i.e., the first PMOS tube. The first switch submodule is M1. C1 is a capacitor module, NM1 is a first NMOS tube, NM2 is a second NMOS tube, C2 represents the parasitic junction capacitance of the first NMOS tube, C3 represents the parasitic junction capacitance of the second NMOS tube, OPM1 represents an operational amplifier, VB1 represents the substrate bias provided by the operational amplifier, and bias is provided for NM1, NM2, and PM2 respectively. CLK represents a clock signal, i.e., a phase control signal, CLKB is an inverted signal of CLK, Vi represents a sampled input signal, Vo represents a sampled output signal, VCC is a power supply, and GND is a ground point.

[0068] The working principle of the circuit is: when CLK is high, CLKB is low, then M1 is turned on, M4 and M5 are turned on, and the voltage of the gate of PM1 is pulled down, so that PM1 is turned on. Since CLKB is low, PM3 is turned on, so that the gate of PM2 is the power supply voltage, PM2 is not turned on, M2 and M3 are also not turned on, so that the capacitor C1 is charged by the power supply VCC to the same voltage as VCC, and NM1 is not turned on, so that Vo maintains the previously sampled voltage.

[0069] On the contrary, when CLK is low, CLKB is high, at this time M1 is not conducting, M4 is conducting, but M5 is not conducting, increasing the gate voltage of PM1, making PM1 not conducting, and stopping the charging of capacitor C1. Since CLKB is high, PM3 is not conducting, but M3 is conducting, so that the gate of PM2 is pulled down, so that PM2 is conducting, M2 is not conducting, so that the voltage of capacitor C1 is loaded on NM1 and NM2, making the VGS (gate and source) voltage of NM1 and NM2 equal to VCC, and making NM2 start sampling the Vi signal, so that Vo is equal to Vi.

[0070] In specific implementation, the above-mentioned M1-M5, PM1-PM3 can adopt 0.8V core NMOS devices based on FDSOI (Fully Depleted-Silicon-On-Insulator, fully depleted SOI technology), and NM1-NM2 are NMOS made of flipped-well (flip chip technology).

[0071] It is understandable that those skilled in the art may also use MOS tubes made of other models and technologies, which is not limited here.

[0072] An embodiment of the present application further provides an analog-to-digital converter, comprising the low-voltage sampling device as described in the above embodiment.

[0073] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other. The modules and submodules in the devices and terminals of each embodiment of the present application can be merged, divided and deleted according to actual needs, and the features recorded in each embodiment can be replaced or combined.

[0074] In the several embodiments provided in the present application, it should be understood that the disclosed terminals and devices can be implemented in other ways. For example, the division of modules or submodules is only a logical function division, and there may be other division methods in actual implementation, such as multiple submodules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0075] The modules or submodules described as separate components may or may not be physically separated, and the components of the modules or submodules may or may not be physical modules or submodules, that is, they may be located in one place, or they may be distributed on multiple network modules or submodules. Some or all of the modules or submodules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0076] In addition, each functional module or sub-module in each embodiment of the present application may be integrated into one processing module, or each module or sub-module may exist physically separately, or two or more modules or sub-modules may be integrated into one module.

[0077] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the elements.

[0078] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-pressure sampling device, characterized in that: include: Capacitor module, charge and discharge control module, sampling voltage holding module and operational amplifier module; The input end of the charge and discharge control module is connected to a power supply, the output end of the charge and discharge control module is connected to a ground end, and the first control interface of the charge and discharge control module is connected to the capacitor module; The sampling voltage holding module includes: two NMOS tubes, the source of the first NMOS tube is connected to the drain of the second NMOS tube as a signal input terminal, the drain of the first NMOS tube is connected to a control terminal of the second control interface of the charge and discharge control module, the gate of the first NMOS tube and the gate of the second NMOS tube are respectively connected to another control terminal of the second control interface, and the source of the second NMOS tube is used as a signal output terminal; The operational amplifier module inputs the voltage of the input signal to the back gate of the first NMOS tube and the back gate of the second NMOS tube in the form of unit negative feedback; The charge-discharge control module charges the capacitor module to the same voltage as the first voltage of the power supply when the current clock signal is in the first phase, and makes the voltage of the signal output end the same as the voltage input from the signal input end by the previous clock signal, wherein the previous clock signal is adjacent to the current clock signal and earlier than the current clock signal; When the current clock signal is in the second phase, the charge and discharge control module stops charging the capacitor module, and makes the second voltage and the third voltage respectively the same as the first voltage, and the voltage of the signal output end is the same as the voltage currently input to the signal input end, the second voltage is the voltage between the gate and the source of the first NMOS tube, the second voltage is the voltage between the gate and the source of the second NMOS tube, and the first phase and the second phase are opposite.

2. The low-pressure sampling device according to claim 1, characterized in that: The operational amplifier module includes: an operational amplifier, a first input terminal of the operational amplifier is connected to an input signal, a second input terminal of the operational amplifier is connected to an output terminal of the operational amplifier, and an output terminal of the operational amplifier is respectively connected to a back gate of the first NMOS tube and a back gate of the second NMOS tube.

3. The low-pressure sampling device according to claim 1, characterized in that: The capacitor module includes: at least one capacitor, and the at least one capacitor is connected to the first control interface in parallel.

4. The low-pressure sampling device according to claim 1, characterized in that: The charge and discharge control module includes: a first switch submodule and a second switch submodule; The input end of the first switch submodule is connected in series with the capacitor module, the output end of the first switch submodule is connected with the ground end, and the control end of the first switch submodule is connected with a clock signal; The first input end of the second switch submodule is connected to the power supply, the first control end of the second switch submodule is connected to the capacitor module, the second control end of the second switch submodule is connected to the input end of the first switch submodule, the third control end of the second switch submodule is connected to the drain of the first NMOS tube, the fourth control end of the second switch submodule is connected to the gate of the first NMOS tube, the second input end of the second switch submodule is connected to the clock signal, and the third input end of the second switch submodule is connected to the inverted signal of the clock signal.

5. The low-pressure sampling device according to claim 4, characterized in that: The second switch submodule includes: a first switch unit, a first control unit, a second switch unit and a second control unit; The input end of the first switch unit is connected to the power supply, the output end of the first switch unit is connected to the capacitor module, and the control end of the second switch unit is connected to a common point; The input terminal of the first control unit is connected to the common point, the output terminal of the first control unit is connected to the ground terminal, the first control terminal of the first control unit is connected to the power supply, and the second control terminal of the first control unit is connected to the clock signal; The input end of the second switch unit is connected to the common point, the output end of the second switch unit is connected to the capacitor module, and the control end of the second switch unit is connected to the first input end of the second control unit; The first control terminal of the second control unit is connected to the common point, the second input terminal of the second control unit is connected to the power supply, the second control terminal of the second control unit is connected to the inverted signal of the clock signal, and the output terminal of the second control unit is connected to the input terminal of the first switch submodule; The gate of the first MOS transistor is connected to the common point, and the drain of the first MOS transistor is connected to the input end of the first switch sub-module.

6. The low-pressure sampling device according to claim 5, characterized in that: The first control unit includes: a third NMOS tube and a fourth NMOS tube, the gate of the third NMOS tube is connected to the power supply, the drain of the third NMOS tube is connected to the common point, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the clock signal, and the source of the fourth NMOS tube is connected to the ground terminal.

7. The low-pressure sampling device according to claim 5, characterized in that: The second control unit includes: a fifth NMOS tube, a sixth NMOS tube and a first PMOS tube, the drain of the fifth NMOS tube is connected to the control end of the second switch unit, the source of the fifth NMOS tube is connected to the input end of the first switch submodule, and the gate of the fifth NMOS tube is connected to the common point; The drain of the sixth NMOS tube is connected to the control end of the second switch unit, the source of the sixth NMOS tube is connected to the input end of the first switch submodule, and the gate of the sixth NMOS tube is connected to the inverted signal of the clock signal; The source of the first PMOS tube is connected to the power supply, the gate of the first PMOS tube is connected to the inverted signal of the clock signal, and the drain of the first PMOS tube is connected to the drain of the sixth NMOS tube.

8. The low-pressure sampling device according to claim 5, characterized in that: The first switch unit includes: a second PMOS tube, a drain of the second PMOS tube is connected to the capacitor module, a source of the second PMOS tube is connected to the power supply, and a gate of the second PMOS tube is connected to the common point.

9. The low-pressure sampling device according to claim 7, characterized in that: The second switch unit includes: a third PMOS tube, a drain of the third PMOS tube is connected to the capacitor module, a source of the third PMOS tube is connected to the common point, and a gate of the third PMOS tube is connected to the drain of the fifth NMOS tube.

10. An analog-to-digital converter, characterized in that: Comprising the low-pressure sampling device as described in any one of claims 1 to 9.

Images