Feed-forward equalizer delay chain control system for high-speed memory interface

Abstract

The invention provides a feed-forward equalizer delay chain control system for a high-speed memory interface, and relates to the technical field of high-speed large-capacity memories. Comprising a delay unit T1, a digital automatic gain controller DAGC and a digital delay phase-locked loop DDLL. And the digital automatic gain controller DAGC compares the data Tout delayed by the delay unit T1 with the original input data Din, controls the number of resistor arrays or current source arrays of the delay unit T1 according to a comparison result, and keeps the gain of the delay unit T1 to be 0dB all the time. The DDLL adjusts the number of capacitor arrays of the delay unit T1 according to channel characteristics, accurately adjusts the delay time of the delay unit, and ensures that the delay time of each stage of delay unit in the delay chain is consistent. The delay chain automatic control loop can ensure that no signal distortion occurs when a high-speed signal is transmitted on the delay chain of the feed-forward equalizer.

Description

Technical Field

[0001] The invention belongs to the technical field of high-speed and large-capacity memory, and in particular relates to a feedforward equalizer delay chain control system for a high-speed memory interface. Background Art

[0002] The increasing bandwidth of network traffic speed requires the storage subsystem to have a high random storage rate. However, in most subsystems, the signal transmission between the memory and the main control chip must be transmitted through the backplane, and the skin effect and dielectric loss become the main factors limiting the channel bandwidth. The difference in the attenuation degree of low-frequency and high-frequency components is too large, which eventually closes the eye diagram at the receiving end. The signal swing at the receiving end is reduced, and the quality of the overlapping signal between codes deteriorates, which will lead to an increase in the bit error rate and a decrease in system performance. In severe cases, it may even fail to work properly. To solve these problems, the receiving end usually needs to reshape the signal and introduce a filter to correct the signal. This filter is called an equalizer. Feedforward equalizer (FFE) is one of the commonly used discrete digital filter equalizers.

[0003] Figure 1 It is a commonly used feedforward equalization circuit, including a delay unit T, a tap Cn (n = -n ... -2, -1, 0, 1, 2 ... n), a coefficient adjustment unit and a summing module. The delay unit T forms a delay chain, and the delay unit delays the input signal by one, 1 / 2 or a fraction of the signal unit length; the taps, C0 is the main tap, C-1 and C-2 are the front taps used to compensate for the inter-symbol interference effect before the main tap, and C1 and C2 are the rear taps used to compensate for the inter-symbol interference effect after the tap; the coefficient adjustment unit adjusts the supplementary strength of each tap according to the channel characteristics; the summing module adds the coefficients and outputs the data with the inter-symbol interference eliminated.

[0004] In the commonly used feedforward system, the delay chain has strict requirements, requiring the signal to be undistorted and the delay time of each stage to be precisely equal. However, in actual applications, the delay unit will be affected by changes in temperature and power supply voltage, causing changes in delay time and gain, resulting in signal attenuation and deformation when the signal is transmitted on the delay chain. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art and provide a feedforward equalizer delay chain control system for a high-speed memory interface, which automatically adjusts the delay unit to ensure that the delay chain signal is not distorted and each stage is accurately equal.

[0006] In order to solve the above technical problems, the present invention provides a feedforward equalizer delay chain control system for a high-speed memory interface, comprising:

[0007] Delay unit T1, a plurality of upper and lower delay units T1 connected end to end;

[0008] A digital automatic gain controller DAGC is connected to the delay units T1 and the digital delay phase-locked loop DDLL of the upper and lower levels, and is used to keep the gain of the delay unit T1 at 0 dB;

[0009] The digital delay locked loop DDLL is connected to a plurality of upper and lower level delay units T1 to accurately adjust the delay time of the delay unit T1 and ensure that the delay time of each level of the delay unit T1 in the delay chain is consistent.

[0010] Preferably, the delay unit T1 includes: an adjustable resistor array or an adjustable current source array, an adjustable capacitor array and a buffer; wherein the adjustable resistor array or the adjustable current source array is connected to the buffer and the digital automatic gain controller DAGC, and the digital automatic gain controller DAGC realizes the function of adjusting the buffer gain by adjusting the number of the adjustable resistor array or the adjustable current source array; the adjustable capacitor array is connected to the buffer and the digital delay phase-locked loop DDLL, and the digital delay phase-locked loop DDLL realizes the function of adjusting the delay of the delay unit T1 by adjusting the number of the adjustable capacitor array.

[0011] Preferably, the digital automatic gain controller DAGC includes: a differential comparator and a U / D add-subtract counter; wherein the differential comparator, the U / D add-subtract counter and the delay unit T1 are connected end to end to form a loop, the data Tout delayed by the delay unit T1 and the original input data Din are connected to the input end of the differential comparator, the comparison result is connected to the input end of the U / D add-subtract counter via the output end of the differential comparator, the U / D add-subtract counter performs up-counting or down-counting according to the output result of the differential comparator, the counting result is connected to the adjustable resistor array or adjustable current source array of the delay unit T1 via the output end of the U / D add-subtract counter, the number of resistors and current sources in the adjustable resistor array or adjustable current source array of the delay unit T1 is controlled, thereby controlling the gain of the delay unit T1; the differential comparator and the U / D add-subtract counter are connected to the clock signal CLK.

[0012] Preferably, the digital delay locked loop DDLL comprises: a binary phase detector BBPD and a digital filter DLF; wherein the delay unit T1, the binary phase detector BBPD and the digital filter DLF are connected end to end to form a loop, the reference clock signal REF CLK is input into the delay chain composed of the delay unit T1, and the delayed clock signal REF CLK delayThe reference clock signal REF CLK is input into the binary phase detector BBPD together, and the phase difference between the two is detected. The identification result of the binary phase detector BBPD is input into the digital filter DLF. The digital filter DLF adjusts the number of the adjustable capacitor array in the delay unit T1 according to the digital control signal generated by the phase error, so as to realize the delay function of adjusting the delay unit T1.

[0013] Preferably, the frequency of the reference clock signal REF CLK and the number N of the delay chains of the digital delay locked loop DDLL are set according to the channel characteristics, so as to obtain the delay time t of the delay unit T1; that is, t=t clk / N; where t is the delay time of each delay unit T1; t clk is the cycle time of the reference clock signal REF CLK, that is, 1 / frequency; N is the number of delay units T1 in the delay chain.

[0014] Preferably, the feedforward equalizer delay chain control system performs foreground calibration under conditions where voltage and temperature changes are small, that is, the delay chain calibration is completed before the system works normally; specifically, it includes: entering the calibration mode, the digital automatic gain controller DAGC first completes convergence, then the digital delay phase-locked loop DDLL is locked, and finally initialization is completed and the calibration mode is exited.

[0015] Preferably, the feedforward equalizer delay chain control system performs background calibration under conditions of large voltage and temperature changes, that is, the delay chain is continuously calibrated as the voltage and temperature change when the system is working normally; wherein, in the background calibration process, the convergence bandwidth of the digital automatic gain controller DAGC is smaller than the bandwidth of the digital delay locked loop DDLL.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The present invention proposes a feedforward equalizer delay chain control system for a high-speed memory interface, comprising a delay unit T1, a digital automatic gain controller DAGC, and a digital delay phase-locked loop DDLL. The digital automatic gain controller DAGC compares the data Tout delayed by T1 with the original input data Din, and controls the number of resistor arrays or current source arrays of the delay unit T1 according to the comparison result, so as to keep the gain of the delay unit T1 always at 0dB. The digital delay phase-locked loop DDLL adjusts the number of capacitor arrays of the delay unit T1 according to the channel characteristics, accurately adjusts the delay time of the delay unit, and ensures that the delay time of each level of delay unit in the delay chain is consistent. The delay chain automatic control loop can ensure that no signal distortion occurs when the high-speed signal is transmitted on the delay chain of the feedforward equalizer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the traditional feedforward equalization circuit structure.

[0019] Figure 2 It is a schematic diagram of the delay chain automatic control loop structure of the present invention.

[0020] Figure 3 It is a schematic diagram of the delay unit structure of the present invention.

[0021] Figure 4 It is a structural schematic diagram of a digital automatic gain controller of the present invention.

[0022] Figure 5 It is a schematic diagram of the structure of a digital delay locked loop of the present invention.

[0023] Figure 6 It is a schematic diagram of the foreground calibration process of the feedforward equalizer delay chain control system of the present invention.

[0024] Figure 7 It is a schematic diagram of the background calibration process of the feedforward equalizer delay chain control system of the present invention. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0026] like Figure 2 As shown, an embodiment of the present invention provides a feedforward equalizer delay chain control system for a high-speed memory interface, comprising:

[0027] Delay unit T1, a plurality of upper and lower delay units T1 connected end to end;

[0028] A digital automatic gain controller DAGC is connected to the delay units T1 and the digital delay phase-locked loop DDLL of the upper and lower levels, and is used to keep the gain of the delay unit T1 at 0 dB;

[0029] The digital delay locked loop DDLL is connected to a plurality of upper and lower level delay units T1 to accurately adjust the delay time of the delay unit T1 and ensure that the delay time of each level of the delay unit T1 in the delay chain is consistent.

[0030] like Figure 3As shown, the delay unit T1 includes: an adjustable resistor array or an adjustable current source array, an adjustable capacitor array and a buffer; wherein the adjustable resistor array or the adjustable current source array is connected to the buffer and the digital automatic gain controller DAGC, and the digital automatic gain controller DAGC adjusts the buffer gain by adjusting the number of the adjustable resistor array or the adjustable current source array; the adjustable capacitor array is connected to the buffer and the digital delay phase-locked loop DDLL, and the digital delay phase-locked loop DDLL adjusts the delay of the delay unit T1 by adjusting the number of the adjustable capacitor array.

[0031] like Figure 4 As shown, the digital automatic gain controller DAGC includes: a differential comparator and a U / D add-subtract counter; wherein the differential comparator, the U / D add-subtract counter and the delay unit T1 are connected end to end to form a loop, the data Tout delayed by the delay unit T1 and the original input data Din are connected to the input end of the differential comparator, the comparison result is connected to the input end of the U / D add-subtract counter via the output end of the differential comparator, the U / D add-subtract counter performs up-counting or down-counting according to the output result of the differential comparator, the counting result is connected to the adjustable resistor array or adjustable current source array of the delay unit T1 via the output end of the U / D add-subtract counter, the number of resistors and current sources in the adjustable resistor array or adjustable current source array of the delay unit T1 is controlled, thereby controlling the gain of the delay unit T1; the differential comparator and the U / D add-subtract counter are connected to the clock signal CLK.

[0032] like Figure 5 As shown, the digital delay phase-locked loop DDLL includes: a binary phase detector BBPD and a digital filter DLF; wherein the delay unit T1, the binary phase detector BBPD and the digital filter DLF are connected end to end to form a loop, the reference clock signal REF CLK is input into the delay chain composed of the delay unit T1, the delayed clock signal REFCLKdelay and the reference clock signal REF CLK are input into the binary phase detector BBPD together, and the phase difference between the two is detected, the identification result of the binary phase detector BBPD is input into the digital filter DLF, and the digital filter DLF adjusts the number of the adjustable capacitor array in the delay unit T1 according to the digital control signal generated by the phase error, so as to realize the delay function of adjusting the delay unit T1.

[0033] The frequency of the reference clock signal REF CLK and the number N of the delay chains of the digital delay locked loop DDLL are set according to the channel characteristics, thereby obtaining the delay time t of the delay unit T1; that is, t=tclk / N; wherein t is the delay time of each delay unit T1; tclk is the cycle time of the reference clock signal REF CLK, that is, 1 / frequency; N is the number of delay units T1 in the delay chain.

[0034] The feedforward equalizer delay chain control system is controlled under the condition that the voltage and temperature change is small, such as Figure 6 As shown in the flowchart, foreground calibration can be performed, that is, delay chain calibration is completed before the system works normally. Entering the calibration mode, first, the digital automatic gain controller DAGC completes convergence, next, the digital phase-locked loop is locked, and finally the initialization is completed to exit the calibration mode.

[0035] The feedforward equalizer delay chain control system is under the condition of large voltage and temperature changes, such as Figure 7 As shown in the flowchart, background calibration can be performed, that is, the delay chain is continuously calibrated with voltage and temperature changes when the system is working normally. In the background calibration process, the digital automatic gain controller DAGC convergence bandwidth is smaller than the digital phase-locked loop bandwidth.

[0036] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A feedforward equalizer delay chain control system for a high-speed memory interface, characterized in that: include: Delay unit T1, a plurality of upper and lower delay units T1 connected end to end; A digital automatic gain controller DAGC is connected to the delay units T1 and the digital delay phase-locked loop DDLL of the upper and lower levels, and is used to keep the gain of the delay unit T1 at 0 dB; The digital delay locked loop DDLL is connected to a plurality of upper and lower level delay units T1 to accurately adjust the delay time of the delay unit T1 and ensure that the delay time of each level of the delay unit T1 in the delay chain is consistent.

2. A feedforward equalizer delay chain control system for a high-speed memory interface as claimed in claim 1, characterized in that: The delay unit T1 includes: an adjustable resistor array or an adjustable current source array, an adjustable capacitor array and a buffer; wherein the adjustable resistor array or the adjustable current source array is connected to the buffer and the digital automatic gain controller DAGC, and the digital automatic gain controller DAGC adjusts the buffer gain by adjusting the number of the adjustable resistor array or the adjustable current source array; the adjustable capacitor array is connected to the buffer and the digital delay phase-locked loop DDLL, and the digital delay phase-locked loop DDLL adjusts the delay of the delay unit T1 by adjusting the number of the adjustable capacitor array.

3. A feedforward equalizer delay chain control system for a high-speed memory interface as claimed in claim 1, characterized in that: The digital automatic gain controller DAGC comprises: a differential comparator and a U / D add-subtract counter; wherein the differential comparator, the U / D add-subtract counter and the delay unit T1 are connected end to end to form a loop, the data Tout delayed by the delay unit T1 and the original input data Din are connected to the input end of the differential comparator, the comparison result is connected to the input end of the U / D add-subtract counter via the output end of the differential comparator, the U / D add-subtract counter performs up-counting or down-counting according to the output result of the differential comparator, the counting result is connected to the adjustable resistor array or the adjustable current source array of the delay unit T1 via the output end of the U / D add-subtract counter, the number of resistors and current sources in the adjustable resistor array or the adjustable current source array of the delay unit T1 is controlled, thereby controlling the gain of the delay unit T1; the differential comparator and the U / D add-subtract counter are connected to the clock signal CLK.

4. A feedforward equalizer delay chain control system for a high-speed memory interface as claimed in claim 1, characterized in that: The digital delay locked loop DDLL comprises: a binary phase detector BBPD and a digital filter DLF; wherein the delay unit T1, the binary phase detector BBPD and the digital filter DLF are connected end to end to form a loop, the reference clock signal REF CLK is input into the delay chain composed of the delay unit T1, and the delayed clock signal REF CLK delay The reference clock signal REF CLK is input into the binary phase detector BBPD together, and the phase difference between the two is detected. The identification result of the binary phase detector BBPD is input into the digital filter DLF. The digital filter DLF adjusts the number of the adjustable capacitor array in the delay unit T1 according to the digital control signal generated by the phase error, so as to realize the delay function of adjusting the delay unit T1.

5. A feedforward equalizer delay chain control system for a high-speed memory interface as claimed in claim 1, characterized in that: The frequency of the reference clock signal REF CLK and the number N of the delay chains of the digital delay locked loop DDLL are set according to the channel characteristics, thereby obtaining the delay time t of the delay unit T1; that is, t=t clk / N; where t is the delay time of each delay unit T1; t clk is the cycle time of the reference clock signal REF CLK, that is, 1 / frequency; N is the number of delay units T1 in the delay chain.

6. A feedforward equalizer delay chain control system for a high-speed memory interface according to any one of claims 1 to 5, characterized in that: The feedforward equalizer delay chain control system performs foreground calibration under conditions of small voltage and temperature changes, that is, completes the delay chain calibration before the system works normally; specifically, it includes: entering the calibration mode, the digital automatic gain controller DAGC first completes convergence, then the digital delay phase-locked loop DDLL is locked, and finally completes initialization and exits the calibration mode.

7. A feedforward equalizer delay chain control system for a high-speed memory interface according to any one of claims 1 to 5, characterized in that: The feedforward equalizer delay chain control system performs background calibration under conditions of large voltage and temperature changes, that is, the delay chain is continuously calibrated as the voltage and temperature change when the system is working normally; wherein, in the background calibration process, the convergence bandwidth of the digital automatic gain controller DAGC is smaller than the bandwidth of the digital delay locked loop DDLL.

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