A method, apparatus and rate controller for controlling a message sending rate

Abstract

The application relates to a method, device and rate controller for controlling a message sending rate, the method comprising: obtaining a target sending rate of a to-be-sent message; determining a clock cycle simulation signal of a sending end according to the target sending rate of the to-be-sent message; processing the to-be-sent message based on the clock cycle simulation signal of the sending end and a target output bit width of the sending end to obtain at least one message data block, and sending the message data block; wherein the target output bit width of the sending end is determined based on an input bit width of a receiving end. Based on the above scheme, when a chip performance is verified, the chip can be flexibly configured with a sending rate without an external test instrument, so that the verification efficiency and quality can be improved while the verification cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip verification, and in particular to a method and device for controlling the sending rate of a message and a rate controller. BACKGROUND

[0002] Chip performance verification usually includes single-port performance verification of a chip, full-port throughput performance verification of a chip, unicast, multicast performance verification, shaper performance verification, verification of performance characteristics of various scheduling algorithms (such as PQ, DWRR, PQ+DWRR, WRR, PQ+WRR, Calendar), and the like. Through verification of these performances, it can be ensured that the internal performance of a chip meets the design requirements. In order to implement verification of these different performances, a corresponding ingress rate generator (a rate generator is used to simulate a traffic model in an actual network environment, so as to ensure the richness of a verification scenario and the reliability of a verification result) is needed to drive input data according to a target rate, so as to perform comprehensive performance verification.

[0003] The existing chip performance verification mainly adopts system-level verification, EMU hardware simulation accelerator, or FPGA prototype verification, and the like. The system-level verification focuses on verifying the functions of the entire system rather than the functions of a single chip. In the system-level verification, a model is usually constructed to simulate the interaction of the entire system, including the interaction of a chip with external devices. However, this type of verification has the problems of long compilation and simulation time, and limited traffic model, which cannot fully simulate the real network environment. The EMU hardware simulation accelerator is a hardware platform for accelerating the verification of circuit design. It accelerates the simulation process through special hardware. However, this type of verification needs a special EMU device and needs to be connected to a tester, which increases the cost of purchasing the device and the difficulty of debugging. The FPGA prototype verification refers to the process of mapping a chip to be verified onto an FPGA for verification. However, this type of verification also needs an FPGA device and a tester, thus also bringing high financial cost. In addition, the FPGA prototype-based verification also needs a special debugging personnel, which also increases the cost of human resources. SUMMARY

[0004] In view of the above problems of the prior art, the present application provides a method and device for controlling the sending rate of a message and a rate controller, which can simulate a traffic model in a real network environment by sending message data according to a target rate without the need of external testers and other hardware devices. In this way, the cost is reduced, and UUT-level verification and system-level verification can be implemented, thus improving the verification efficiency and verification quality.

[0005] To achieve the above object, the first aspect of the present application provides a method for controlling a message sending rate, comprising: obtaining a target sending rate of a to-be-sent message; determining a clock cycle simulation signal of a sending end according to the target sending rate of the to-be-sent message; processing the to-be-sent message based on the clock cycle simulation signal of the sending end and a target output bit width of the sending end to obtain at least one message data block, and sending the message data block; wherein the target output bit width of the sending end is determined based on an input bit width of a receiving end.

[0006] From the above, the present application controls the message sending rate by software, calculates the clock cycle of the sending end through the target sending rate, and then processes the to-be-sent message based on the clock cycle of the sending end and the target output bit width, so that the chip verification can be carried out flexibly at the UUT and system levels, and different message sending rates can be simulated without external test instruments in the chip verification process, thereby saving costs and improving verification efficiency and quality.

[0007] As an implementation manner of the present aspect, the determining of the clock cycle simulation signal of the sending end according to the target sending rate of the to-be-sent message comprises: determining a clock frequency actual signal of the sending end according to the target sending rate of the to-be-sent message; and determining the clock cycle simulation signal of the sending end according to the clock frequency actual signal of the sending end, a clock cycle simulation signal of the receiving end, and a clock frequency actual signal of the receiving end.

[0008] From the above, the clock information of the sending end is converted by mapping the clock ratio relationship between the sending end and the receiving end in the simulation process, thereby improving the accuracy and controllability of the simulation.

[0009] As an implementation manner of the present aspect, the processing of the to-be-sent message based on the clock cycle simulation signal of the sending end and the target output bit width of the sending end to obtain at least one message data block, and the sending of the message data block, comprises: in each cycle of the clock cycle simulation signal of the sending end, deducting a preset number of bytes from a byte stream of the to-be-sent message; when the number of deducted bytes reaches an integer multiple of the target output bit width or after the bytes of the byte stream of the to-be-sent message are all deducted, taking the number of bytes deducted this time as one message data block for sending according to the target sending rate.

[0010] From the above, by the processing of deducting the number of bytes at the sending end, the sending end can output data according to the input bit width of the receiving end, thereby controlling the message sending rate.

[0011] As an implementation form of the aspect, the method further comprises: generating a scheduling flag when the number of bytes deducted reaches a positive integer multiple of the target output bit width or when the number of bytes of the byte stream of the to-be-sent packet is completely deducted; wherein the scheduling flag is used to indicate that the sending end is ready for the packet data block to be transmitted; and the scheduling flag is sent, and after the receiving end receives the scheduling flag, the packet data block is sent according to the target sending rate.

[0012] According to the above, the sending end is indicated to be ready for data by the scheduling flag, so that the scheduling is convenient and reasonable and in order.

[0013] As an implementation form of the aspect, when there are multiple parallel sending data streams in the sending end and there is only one receiving data stream in the receiving end, the following steps are performed: the multiple sending data streams respectively perform the processing to obtain respective corresponding packet data blocks; after the respective corresponding packet data blocks are obtained, scheduling flags of the packet data blocks are generated, different scheduling flags corresponding to different sending data streams are different, and the scheduling flags are used to indicate that the sending end is ready for the packet data block to be transmitted; when multiple different scheduling flags are received in one clock cycle of the receiving end, a scheduling order of the packet data blocks corresponding to the different scheduling flags is determined according to a preset rule; and the packet data blocks are sequentially sent according to the scheduling order; wherein one data stream corresponds to one or more to-be-sent packets, and the data stream includes a sending data stream and a receiving data stream.

[0014] According to the above, the parallel data streams of the sending end are converted into serial data streams by adding a scheduling rule, and the scheduling can also be sequentially implemented.

[0015] As an implementation form of the aspect, when there are multiple receiving data streams in the receiving end, the multiple receiving data streams are simultaneously run.

[0016] As an implementation form of the aspect, the packet sending further comprises a burst mode, in which the average sending rate of the to-be-sent packet is controlled to be equal to the target sending rate.

[0017] As an implementation form of the aspect, the control of the average sending rate of the to-be-sent packet to be equal to the target sending rate comprises: configuring a required burst data amount, the burst data amount being not more than the target output bit width; in an acceleration phase of packet sending, when the clock cycle of the sending end is deducted to the burst data amount, a flag is generated to indicate that the to-be-sent packet data is sent in advance; and in a deceleration phase of packet sending, after the burst data amount is delayed, a new packet deduction count is started.

[0018] From the above, the burst mode in the real network environment is simulated, and the rate model is enriched.

[0019] The second aspect of the present application provides a rate controller, which is used to send the to-be-sent packet at the target sending rate based on the configuration data input through the interfaces and the method of any one of the first aspect.

[0020] The beneficial effects of the present aspect can also be seen from the description of the beneficial effects of each part of the first aspect.

[0021] The third aspect of the present application provides a device for controlling the sending rate of a packet, comprising: a packet generator, which is used to generate a packet stream with port identification based on different ports and take the packet stream as a to-be-sent packet; a rate controller, which is used to configure a target sending rate for the to-be-sent packet according to the method of any one of claims 1-8; a scheduler, which is used to determine the sending order of the packet stream according to the pre-configured scheduling order rule when there are multiple parallel sending data streams in the sending end and there is only one receiving data stream in the receiving end; and a driver, which sends the packet according to the target output bit width and the target sending rate.

[0022] The beneficial effects of the present aspect can also be seen from the description of the beneficial effects of each part of the first aspect.

[0023] The fourth aspect of the present application provides a computing device, comprising: at least one processor; and at least one memory connected with the processor and storing program instructions, which, when executed by the at least one processor, cause the at least one processor to execute the method for controlling the sending rate of a packet in any one of the first aspect.

[0024] The beneficial effects of the present aspect can also be seen from the description of the beneficial effects of each part of the first aspect.

[0025] The fifth aspect of the present application provides a computer readable storage medium, which stores program instructions, which, when executed by a computer, cause the computer to execute the method for controlling the sending rate of a packet in any one of the first aspect.

[0026] The beneficial effects of the present aspect can also be seen from the description of the beneficial effects of each part of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0027] The various technical features of the present application and the relationships between them will be further illustrated below with reference to the accompanying drawings. The drawings are exemplary, some technical features are not shown in actual proportion, and some technical features in the drawings can be omitted, which are conventional in the technical field to which the present application belongs and are not essential for understanding and implementing the present application, or additional technical features are shown, which are not essential for understanding and implementing the present application. That is, the combination of various technical features shown in the drawings is not used to limit the present application. In addition, the same reference signs refer to the same contents throughout the present application. The specific drawings are as follows:

[0028] Figure 1 A flow chart of a method for controlling a packet sending rate according to an embodiment of the present application;

[0029] Figure 2 A schematic diagram of processing a to-be-sent packet according to an embodiment of the present application;

[0030] Figure 3 A schematic diagram of processing a to-be-sent packet when there are multiple data streams at the sending end and one data stream at the receiving end according to an embodiment of the present application;

[0031] Figure 4 A rate model schematic diagram of a burst mode according to an embodiment of the present application;

[0032] Figure 5 A schematic diagram of processing a to-be-sent packet in a burst mode according to an embodiment of the present application;

[0033] Figure 6 A structural schematic diagram of a device for controlling a packet sending rate according to an embodiment of the present application;

[0034] Figure 7 A structural schematic diagram of a computing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions provided by the present application will be further described below in combination with the drawings and embodiments. It should be understood that the system structure and service scenarios provided in the embodiments of the present application are mainly used to illustrate possible implementation manners of the technical solutions of the present application, and should not be interpreted as the only limitation of the technical solutions of the present application. Those skilled in the art can know that the technical solutions provided by the present application are also applicable to similar technical problems with the evolution of system structure and the emergence of new service scenarios.

[0036] It should be understood that the embodiments of the present application provide a scheme for controlling the sending rate of a packet. Since the principles of the technical solutions for solving problems are the same or similar, in the introduction of the following specific embodiments, some repetitions may not be described again, but should be regarded as mutual reference and mutual combination between the specific embodiments.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. If there is a conflict between the meanings of terms in the specification and the meanings of the terms according to the prior art, the meanings in the specification or the meanings derived from the content described in the specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0038] Before the specific embodiments of the present application are further described in detail, the terms and belong to the embodiments of the present application and their corresponding uses\roles\functions in the present application are described. The terms and belong to the embodiments of the present application are applicable to the following explanations:

[0039] UUT (Unit Under Test) level verification: In the field of chip design, UUT level verification generally refers to verification of the chip itself. The goal of UUT level verification is to ensure that the chip works normally at its basic functional level, including verifying its logic function, timing, power management, signal integrity, etc.

[0040] System level verification: refers to verification of multiple interrelated UUTs or modules after integration. In integrated circuit design, it means integrating multiple UUTs together to form a larger functional module or system, and then verifying the characteristics of the functional module or system when it is operating as a whole.

[0041] The embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. First, the application scenario of the scheme for controlling the sending rate of a packet provided by the embodiments of the present application is introduced.

[0042] The scheme for controlling the sending rate of a packet provided by the present application can accurately control the sending rate of a packet without external testing instruments and other hardware devices to simulate and manage different network traffic models. Therefore, the present scheme is particularly suitable for use in the verification scenario of a network chip (which may include a network switch chip, a router, various data processing units (such as a DPU), etc.) to verify the performance (such as throughput, latency, etc.) of the network chip at different rates. The present scheme can also be applied in network communication, such as in network protocol verification or traffic model generation, to ensure that packets are sent at a specific rate to test the performance of network devices.

[0043] It should be understood that the above application scenarios are exemplary descriptions and are not intended to limit the scope of the present application.

[0044] The method for controlling the sending rate of a message provided by the embodiment of the present application is described in detail below with reference to the accompanying drawings. The following embodiment is described in terms of data processing units of bytes (byte), wherein 1 byte = 8 bits (bit), that is, a message is generally processed into a format of n*8 bits (n≥1, n is an integer) for transmission.

[0045] As shown in FIG. 1, the method for controlling the sending rate of a message includes the following steps S110-S130, which are described in detail as follows. Figure 1

[0046] S110: Obtain a target sending rate of a message to be sent.

[0047] In the embodiment, the target sending rate of a message is determined based on the required rate of a specific application scenario, and the specific meaning thereof is described below by way of several examples.

[0048] For example, in single-port performance verification of a chip, if the highest performance of a single port is to be verified, the target sending rate can be set to the maximum rate supported by the port, for example, 10 Gbps.

[0049] For another example, if a switch chip supporting multiple high-speed ports is to be verified, the target sending rate can be set to the maximum rate supported by each port, and then summed up to obtain the total throughput, for example, the total throughput of four 10 Gbps ports is 40 Gbps.

[0050] For another example, in verification of a shaper, the target sending rate can be set to different rate values, for example, 10 Mbps, 100 Mbps, 1 Gbps, etc., to verify whether the shaper can correctly limit the sending rate of a message.

[0051] Generally, the commonly used data transmission rates in network transmission include 10 Mbps, 100 Mbps, 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps, etc., and the required target sending rate can be selected based on the requirements of different application scenarios, and other target sending rates not listed can also be set based on different requirements.

[0052] S120: Determine a clock period simulation signal of a sending end according to the target sending rate of the message to be sent.

[0053] First, the clock frequency actual signal of the sending end is determined according to the target sending rate of the message to be sent, specifically:

[0054] ​Generally, the sending rate is expressed in "bit per second" (bps). In the chip, the sending rate is counted by clock number, where one clock period is the difference between two adjacent rising edges or the difference between two adjacent falling edges. One clock period T = 1 / F (F is the clock frequency), then the sending rate rate corresponding to sending 8bit data in N clock periods can be calculated by the following formula: rate = 8bit / NT = 8bit*F / N.

[0055] If one clock period is used to send message data with 8bit bit width, then based on the above rate calculation formula, the clock frequency F corresponding to the rate rate of 10Mbps is 1.25Mhz; the clock frequency F corresponding to the rate rate of 100Mbps is 12.5Mhz; the clock frequency F corresponding to the rate rate of 1Gbps is 125Mhz; the clock frequency F corresponding to the rate rate of 2.5Gbps is 312.5Mhz; the clock frequency F corresponding to the rate rate of 5Gbps is 625Mhz; the clock frequency F corresponding to the rate rate of 10Gbps is 1250Mhz. It should be understood that the rates of 10Mbps, 100Mbps, 1Gbps, 2.5Gbps, 5Gbps, 10Gbps and the like in the above examples are commonly used transmission rates in network transmission, so the corresponding frequency values are listed, but these rate examples do not limit the scope of the present application, and in other embodiments, the corresponding clock frequency value can be obtained by the above formula calculation based on the actual required target rate.

[0056] Then, the clock period simulation signal of the sending end is determined according to the clock frequency actual signal of the sending end, the clock period simulation signal of the receiving end, and the clock frequency actual signal of the receiving end. Specifically, the simulation signal of the clock period of the sending end can be determined according to the following formula:

[0057]

[0058] In the above formula, is the clock period simulation signal of the sending end, is the clock frequency actual signal of the sending end, is the clock period simulation signal of the receiving end, is the clock frequency actual signal of the receiving end.

[0059] It should be understood that since the simulation period is counted in terms of the number of clock cycles (i.e., several clock cycles) rather than the specific duration, the simulated clock cycle signal at the transmitting end needs to be mapped back to the transmitting end in a mapped form to represent the clock cycle at the transmitting end. Therefore, the above calculation formula describes the number of clock cycles corresponding to mapping the simulated clock cycle signal at the receiving end to the transmitting end. That is, the simulated clock cycle signal at the transmitting end can be calculated by multiplying the simulated clock cycle signal at the receiving end and the actual clock frequency signal at the receiving end, and then dividing by the actual clock frequency signal at the transmitting end calculated using the frequency formula.

[0060] S130: Process the message to be sent based on the clock cycle simulation signal of the transmitting end and the target output bit width of the transmitting end to obtain at least one message data block, and send the message data block.

[0061] In this embodiment, the target output bit width of the transmitting end is determined based on the input bit width of the receiving end. For example, if the input bit width received by the receiving end is 2 bytes, then the target output bit width of the transmitting end should also be 2 bytes.

[0062] Specifically, in each cycle of the clock simulation signal at the transmitting end, a preset number of bytes are deducted from the byte stream of the message to be sent. When the number of deducted bytes reaches a positive integer multiple of the target output bit width, or when all bytes in the byte stream of the message to be sent have been deducted, the number of bytes deducted is taken as a message data block for the transmitting end to send at the target transmission rate.

[0063] In some embodiments, after each byte deduction operation is performed (i.e., when the number of deducted bytes reaches a positive integer multiple of the target output bit width or when all bytes of the byte stream of the message to be sent are deducted), a scheduling flag is generated to indicate that the sender is ready to transmit the message data block. Then the sender sends the scheduling flag. After the next-level module (e.g., the scheduler or the receiver) receives the scheduling flag, the sender sends the message data block according to the target transmission rate.

[0064] Next Figure 2 The example shown illustrates the processing procedure for the message to be sent in this step.

[0065] exist Figure 2 In the example shown, the data length of the message to be sent is 64 bytes, the target output bit width (i.e., the input bit width of the receiver) is 4 bytes (i.e., 4*8=32 bits), and the preset number of bytes deducted per clock cycle by the transmitter is 1 byte. In this example, the clock cycle simulation signal of the transmitter is represented by clock inner, and the clock cycle simulation signal of the receiver is represented by clock DUT.

[0066] In this example, the actual frequency of the transmitter clock is first calculated based on the target transmission rate, and then the simulated transmitter clock period signal is calculated based on this frequency. Figure 2 As shown, the data length of the message to be sent at the transmitting end is 64 bytes, that is, the message length is 1~64 bytes before the start of the first cycle. One byte of data is deducted in each clock cycle at the transmitting end, that is, after the first cycle, the message length becomes 2~64 bytes, after the second cycle, the message length becomes 3~64 bytes, after the third cycle, the message length becomes 4~64 bytes, and after the fourth cycle, the message length should be 5~64 bytes (not shown). At this time, the number of bytes deducted is bytes 1~4, a total of 4 bytes. At the end of the fourth cycle, data with a width of 4 bytes has been generated, which is twice the target output width of 4 bytes. The deducted 1~4 bytes are treated as a message data block. At this time, a scheduling flag is generated to indicate that the transmitting end has completed the conversion of the message to be sent according to the target transmission rate. The scheduling flag is sent to the receiving end, and the message data block (i.e., the message data of bytes 1~4) is driven to be sent to the corresponding clock of the receiving end at the target rate. Similarly, after the 8th cycle of the sending end, the second flag and the second message data block (i.e., the message data from the 5th to the 8th byte) are sent to the receiving end. And so on, the sending end sends out all 64 bytes of message data. The sending end needs to generate 16 flags, which are sent in 16 separate 4-byte segments.

[0067] In some embodiments, when there are multiple received data streams at the receiving end, the message processing principle is the same as that for a single stream (refer to the description in the above embodiments). Therefore, the multiple received data streams can run simultaneously, that is, each runs its own and does not affect the others.

[0068] In some embodiments, when the transmitting end has multiple parallel data streams and the receiving end has only one data stream, it is necessary to convert the parallel streams at the transmitting end into a serial stream, and then use time-division multiplexing at the receiving end. Specifically, this can be handled as follows:

[0069] Multiple data streams process the packets to be sent separately (as described in the byte deduction process in the above embodiment), thereby obtaining their respective packet data blocks and generating corresponding scheduling flags (different data streams have different scheduling flags). Therefore, it is possible that the receiving end receives multiple different scheduling flags within the same clock cycle. In this case, this embodiment adds a scheduler between the sending end and the receiving end to schedule multiple packet data blocks. Within the scheduler, the packet data blocks corresponding to different scheduling flags are scheduled according to the determined scheduling order based on a pre-set scheduling algorithm or scheduling rules.

[0070] In some embodiments, the scheduling algorithms or rules within the scheduler include, but are not limited to, Round Robin, Priority Scheduling, and Calendar Scheduling.

[0071] It should be understood that a data stream corresponds to one or more of the aforementioned messages to be sent. That is, a message to be sent can be sent through a single data stream or split into multiple data streams. A single data stream can send one message to be sent or multiple messages to be sent. This application does not impose any restrictions on this.

[0072] Next, combine Figure 3 This example illustrates the scenario where the sending end has multiple data streams and the receiving end has only one data stream. For example... Figure 3 As shown, in this example, the transmitting end has two transmitted data streams, and the corresponding clock cycle simulation signals for these two transmitted data streams are represented by clock inner a and clock inner b (the calculation method is described in step S120 above). The receiving end has one received data stream, and the clock cycle simulation signal for this received data stream is represented by clock DUT. In this example, due to the situation of parallel streams being converted to serial streams, a scheduler needs to be added between the transmitting and output ends to implement scheduling. Specifically, as shown... Figure 3As shown, the packet data of clock inner a generates a flag to send to the scheduler after deducting 4 bytes (the target output bit width is 4 bytes in this example), and the packet data of clock inner b also generates a flag to send to the scheduler after deducting 4 bytes, and the scheduler determines that the packet data of clock inner a is preferentially sent according to the two received flags and the preconfigured scheduling rule, so the packet data of clock inner a is first driven to be sent to the receiving end, and then the packet data of clock inner b is driven to be sent to the receiving end, and so on, until the packet data of clock inner a and clock inner b are all sent, and the packet sending process is ended.

[0073] In some embodiments, the packet sending of the present application also supports a burst mode, which refers to a special mode in the packet sending process, allowing more data streams to be sent in a short time. In the burst mode of the present application, the average sending rate of the to-be-sent packet is controlled to be equal to the target sending rate. The rate model of the burst mode can refer to Figure 4 that is, the packet sending process is divided into an acceleration phase and a deceleration phase, and the average sending rates of the acceleration phase and the deceleration phase are equal to the target sending rate. Specifically, first, the required burst data stream is configured, which generally does not exceed the target output bit width; in the acceleration phase of the packet sending, when the clock period of the sending end is deducted to the burst data amount, a flag is generated to indicate that the advance sending is completed, that is, the acceleration sending is completed; in the deceleration phase of the packet sending, the processing of new packets is restarted after being delayed by the burst data amount, so as to ensure that the average rate is equal to the target rate.

[0074] Next, the burst mode is described in combination with the example of Figure 5 In this example, the packet length is 64 bytes, and the target output bit width is 4 bytes. In this case, the burst data amount generally ranges from rate*(64 / 60 ~ 64 / 68), so the example takes 2 bytes (that is, the packet is sent 2 bytes in advance) as an example to describe. As shown in Figure 5 The clock inner represents the clock period simulation signal of the sending end, and the clock DUT represents the clock period simulation signal of the received data stream, and the process of generating the scheduling flag is not described here, and can be referred to the description of the above embodiments.

[0075] In this example, the burst 2 bytes, i.e. the 64 bytes need to be sent at the original 62 bytes, then a flag is generated at the 62nd cycle of the sending end to indicate that the packet is sent in advance. As an implementation manner, the 2 bytes of data to be accelerated can be sent at the 62nd cycle of the sending end, i.e. 3 bytes of packet data are prepared at the 62nd cycle of the sending end. As another implementation manner, the data of the 1st to 64th bytes can be sent averagely at the 1st to 62nd cycles, or sent in other manners, and the application does not limit the same, and only the 64 bytes of data are prepared at the 62nd cycle of the sending end, and the acceleration stage is completed. Therefore, in the sending process of the following packet, the packet data needs to be sent with a delay of 2 bytes (i.e. corresponding to the deceleration stage), so as to ensure that the average rate is equal to the target rate.

[0076] In some embodiments, the commonly used language for chip verification is System Verilog, and the above method for controlling the sending rate of the packet can be implemented through the SV language or UVM.

[0077] Based on the method for controlling the sending rate of the packet provided in the above embodiments, the clock ratio mapping relationship between the sending end and the receiving end in the simulation process is mapped, so that the performance verification of the chip can be flexibly carried out at the UUT and the system level, and in cooperation with the packet processing manner provided in the application, different packet sending rates can be simulated in the chip verification process without external test instruments, which can save costs and improve verification efficiency and quality.

[0078] Another embodiment of the application provides a rate controller, which comprises a first interface to a sixth interface. The first interface is configured to configure a target sending rate of a to-be-sent packet; the second interface is configured to configure a clock cycle simulation signal of a receiving end; the third interface is configured to configure a clock frequency actual signal of the receiving end; the fourth interface is configured to configure a packet length of the to-be-sent packet; the fifth interface is configured to configure a target output bit width of the sending end; and the sixth interface is configured to configure a burst data amount in a burst mode.

[0079] Based on the configured target sending rate, the clock cycle simulation signal of the receiving end and the clock frequency actual signal of the receiving end, the clock cycle simulation signal of the sending end is determined, and then the to-be-sent packet is processed based on the clock cycle simulation signal of the sending end and the target output bit width of the sending end, so that the to-be-sent packet is sent in the form of a database according to the target sending rate.

[0080] It should be understood that the rate controller provided in the embodiment is used to execute the method for controlling the sending rate of the packet in the above embodiments, and the specific implementation manner of the embodiment can be referred to the introduction of the above embodiments, and the embodiment will not be described herein.

[0081] Yet another embodiment of the present application provides an apparatus for controlling the sending rate of packets, as shown in Figure 6 The apparatus includes a packet generator 610, a rate controller 620, a scheduler 630, and a driver 640.

[0082] The packet generator 610 is configured to generate packet flows with port identifiers based on different ports, and send the packet flows as to-be-sent packets. As shown in Figure 6 The pkt identifier represents a packet flow, and pkt a represents a packet flow with port identifier a, and pkt b represents a packet flow with port identifier b, where the port identifier is mainly used to identify the source or destination of each packet flow. The packet generator 610 sends the packet flows to the rate controller 620 and the scheduler 630.

[0083] The rate controller 620 processes the received packet flows according to the method provided in the above embodiments, so as to obtain a target sending rate, and declares to be configured with a rate that can be scheduled by generating a scheduling flag.

[0084] The scheduler (SCH) 630 is responsible for managing the sending order of the packets, and determines which packet can be sent preferentially according to a pre-configured scheduling order rule or a short sending, so as to realize the ordered scheduling of the packets.

[0085] The driver (Driver) 640 sends corresponding packet data to the receiving end with a target output bit width and a target sending rate.

[0086] In Figure 6 , the target output bit width is represented as 8*n bit, and the receiving end is represented as DUT, where the DUT is a chip to be verified.

[0087] The specific implementation of each device in this embodiment can refer to the description of each embodiment described above, and the present embodiment will not be described again.

[0088] Figure 7 is a structural schematic diagram of a computing device 900 provided by an embodiment of the present application. The computing device can execute each optional embodiment of the above method for controlling the sending rate of packets, and the computing device can be a terminal, or a chip or chip system inside the terminal. As shown in Figure 7 The computing device 900 includes a processor 910, a memory 920, and a communication interface 930.

[0089] It should be understood that Figure 7 The communication interface 930 in the computing device 900 shown in the figure can be used for communication with other devices, and can specifically include one or more transceiver circuits or interface circuits.

[0090] The processor 910 can be connected with the memory 920. The memory 920 can be used to store the program code and data. Therefore, the memory 920 can be a storage unit inside the processor 910, can be an external storage unit independent of the processor 910, or can be a component including the storage unit inside the processor 910 and the external storage unit independent of the processor 910.

[0091] Optionally, the computing device 900 can further include a bus. The memory 920 and the communication interface 930 can be connected with the processor 910 through the bus. The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 4 In the figure, a line without an arrow is used to represent one bus, but it does not mean that there is only one bus or only one type of bus.

[0092] It should be understood that, in the embodiments of the present application, the processor 910 can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. Alternatively, the processor 910 uses one or more integrated circuits to execute related programs to implement the technical solutions provided by the embodiments of the present application.

[0093] The memory 920 can include read-only memories and random access memories, and provide instructions and data for the processor 910. A part of the processor 910 can also include a non-volatile random access memory. For example, the processor 910 can also store device type information.

[0094] When the computing device 900 is running, the processor 910 executes the computer execution instructions in the memory 920 to perform any operation steps of the above method and any optional embodiments thereof.

[0095] It should be understood that the computing device 900 according to the embodiments of the present application can correspond to the respective subject performing the method according to the embodiments of the present application, and the above and other operations and / or functions of the various modules in the computing device 900 are respectively for realizing the respective processes of the method according to the embodiments of the present application, and for brevity, will not be repeated here.

[0096] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0097] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0098] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0099] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0100] In addition, each functional unit in the embodiments of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0101] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0102] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program. The program is executed by a processor to perform the above method, which includes at least one of the schemes described in the above embodiments.

[0103] The computer storage medium of the embodiments of the present application can adopt any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples (non-exhaustive list) of the computer readable storage medium include: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus.

[0104] The computer readable signal medium can include a data signal propagated in a baseband or as a part of a carrier wave, in which a computer readable program code is borne. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination of the above. The computer readable signal medium can also be any computer readable medium other than the computer readable storage medium, which can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or apparatus.

[0105] The program code embodied on the computer readable media can be transmitted using any appropriate medium, including but not limited to wireless, wire line, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0106] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0107] In addition, the use of the terms "first", "second", "third" and the like in the description and the claims to refer to a number of steps in a method in the description and the claims, or modules A, B, C and the like in the description and the claims, is only to identify such steps or modules as they occur in the description or claims and does not require or imply that the steps or modules are to be performed in this order, unless the order is explicitly required by the description or the claims.

[0108] In the description above, reference has been made to steps represented by numerals such as S110, S120, etc. These numerals do not necessarily indicate that the steps are to be performed in the order in which they are described, unless the order is explicitly required by the description or the claims.

[0109] The term "comprising", used in the description and the claims, should not be interpreted as limiting to the contents listed thereafter; it does not exclude other elements or steps. It does thus specify the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, nor does it preclude a combination of two or more features, integers, steps or components in one or more claims. The term "comprising" should therefore be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, nor does it preclude a combination of two or more features, integers, steps or components in one or more claims. The expression "device including A and B" should thus not be construed as being limited to devices that consist only of A and B, but it should be interpreted as meaning that the device includes A and B.

[0110] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but can refer to different embodiments. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0111] It is noted that the foregoing are merely preferred embodiments of, and the technical principles applied to, the present application. It can be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, and that various obvious changes, modifications and replacements can be made by those skilled in the art without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments only, and can include more other equivalent embodiments without departing from the concept of the present application, and all of them belong to the protection scope of the present application.

Claims

1. A method for controlling a message sending rate, the method comprising: The method comprises the following steps: acquiring a target sending rate of a to-be-sent message; determining a clock cycle simulation signal of a sending end according to the target sending rate of the to-be-sent message; processing the to-be-sent message based on the clock cycle simulation signal of the sending end and a target output bit width of the sending end to obtain at least one message data block, and sending the message data block; wherein the target output bit width of the sending end is determined based on an input bit width of a receiving end; the processing the to-be-sent message based on the clock cycle simulation signal of the sending end and the target output bit width of the sending end to obtain at least one message data block, and sending the message data block comprises: in each cycle of the clock cycle simulation signal of the sending end, deducting a preset number of bytes from a byte stream of the to-be-sent message; when the number of bytes deducted in n cycles of the clock cycle simulation signal of the sending end reaches one time of the target output bit width or when the number of bytes of the byte stream of the to-be-sent message is deducted completely, taking the number of bytes deducted in the n cycles as one message data block for sending according to the target sending rate; wherein n is a positive integer.

2. The method of claim 1, wherein, the determining the clock cycle simulation signal of the sending end according to the target sending rate of the to-be-sent message comprises: determining a clock frequency actual signal of the sending end according to the target sending rate of the to-be-sent message; determining the clock cycle simulation signal of the sending end according to the clock frequency actual signal of the sending end, a clock cycle simulation signal of the receiving end, and a clock frequency actual signal of the receiving end.

3. The method of claim 1, wherein, the method further comprises: when the number of bytes deducted in n cycles of the clock cycle simulation signal of the sending end reaches one time of the target output bit width or when the number of bytes of the byte stream of the to-be-sent message is deducted completely, generating a scheduling flag; wherein the scheduling flag is used to indicate that the sending end is ready for the message data block to be transmitted; sending the scheduling flag, and sending the message data block according to the target sending rate after the receiving end receives the scheduling flag.

4. The method of claim 1, wherein, the method further comprises: when there are multiple parallel sending data streams in the sending end and there is only one receiving data stream in the receiving end, the following steps are performed: respectively processing the multiple sending data streams to obtain respective corresponding message data blocks; after obtaining the respective corresponding message data blocks, generating scheduling flags of the message data blocks, different scheduling flags corresponding to different sending data streams, the scheduling flags being used to indicate that the sending end is ready for the message data block to be transmitted; when multiple different scheduling flags are received in one clock cycle of the receiving end, determining a scheduling order of the message data blocks corresponding to the different scheduling flags according to a pre-set rule; sending the message data blocks in sequence according to the scheduling order; wherein one sending data stream corresponds to one or more to-be-sent messages.

5. The method of claim 1, wherein, the method further comprises: when there are multiple receiving data streams in the receiving end, the multiple receiving data streams run simultaneously.

6. The method of claim 1, wherein, The packet sending further comprises a burst mode, in which the average sending rate of the to-be-sent packet is controlled to be equal to the target sending rate.

7. The method of claim 6, wherein, The controlling of the average sending rate of the to-be-sent packet to be equal to the target sending rate comprises: configuring a required burst data amount, the burst data amount not exceeding the target output bit width; in an acceleration stage of packet sending, when a preset number of bytes deducted from the byte stream of the to-be-sent packet reaches the burst data amount within a clock cycle of the sending end, a flag is generated to indicate that the to-be-sent packet data is sent in advance; in a deceleration stage of packet sending, after the burst data amount is delayed, a new packet deduction count is started.

8. A rate controller characterized by, The rate controller is configured to send the to-be-sent packet at the target sending rate based on configuration data input through the interfaces and by performing the method of any one of claims 1-7; The interfaces comprise: a first interface configured to configure a target sending rate of the to-be-sent packet; a second interface configured to configure a clock cycle simulation signal of the receiving end; a third interface configured to configure a clock frequency actual signal of the receiving end; a fourth interface configured to configure a packet length of the to-be-sent packet; a fifth interface configured to configure a target output bit width of the sending end; a sixth interface configured to configure a burst data amount in the burst mode.

9. A device for controlling the message transmission rate, characterized in that, The rate controller is configured to configure a target sending rate for the to-be-sent packet according to the method of any one of claims 1-7; a scheduler configured to determine a sending order of the packet stream according to a pre-configured scheduling order rule when there are multiple parallel sending data streams in the sending end and there is only one receiving data stream in the receiving end; and a driver configured to send the packet according to the target output bit width and the target sending rate. ​ ​

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