Semiconductor structure and preparation method thereof

Abstract

The present disclosure relates to a semiconductor structure and a method for preparing the same. The method comprises: providing a substrate, alternately stacking multiple layers of sacrificial material layers and multiple layers of semiconductor material layers on the substrate; patterning the multiple layers of sacrificial material layers and multiple layers of semiconductor material layers to form multiple isolation trenches spaced apart in a first direction, and multiple layers of sacrificial layers and multiple layers of semiconductor layers located on both sides of each isolation trench along the first direction; filling the isolation trench with a spin-on dielectric material, and performing an annealing process on the resulting structure to form a first damage layer on the surface of the sacrificial layer in contact with the spin-on dielectric material; patterning the spin-on dielectric material to form at least two support definition holes spaced apart in a second direction, and exposing the first damage layer of the first target area through the support definition holes; removing the first damage layer of the first target area; and forming a support structure in the support definition holes and the first target area. The present disclosure is conducive to improving the production yield, performance and reliability of semiconductor structures.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of a number of memory cells arranged in an array. Furthermore, as the demand for memory capacity and storage density continues to increase, the memory cells are increasingly being arranged in three dimensions (3D).

[0003] Currently, 3D-DRAM typically requires a support structure to support the structure after removing the sacrificial layer, facilitating subsequent processing. However, due to limitations in current 3D-DRAM structures and processes, such as simple hole-forming processes and lateral etching of the sacrificial layer, problems such as shape irregularities and stress concentration can easily occur, leading to degradation of device performance or other unpredictable effects, thus impacting production yield and device reliability. Summary of the Invention

[0004] Based on this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are beneficial to improving the production yield, performance and reliability of the semiconductor structure.

[0005] On the one hand, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising the following steps.

[0006] A substrate is provided, and multiple sacrificial material layers and multiple semiconductor material layers are alternately stacked on the substrate.

[0007] The multi-layer sacrificial material layer and the multi-layer semiconductor material layer are patterned to form a plurality of isolation trenches spaced apart in a first direction, and the multi-layer sacrificial layer and the multi-layer semiconductor layer are located on both sides of each isolation trench along the first direction.

[0008] The isolation trench is filled with a spin-on dielectric material, and an annealing process is performed on the resulting structure to form a first damaged layer based on an in-situ reaction on the surface of the sacrificial layer in contact with the spin-on dielectric material.

[0009] The dielectric material is patterned and spin-coated to form at least two support definition holes spaced apart in a second direction, and the support definition holes expose the first damaged layer in the first target area. The second direction intersects the first direction.

[0010] A first damaged layer in a first target area is removed.

[0011] A support structure is formed in the support definition hole and the first target area.

[0012] In some embodiments of the present disclosure, the method for preparing the semiconductor structure further includes the following steps.

[0013] The spin-on dielectric material between two adjacent support structures is removed to form a first etched hole, and the first etched hole exposes the first damaged layer in the second target area.

[0014] The first damaged layer in the second target area is removed.

[0015] The remaining sacrificial layer and the remaining spin-on dielectric material are removed.

[0016] An isolation structure is formed in the first etched hole, the second target area, and the removal area of ​​the residual sacrificial layer and the residual spin-on dielectric material.

[0017] In some embodiments of the present disclosure, the method for preparing the semiconductor structure further includes the following steps.

[0018] Simultaneously, a first damaged layer is formed on a surface of the sacrificial layer in contact with the spin-on dielectric material, and a second damaged layer is formed on a surface of the semiconductor layer in contact with the spin-on dielectric material, wherein a maximum dimension of the second damaged layer in the first direction is less than or equal to a minimum dimension of the first damaged layer in the first direction.

[0019] Accordingly, the first damaged layer and the second damaged layer in the first target area are removed synchronously. The first damaged layer and the second damaged layer in the second target area are removed synchronously.

[0020] In some embodiments of the present disclosure, the method for preparing the semiconductor structure further includes the following steps.

[0021] Before removing the remaining sacrificial layer and the remaining spin-on dielectric material, channel doping is performed on the semiconductor layer based on the surface of the semiconductor layer exposed by the first etched hole and the second target area.

[0022] In some embodiments of the present disclosure, the method for preparing the semiconductor structure further includes the following steps.

[0023] The isolation structure is self-aligned and etched based on the interval between two adjacent support structures to form a second etched hole.

[0024] The sidewall of the isolation structure is etched along the first direction based on the second etched hole to expose the end of the semiconductor layer in the first direction and obtain a word line definition hole.

[0025] A gate dielectric layer is formed to cover the end portion of the semiconductor layer exposed in the word line defining hole.

[0026] A word line covering the gate dielectric layer is formed in the word line definition hole.

[0027] In some embodiments of the present disclosure, the word line definition hole is located between semiconductor layers on both sides of the same isolation trench. The method for preparing the semiconductor structure further includes the following steps.

[0028] A separation hole is formed which penetrates the word line in a direction perpendicular to the substrate and extends in a second direction.

[0029] A separation structure is formed in the separation hole; the separation structure separates the word line into a first word line and a second word line corresponding to the semiconductor layers on both sides.

[0030] In some embodiments of the present disclosure, the end portion of the semiconductor layer exposed in the word line defining hole has a first length in the first direction, a second length in the first direction, and the first length is less than or equal to one third of the second length.

[0031] In some embodiments of the present disclosure, the sacrificial layer includes a silicon germanium layer, and the semiconductor layer includes a silicon layer.

[0032] On the other hand, the embodiments of the present disclosure further provide a semiconductor structure that can be prepared using the semiconductor structure preparation methods described in some of the above embodiments.

[0033] The semiconductor structure includes: a substrate and a plurality of repeating units and a plurality of support structures arranged on the substrate. The plurality of repeating units are arranged at intervals along a first direction on the substrate. The repeating units include: a plurality of semiconductor layers arranged along a direction perpendicular to the substrate, and an isolation structure located between any two adjacent semiconductor layers. The support structure is located in the interval between two adjacent repeating units and contacts the side walls of the semiconductor layer and the isolation structure extending along the second direction. The second direction intersects with the first direction. The surface of the support structure contacting the isolation structure is curved and protrudes toward the isolation structure, and the top surface and bottom surface of the protruding portion of the support structure toward the isolation structure are in contact with the corresponding surfaces between the two adjacent semiconductor layers, respectively.

[0034] In some embodiments of the present disclosure, a maximum dimension of a portion of the support structure protruding toward the isolation structure in the first direction is less than or equal to one third of a dimension of the semiconductor layer in the first direction.

[0035] The embodiments of the present disclosure may or may have at least the following advantages:

[0036] In the embodiment of the present disclosure, after the spin-on dielectric material is filled in the isolation trench, an annealing process of the spin-on dielectric material can be performed to cause an in-situ reaction between the surface of the sacrificial layer and the surface in contact with the spin-on dielectric material to form a first damaged layer. In this way, after forming the support definition hole and removing the first damaged layer exposed to the first target area in the support definition hole, it is easy to ensure that the accommodation space formed on one side of the sidewall of each layer of the sacrificial layer has a regular shape and is evenly distributed to accommodate the protruding support portion of the support structure, that is, the surface shape of the support structure can be correspondingly defined to simplify the process of the support structure and avoid problems such as irregular surface shape or stress concentration in the support structure; thereby effectively improving the production yield, performance and reliability of the semiconductor structure.

[0037] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A flowchart of a method for preparing a semiconductor structure provided in some embodiments;

[0040] Figure 2 A flowchart of another method for preparing a semiconductor structure provided in some embodiments;

[0041] Figure 3 A flowchart of another method for preparing a semiconductor structure provided in some embodiments;

[0042] Figure 4 A schematic structural diagram of a structure obtained after forming various sacrificial material layers and various semiconductor material layers, provided in some embodiments;

[0043] Figure 5 is a schematic structural diagram of a semiconductor structure obtained after forming an isolation trench provided in some embodiments;

[0044] Figure 6 A schematic structural diagram of a semiconductor structure obtained after forming a spin-on dielectric material provided in some embodiments;

[0045] Figure 7A schematic structural diagram of a semiconductor structure obtained after forming a first damaged layer and a second damaged layer, provided in some embodiments;

[0046] Figure 8 A schematic structural diagram of a semiconductor structure obtained after forming a support-defining hole provided in some embodiments;

[0047] Figure 9 A schematic structural diagram of a semiconductor structure obtained after removing a first damaged layer and a second damaged layer in a first target region provided in some embodiments;

[0048] Figure 10 A schematic structural diagram of a semiconductor structure obtained after forming a support structure provided in some embodiments;

[0049] Figure 11 A schematic structural diagram of a semiconductor structure obtained after forming a first etched hole and removing a first damaged layer and a second damaged layer in a second target region, provided in some embodiments;

[0050] Figure 12 A schematic structural diagram of a semiconductor structure obtained after removing a residual sacrificial layer and a residual spin-on dielectric material provided in some embodiments;

[0051] Figure 13 A schematic structural diagram of a semiconductor structure obtained after forming an isolation structure provided in some embodiments;

[0052] Figure 14 A schematic structural diagram of a semiconductor structure obtained after forming a second etched hole provided in some embodiments;

[0053] Figure 15 A schematic structural diagram of a semiconductor structure obtained after forming a word line definition hole provided in some embodiments;

[0054] Figure 16 A schematic structural diagram of a semiconductor structure obtained after forming a gate dielectric layer and a word line, provided in some embodiments;

[0055] Figure 17 Schematic diagram of a semiconductor structure obtained after forming a first word line and a second word line provided in some embodiments.

[0056] Description of reference numerals:

[0057] 1-substrate, U-repeating unit, L1-sacrificial material layer, L2-semiconductor material layer, L3-insulating material layer, YM-hard mask layer, 11-sacrificial layer, 12-semiconductor layer, 111-first damaged layer, 121-second damaged layer, 2-spin-on dielectric material, 3-support structure, 4-isolation structure, 5-gate dielectric layer, 6-separation structure, WL-word line, WL1-first word line, WL2-second word line, U-repeating unit, G-isolation trench, H1-support definition hole, H2-first etching hole, H3-second etching hole, H4-word line definition hole, R1-first target area, R2-second target area, D1-first length, D2-second length. DETAILED DESCRIPTION

[0058] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0060] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "electrically connected to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0061] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present disclosure should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0063] In 3D-DRAM, a support structure is typically required to support the structure after removing the sacrificial layer, facilitating subsequent processing. However, due to limitations in current 3D-DRAM structures and processes, such as simple hole-forming processes and lateral etching of the sacrificial layer, problems such as irregular shapes and stress concentration can easily occur, leading to degradation of device performance or other unpredictable effects, thus impacting production yield and device reliability.

[0064] Based on this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can effectively improve the production yield, performance and reliability of the semiconductor structure.

[0065] See also Figure 1 The method for preparing a semiconductor structure provided in an embodiment of the present disclosure includes the following steps.

[0066] S100 , providing a substrate, and alternately stacking multiple sacrificial material layers and multiple semiconductor material layers on the substrate.

[0067] S110 , patterning multiple sacrificial material layers and multiple semiconductor material layers to form multiple isolation trenches spaced apart in a first direction, and multiple sacrificial layers and multiple semiconductor layers located on both sides of each isolation trench along the first direction.

[0068] S120 , filling the isolation trench with a spin-on dielectric material, and performing an annealing process on the resulting structure to form a first damaged layer based on an in-situ reaction on the surface of the sacrificial layer in contact with the spin-on dielectric material.

[0069] S130, patterning and spin-coating a dielectric material to form at least two support definition holes spaced apart in a second direction, and exposing the first damaged layer in the first target area through the support definition holes. The second direction intersects the first direction.

[0070] S140, removing the first damaged layer in the first target area.

[0071] S150, forming a support structure in the support definition hole and the first target area.

[0072] In the disclosed embodiments, a spin-on dielectric (SOD) material exhibits excellent hole-filling capabilities and localized planarization. Filling the isolation trenches with the SOD material can form a film with superior properties, such as the ability to fill minute gaps and form an extremely thin insulating layer within them. Consequently, the disclosed embodiments utilize SOD to fill the isolation trenches, facilitating a wider process operating range and reducing production equipment costs.

[0073] In some embodiments, the spin-on dielectric material can be spin-coated using a liquid solvent to ensure uniform coating. Furthermore, after the isolation trench is filled with the spin-on dielectric material, an annealing process is performed on the resulting structure to form a cured silicon dioxide (SiO2)-like dielectric film on the inner wall of the isolation trench.

[0074] Illustratively, the sacrificial layer includes a silicon germanium (SiGe) layer, and the semiconductor layer includes a silicon (Si) layer.

[0075] Accordingly, after the spin-on dielectric material is filled in the isolation trench and the resulting structure is annealed, the performance of the sacrificial layer and the semiconductor layer during the annealing process is quite different, specifically: during the annealing process, the Ge-Ge weak bond of the sacrificial layer is preferentially destroyed by H (hydrogen) and forms a Ge-H bond, and then the remaining Ge forms a Ge-O bond, so that the surface of the sacrificial layer in contact with the spin-on dielectric material forms a first damage layer. At this time, by performing lens electroscanning (Transmission Electron Microscope, referred to as TEM) on the semiconductor structure, it can be found that: compared with the semiconductor layer, the sacrificial layer will have more damage during the annealing process of the spin-on dielectric material to form a first damage layer. Based on this, through the difference in damage between the semiconductor layer and the sacrificial layer during the annealing process of the spin-on dielectric material, after the damaged portion of the corresponding area (such as the first damaged layer of the first target area) is subsequently removed, a accommodating space similar to the back-etched sidewall can be formed on one side of the sidewall of the semiconductor layer and the sacrificial layer to accommodate the protruding support portion of the support structure.

[0076] It can be understood that a first damaged layer is formed on the surface of each sacrificial layer in contact with the spin-on dielectric material. This first damaged layer originates from the in-situ reaction between the weak Ge-Ge bonds in the silicon-germanium material and the hydrogen (H) and oxygen (O) in the spin-on dielectric material. Therefore, after forming the first damaged layer using the preparation method provided by the embodiment of the present disclosure, the first damaged layer of each sacrificial layer has a regular shape and is evenly distributed, effectively avoiding problems such as irregular shape or stress concentration caused by simple hole opening processes and sacrificial layer lateral etching processes.

[0077] As described above, after the isolation trench is filled with the spin-on dielectric material, the embodiment of the present disclosure can be subjected to an annealing process for the spin-on dielectric material, so that the surface where the sacrificial layer contacts the spin-on dielectric material undergoes an in-situ reaction to form a first damaged layer. In this way, after forming the support definition hole and removing the first damaged layer exposed to the first target area in the support definition hole, it is easy to ensure that the accommodation space formed on one side of the sidewall of each layer of the sacrificial layer has a regular shape and is evenly distributed to accommodate the protruding support portion of the support structure, that is, the surface shape of the support structure can be correspondingly defined to simplify the process of the support structure and avoid problems such as irregular surface shape or stress concentration in the support structure; thereby effectively improving the production yield, performance and reliability of the semiconductor structure.

[0078] In some embodiments of the present disclosure, please refer to Figure 2 , the method for preparing the semiconductor structure also includes the following steps.

[0079] S160 , removing the spin-on dielectric material between two adjacent support structures to form a first etched hole, and exposing the first damaged layer in the second target area through the first etched hole.

[0080] S170, removing the first damaged layer in the second target area.

[0081] S180 , removing the remaining sacrificial layer and the remaining spin-on dielectric material.

[0082] S190 , forming an isolation structure in the first etched hole, the second target area, and the area where the residual sacrificial layer and the residual spin-on dielectric material are removed.

[0083] It should be added that, in some embodiments of the present disclosure, the method for preparing the semiconductor structure further includes the following steps.

[0084] During step S120, a first damaged layer is formed on the surface of the sacrificial layer in contact with the spin-on dielectric material, and a second damaged layer is formed on the surface of the semiconductor layer in contact with the spin-on dielectric material. Accordingly, in step 140, the first damaged layer and the second damaged layer are simultaneously removed from the first target area. In step S170, the first damaged layer and the second damaged layer are simultaneously removed from the second target area.

[0085] It is understood that during the annealing process of the spin-on dielectric material, the surface of the semiconductor layer in contact with the spin-on dielectric material will also be damaged, forming a second damaged layer. However, because the amount of damage to the semiconductor layer is much less than that to the sacrificial layer, the average size of the second damaged layer on one side of the semiconductor layer sidewall (e.g., in the first direction) is relatively smaller than the average size of the first damaged layer in the same direction.

[0086] Illustratively, a maximum dimension of the second damaged layer in the first direction is smaller than or equal to a minimum dimension of the first damaged layer in the first direction.

[0087] In some embodiments of the present disclosure, please continue to refer to Figure 2 , the method for preparing the semiconductor structure also includes the following steps.

[0088] S175 , before removing the remaining sacrificial layer and the remaining spin-on dielectric material, performing channel doping on the semiconductor layer based on the surface of the semiconductor layer exposed by the first etched hole and the second target area.

[0089] For example, the semiconductor material layer formed in step S100 may be a lightly doped silicon layer. The channel doping of the semiconductor layer in step S175 specifically includes heavily doping the surface of the semiconductor layer exposed to the first etching hole and the second target area.

[0090] For example, the lightly doped type of the semiconductor material layer and the heavily doped type of the semiconductor layer channel are the same, that is, ions with the same conductivity type may be used for doping.

[0091] In some embodiments of the present disclosure, please refer to Figure 3 , the method for preparing the semiconductor structure also includes the following steps.

[0092] S200 , etching the isolation structure in a self-aligned manner based on the interval between two adjacent support structures to form a second etching hole.

[0093] S210 , etching the sidewall of the isolation structure along the first direction based on the second etched hole to expose the end of the semiconductor layer in the first direction and obtain a word line definition hole.

[0094] S220 , forming a gate dielectric layer covering the end portion of the semiconductor layer exposed in the word line defining hole.

[0095] S230 , forming a word line covering the gate dielectric layer in the word line definition hole.

[0096] In some embodiments of the present disclosure, please continue to refer to Figure 3 The word line definition hole is located between the semiconductor layers on both sides of the same isolation trench. The method for preparing the semiconductor structure further includes the following steps.

[0097] S240 , forming a separation hole penetrating the word line and extending along the second direction.

[0098] S250 , forming a separation structure in the separation hole; the separation structure separates the word line into a first word line and a second word line corresponding to the semiconductor layers on both sides.

[0099] In some embodiments of the present disclosure, the end portion of the semiconductor layer exposed in the word line defining hole has a first length in the first direction, a second length in the first direction, and the first length is less than or equal to one third of the second length.

[0100] It should be understood that although the above Figures 1 to 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figures 1 to 3 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0101] In order to more clearly illustrate the method for preparing the semiconductor structure in some of the above embodiments, Figures 4 to 16 Understand some embodiments of the present disclosure.

[0102] In step S100, refer to Figure 4 In Figures (a) and (b), a substrate 1 is provided, and multiple sacrificial material layers L1 and multiple semiconductor material layers L2 are alternately stacked on the substrate 1. Figure 4 Figure (b) is Figure 4 Figure (a) shows a cross-sectional structure diagram along the AA direction.

[0103] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0104] For example, the number of stacked layers of sacrificial material layer L1 and semiconductor material layer L2 can be set as needed. Furthermore, the alternating stacking of sacrificial material layer L1 and semiconductor material layer L2 can begin with sacrificial material layer L1 and end with semiconductor material layer L2. However, this is not limited to this. For example, starting with semiconductor material layer L2 and ending with sacrificial material layer L1; or starting with sacrificial material layer L1 and ending with sacrificial material layer L1, etc. are all permissible. It should be understood that in the example of starting with semiconductor material layer L2, semiconductor material layer L2 should be insulated from substrate 1.

[0105] In some examples, the sacrificial material layer L1 includes, but is not limited to, a silicon germanium layer.

[0106] In some examples, the semiconductor material layer L2 includes, but is not limited to, a silicon layer.

[0107] For further example, the semiconductor material layer L2 comprises a lightly doped silicon layer. The disclosed embodiments do not limit the doping type of the semiconductor material layer L2; for example, it can be either P-type or N-type. Furthermore, the doping of any semiconductor material layer L2 can be performed simultaneously during its deposition or after it is deposited as a thin film.

[0108] For some examples, see Figure 4 For example, the film layers deposited on substrate 1 start with a sacrificial material layer L1 and end with a semiconductor material layer L2. Furthermore, the film layers deposited on substrate 1 may further include an insulating material layer L3 covering the top semiconductor material layer L2. The insulating material layer L3 includes, but is not limited to, a silicon oxide layer.

[0109] For some examples, see Figure 4 Each film layer deposited on the substrate 1 may further include a protective layer covering the insulating material layer L3, such as a hard mask layer YM. For example, the hard mask layer YM includes but is not limited to a silicon nitride layer.

[0110] In step S110, please combine Figure 4 and Figure 5 It is understood that the multi-layer sacrificial material layer L1 and the multi-layer semiconductor material layer L2 are patterned to form a plurality of isolation trenches G spaced apart in a first direction (e.g., X direction), and a multi-layer sacrificial layer 11 and a multi-layer semiconductor layer 12 located on both sides of each isolation trench G along the first direction (e.g., X direction). Figure 5 Figure (b) is Figure 5 Figure (a) shows a cross-sectional structure diagram along the AA direction.

[0111] Here, the isolation trench G is used to divide the active area and can accommodate isolation materials to form a shallow trench isolation (STI) structure. In addition, the distribution of the isolation trench G can be implemented in various ways to match the different distributions of the active area.

[0112] For example, Figure 5 As shown in FIG. (a) and FIG. (b), the isolation trench G may extend along the second direction (eg, the Y direction) and separate each sacrificial material layer L1 and the semiconductor material layer L2 into Figure 5 The pattern shown in Figure (a) is that each sacrificial material layer L1 and semiconductor material layer L2 is separated into a plurality of parallel and spaced branches.

[0113] In step S120, refer to Figure 6 and Figure 7 , filling the isolation trench G with a spin-on dielectric material 2, and performing an annealing process on the resulting structure to form a first damaged layer 111 based on an in-situ reaction on the surface of the sacrificial layer 11 in contact with the spin-on dielectric material 2. Figure 6 Figure (b) is Figure 6 Figure (a) shows a cross-sectional structure diagram along the AA direction.

[0114] Here, it can be understood that while the first damaged layer 111 is formed on the surface of the sacrificial layer 11 in contact with the spin-on dielectric material 2 , the second damaged layer 121 is also formed on the surface of the semiconductor layer 12 in contact with the spin-on dielectric material 2 .

[0115] Moreover, in combination with the aforementioned formation mechanisms of the first damaged layer 111 and the second damaged layer 121, the amount of damage to the semiconductor layer 12 is much smaller than the amount of damage to the sacrificial layer 11. Therefore, the average size of the second damaged layer 121 on one side of the side wall of the semiconductor layer 12 (for example, in the first direction) will be relatively smaller than the average size of the first damaged layer 111 in the same direction.

[0116] Here, the contour shapes of the first damaged layer 111 and the second damaged layer 121 are matched, and the average size of the two in the first direction can be determined by measuring a plurality of corresponding sampling values ​​and calculating the average value.

[0117] For examples, see Figure 7 The maximum dimension D of the second damaged layer 121 in the first direction (eg, X direction) is 2max The minimum dimension D of the first damaged layer 111 in the first direction (eg, X direction) may be less than or equal to 1min . Figure 7 China-Israel D 2max =D 1min As an example, it is understood that D 2max <D1min , which is also achievable.

[0118] In step S130, refer to Figure 8 In Figures (a) and (b), a dielectric material 2 is patterned and spin-coated to form at least two support definition holes (H1) spaced apart in a second direction (e.g., the Y direction), and the support definition holes (H1) expose the first damaged layer 111 in the first target region R1. The second direction (e.g., the Y direction) and the first direction (e.g., the X direction) intersect, for example, are orthogonal. Figure 8 Figure (b) is Figure 8 Figure (a) shows a cross-sectional structure diagram along the AA direction.

[0119] Here, the first target region R1 refers to a spatial region where the first damaged layer 111 and the second damaged layer 121 are located and exposed in the support definition hole H1 after the support definition hole H1 is formed.

[0120] Furthermore, the support definition holes H1 are used to define the locations where subsequent support structures are formed. The spacing between adjacent support definition holes H1 and the size parameters of each support definition hole H1 can be set to match the needs. Furthermore, the size parameters of adjacent support definition holes H1 can be the same or different.

[0121] In step S140, refer to Figure 9 In FIG. (a) and FIG. (b), the first damaged layer 111 in the first target region R1 is removed. Figure 9 Figure (b) is Figure 9 Figure (a) shows a cross-sectional structure diagram along the AA direction.

[0122] Here, the second damaged layer 121 in the first target region R1 can be removed simultaneously with the first damaged layer 111 in the region.

[0123] In addition, it can be understood that while removing the first damaged layer 111 and the second damaged layer 121, the spin-on dielectric material 2 remaining between adjacent support definition holes H1 and outside the support definition holes H1 along the second direction (e.g., the Y direction) will also be partially etched away, for example Figure 9 The spin-on dielectric material 2 in the M1 region and the M2 region shown in FIG (a) corresponds to the etched extension region of the support definition hole H1, that is, the region that can serve as the component of the final morphology of the support definition hole H1.

[0124] In other embodiments, while removing the first damaged layer 111 and the second damaged layer 121, it is also allowed to retain the spin-coated dielectric material 2 between adjacent support definition holes H1 and outside the support definition hole H1 along the second direction (for example, the Y direction) without etching loss.

[0125] For example, the first damaged layer 111 and the second damaged layer 121 are removed by wet etching. The etching solutions of the first damaged layer 111 and the second damaged layer 121 can be matched with the material selection settings.

[0126] For example, the first damaged layer 111 and the second damaged layer 121 include but are not limited to silicon oxide layers.

[0127] In step S150, refer to Figure 10 In FIG. (a) and FIG. (b), a support structure 3 is formed in the support definition hole H1 and the first target area R1. Figure 10 Figure (b) is Figure 10 Figure (a) shows a cross-sectional structure diagram along the AA direction.

[0128] For example, the support structure 3 includes but is not limited to a silicon nitride layer, and may also be a silicon carbonitride layer.

[0129] Illustratively, the top surface of the support structure 3 is flush with the top surface of the hard mask layer YM.

[0130] In steps S160 and S170, please refer to Figure 11 In Figures (a) and (b), the spin-on dielectric material 2 between two adjacent support structures 3 in the second direction (e.g., the Y direction) is removed to form a first etched hole H2, and the first etched hole H2 exposes the first damaged layer 111 of the second target region R2; the first damaged layer 111 of the second target region R2 is removed. Figure 11 Figure (b) is Figure 11 Figure (a) shows a cross-sectional structure diagram along the BB direction.

[0131] Here, the second damaged layer 121 in the second target region R2 can be removed simultaneously with the first damaged layer 111 in the region.

[0132] In addition, the second target region R2 refers to a spatial region where the first damaged layer 111 and the second damaged layer 121 are located after the first etching hole H2 is formed.

[0133] In step S175, please combine Figure 11 It is understood that channel doping is performed on the semiconductor layer 12 based on the surface of the semiconductor layer 12 exposed by the first etching hole H2 and the second target region R2.

[0134] For example, the semiconductor material layer L2 formed in step S100 may be a lightly doped silicon layer. Here, performing channel doping on the semiconductor layer 12 specifically includes heavily doping the surface of the semiconductor layer 12 exposed to the first etching hole H2 and the second target region R2.

[0135] For example, the lightly doped type of the semiconductor material layer L2 is the same as the heavily doped type of the channel of the semiconductor layer 12, that is, ions of the same conductivity type can be used for doping. Moreover, the doping concentration of the heavily doped channel in the semiconductor layer 12 can be set as required.

[0136] In step S180, refer to Figure 12 As shown in FIG. (a), FIG. (b) and FIG. (c), the remaining sacrificial layer 11 and the remaining spin-on dielectric material 2 are removed. Figure 12 Figure (b) is Figure 12 The structure shown in Figure (a) is a cross-sectional structure diagram along the AA direction. Figure 12 Figure (c) in the figure is Figure 12 Figure (a) shows a cross-sectional structure diagram along the BB direction.

[0137] Here, it can be understood that after forming the aforementioned first etching hole H2, the first etching hole H2 penetrates each sacrificial layer 11 and the semiconductor layer 12 in a direction perpendicular to the substrate 1, and the remaining sacrificial layers 11 can be effectively removed based on the first etching hole H2.

[0138] In addition, the top surface of the residual spin-on dielectric material 2 is exposed and can be directly etched away. Figure 12 The M3 region in (a) of FIG.

[0139] In step S190, refer to Figure 13 In FIG. (a), (b) and (c), an isolation structure 4 is formed in the first etch hole H2, the second target region R2 and the removal area of ​​the residual sacrificial layer 11 and the residual spin-on dielectric material 2. Figure 13 Figure (b) is Figure 13 The structure shown in Figure (a) is a cross-sectional structure diagram along the AA direction. Figure 13 Figure (c) is Figure 13 Figure (a) shows a cross-sectional structure diagram along the BB direction.

[0140] Illustratively, the isolation structure 4 includes but is not limited to a silicon oxide layer.

[0141] In step S200, refer to Figure 14In FIG. (a), (b) and (c), the isolation structure 4 is self-aligned and etched based on the interval between two adjacent support structures 3 in the second direction (eg, the Y direction), thereby forming a second etched hole H3. Figure 14 Figure (b) is Figure 14 The structure shown in Figure (a) is a cross-sectional structure diagram along the AA direction. Figure 14 Figure (c) in the figure is Figure 14 Figure (a) shows a cross-sectional structure diagram along the BB direction.

[0142] For example, the second etched hole H3 may have the same morphology as the first etched hole H2 mentioned in some of the aforementioned embodiments.

[0143] In step S210, refer to Figure 15 In FIG. (a), (b) and (c), the sidewall of the isolation structure 4 is etched along the first direction (e.g., X direction) based on the second etch hole H3 to expose the end of the semiconductor layer 12 in the first direction (e.g., X direction) and obtain the word line definition hole H4. Figure 15 Figure (b) is Figure 15 The structure shown in Figure (a) is a cross-sectional structure diagram along the AA direction. Figure 15 Figure (c) in the figure is Figure 15 Figure (a) shows a cross-sectional structure diagram along the BB direction.

[0144] For example, see Figure 15 In FIG. 3 , the end portion of the semiconductor layer 12 exposed within the wordline defining hole H4 has a first length D1 in a first direction (e.g., the X direction). The semiconductor layer 12 has a second length D2 in the first direction (e.g., the X direction). The first length D1 is less than or equal to one-third of the second length D2.

[0145] It can be understood that in the embodiment of the present disclosure, the first length D1 is controlled to be less than or equal to one-third of the second length D2, and a portion of lightly doped bulk silicon occupying at least one-third of the second length D2 can be reserved in the middle region of the semiconductor layer 12. Furthermore, for example, the lightly doped bulk silicon in the semiconductor layer 12 and the heavily doped channel in the semiconductor layer 12 use the same doping type. This can effectively address the floating body effect of the channel in the semiconductor layer 12 after the lightly doped bulk silicon in the semiconductor layer 12 is subsequently connected to the ground voltage terminal, thereby improving the performance of the transistor in which the semiconductor layer 12 is located and the corresponding semiconductor structure.

[0146] In addition, in the related art, a full-surround gate is usually formed around the semiconductor layer 12. For example, the isolation structure 4 formed in the aforementioned step S190 can be completely removed to form a gate dielectric layer and a gate (such as a word line) on the entire exposed surface of the semiconductor layer 12. However, in the embodiment of the present disclosure, based on the second etching hole H3, the sidewall of the isolation structure 4 is etched along the first direction (such as the X direction) to form the word line definition hole H4. The isolation structure 4 can be retained between the semiconductor layers 12 adjacent in the direction perpendicular to the substrate 1, so as to utilize the isolation structure 4 for auxiliary support. That is, the embodiment of the present disclosure can utilize the isolation structure 4 retained between the semiconductor layers 12 adjacent in the direction perpendicular to the substrate 1 in conjunction with the support structure 3 to jointly realize the support function, thereby further improving the structural stability and process reliability in the semiconductor structure manufacturing process.

[0147] In step S220 and step S230, please refer to Figure 16 As shown in FIG. (a), (b) and (c), a gate dielectric layer 5 is formed covering the semiconductor layer 12 exposed at the inner end of the word line definition hole H4, and a word line WL covering the gate dielectric layer 5 is formed in the word line definition hole H4. Figure 16 Figure (b) is Figure 16 The structure shown in Figure (a) is a cross-sectional structure diagram along the AA direction. Figure 16 Figure (c) is Figure 16 Figure (a) shows a cross-sectional structure diagram along the BB direction.

[0148] For example, the gate dielectric layer 5 may be formed on the end surface of the semiconductor layer 12 exposed in the word line defining hole H4 by using an epitaxial growth process.

[0149] Illustratively, the gate dielectric layer 5 includes but is not limited to a silicon oxide layer.

[0150] For example, the word line WL is obtained by filling the word line definition hole H4 with a metal material; the metal material is, for example, tungsten or copper.

[0151] It is worth noting that in some embodiments, the word lines WL formed within the word line definition holes H4 can meet the requirements by matching the independent distribution of the semiconductor layers 12 in the first direction (e.g., the X direction). For example, if the semiconductor layers 12 are stacked in an independent column along a direction perpendicular to the substrate 1, the word lines WL formed within the word line definition holes H4 using the aforementioned method can only correspond to the sidewalls of the semiconductor layers 12 in that column, and ensure that the portion of the word line WL corresponding to the sidewall of any semiconductor layer 12 constitutes the corresponding gate of that semiconductor layer 12.

[0152] In other embodiments, the semiconductor layers 12 may be stacked in a direction perpendicular to the substrate 1 and spaced apart into multiple columns in a first direction (e.g., the X direction). Accordingly, after forming the aforementioned word line definition holes H4 and word lines WL, the method for fabricating the corresponding semiconductor structure may further include the following steps.

[0153] In step S240 and step S250, please refer to Figure 17 In (a), (b) and (c), a separation hole ( Figure 17 forming a separation structure 6 in the separation hole. Thus, the separation structure 6 can separate the word line WL formed in the word line definition hole H4 into a first word line WL1 and a second word line WL2 corresponding to the semiconductor layer 12 on both sides. Figure 17 Figure (b) is Figure 17 The structure shown in Figure (a) is a cross-sectional structure diagram along the AA direction. Figure 17 Figure (c) is Figure 17 Figure (a) shows a cross-sectional structure diagram along the BB direction.

[0154] And, combined with Figure 17 As shown in Figure (c), in the semiconductor structure fabricated using the aforementioned method, the first word line WL1 and the second word line WL2 can be located on either side of the corresponding semiconductor layer 12, with their portions located outside the sidewalls of the semiconductor layer 12 forming the two gates of the transistor containing the semiconductor layer 12. That is, the transistor formed based on the semiconductor layer 12 and the first and second word lines WL1 and WL2 adopts a vertical double-sided gate structure. This improves the gate control performance of the transistor, thereby enhancing the performance of the semiconductor structure.

[0155] Illustratively, the separation structure 6 includes, but is not limited to, a silicon nitride layer or a silicon nitride layer.

[0156] Some embodiments of the present disclosure further provide a semiconductor structure that can be prepared using the methods for preparing semiconductor structures described in some of the above embodiments. The semiconductor structure also possesses the technical advantages of the above preparation methods, which will not be described in detail here.

[0157] See also Figure 17As shown in Figures (a), (b), and (c) of the present invention, the semiconductor structure includes: a substrate 1, a plurality of repeating units U, and a plurality of support structures 3 disposed on the substrate. The plurality of repeating units U are spaced apart along a first direction (e.g., the X direction) on the substrate 1. The repeating units U include: a plurality of semiconductor layers 12 disposed along a direction perpendicular to the substrate 1 (e.g., the Z direction), and an isolation structure 4 located between any two adjacent semiconductor layers 12. The support structure 3 is located in the interval between two adjacent repeating units U and contacts the sidewalls of the semiconductor layers 12 and the isolation structure 4 extending along a second direction (e.g., the Y direction).

[0158] Illustratively, the second direction (eg, the Y direction) and the first direction (eg, the X direction) intersect, for example, are orthogonal.

[0159] For example, Figure 17 As shown in Figure (b), the surface of the support structure 3 contacting the isolation structure 4 is curved and protrudes toward the isolation structure 4, and the top and bottom surfaces of the protruding portion of the support structure 3 toward the isolation structure 4 are in contact with the corresponding surfaces between the two adjacent semiconductor layers 12 respectively.

[0160] Here, the surface of the support structure 3 contacting the isolation structure 4 is an arc surface and convex toward the isolation structure 4 , that is, the center of curvature of the arc surface is located inside the support structure 3 .

[0161] For example, the support structure 3 includes but is not limited to a silicon nitride layer, and may also be a silicon carbonitride layer.

[0162] Illustratively, the isolation structure 4 includes but is not limited to a silicon oxide layer.

[0163] In some embodiments of the present disclosure, please continue to refer to Figure 17 In FIG. 3 (b), the maximum dimension of the portion of the support structure 3 protruding toward the isolation structure 4 in the first direction (e.g., the X direction) is less than or equal to one-third of the dimension of the semiconductor layer 12 in the first direction (e.g., the X direction). This facilitates strengthening the support effect of the support structure 3 on the semiconductor layer 12 through the portion of the support structure 3 protruding toward the isolation structure 4.

[0164] In some embodiments of the present disclosure, please continue to refer to Figure 17 In Figures (a) and (c), two support structures 3 can be spaced and arranged side by side along the second direction (e.g., the Y direction) within the interval between two adjacent repeating units U. The semiconductor structure further includes: a first word line WL1, a separation structure 6, and a second word line WL2, located between the two adjacent support structures 3 and sequentially distributed along the first direction (e.g., the X direction); and a gate dielectric layer 5 located between the first word line WL1 and the corresponding semiconductor layer 12, and a gate dielectric layer 5 located between the second word line WL2 and the corresponding semiconductor layer 12.

[0165] For example, the first word line WL1 and the second word line WL2 include but are not limited to metal lines, such as tungsten metal lines or copper metal lines.

[0166] Illustratively, the separation structure 6 includes, but is not limited to, a silicon oxide layer.

[0167] Illustratively, the gate dielectric layer 5 includes but is not limited to a silicon oxide layer.

[0168] For example, the channel in the semiconductor layer 12 is a heavily doped silicon layer. The channel in the semiconductor layer 12 is the portion thereof facing the first word line WL1 and the second word line WL2. Thus, the central portion of the semiconductor layer 12 between the two side channels can be lightly doped bulk silicon.

[0169] For example, the lightly doped silicon in the semiconductor layer 12 can be connected to the ground voltage terminal to effectively solve the floating body effect of the channel in the semiconductor layer 12, thereby helping to improve the performance of the transistor in which the semiconductor layer 12 is located and the corresponding semiconductor structure.

[0170] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0171] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0172] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, and all such variations and improvements fall within the scope of protection of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, and alternately stacking multiple sacrificial material layers and multiple semiconductor material layers on the substrate; Patterning the multi-layer sacrificial material layer and the multi-layer semiconductor material layer to form a plurality of isolation trenches spaced apart in a first direction, and multi-layer sacrificial layers and multi-layer semiconductor layers located on both sides of each isolation trench along the first direction; Filling the isolation trench with a spin-on dielectric material and performing an annealing process on the resulting structure to form a first damaged layer based on an in-situ reaction on a surface of the sacrificial layer in contact with the spin-on dielectric material; Patterning the spin-on dielectric material to form at least two support definition holes spaced apart in a second direction, and exposing the first damaged layer in a first target area through the support definition holes; The second direction intersects the first direction; removing the first damaged layer in the first target area; A support structure is formed in the support definition hole and the first target area.

2. The method for preparing a semiconductor structure according to claim 1, wherein: Also includes: removing the spin-on dielectric material between two adjacent support structures to form a first etched hole, and exposing the first damaged layer in a second target area through the first etched hole; removing the first damaged layer in the second target area; removing the remaining sacrificial layer and the remaining spin-on dielectric material; An isolation structure is formed in the first etch hole, the second target area, and the removed area where the sacrificial layer and the spin-on dielectric material remain.

3. The method for preparing a semiconductor structure according to claim 2, wherein: Also includes: forming the first damaged layer on the surface of the sacrificial layer in contact with the spin-on dielectric material and forming a second damaged layer on the surface of the semiconductor layer in contact with the spin-on dielectric material; The maximum size of the second damaged layer in the first direction is less than or equal to the minimum size of the first damaged layer in the first direction; the first damaged layer and the second damaged layer in the first target area are removed simultaneously; and the first damaged layer and the second damaged layer in the second target area are removed simultaneously.

4. The method for preparing a semiconductor structure according to claim 2, wherein: Also includes: Before removing the remaining sacrificial layer and the remaining spin-on dielectric material, channel doping is performed on the semiconductor layer based on the surface of the semiconductor layer exposed by the first etched hole and the second target area.

5. The method for preparing a semiconductor structure according to claim 2, wherein: Also includes: Self-aligning and etching the isolation structure based on the interval between two adjacent support structures to form a second etching hole; etching the sidewall of the isolation structure along the first direction based on the second etched hole to expose the end of the semiconductor layer in the first direction and obtain a word line definition hole; forming a gate dielectric layer covering an end portion of the semiconductor layer exposed in the word line defining hole; A word line covering the gate dielectric layer is formed in the word line definition hole.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The word line definition hole is located between the semiconductor layers on both sides of the same isolation trench; the preparation method further includes: forming a separation hole penetrating the word line in a direction perpendicular to the substrate and extending along the second direction; A separation structure is formed in the separation hole; the separation structure separates the word line into a first word line and a second word line corresponding to the semiconductor layers on both sides.

7. The method for preparing a semiconductor structure according to claim 5, wherein: The end portion of the semiconductor layer exposed in the word line defining hole has a first length in the first direction; The dimension of the semiconductor layer in the first direction is a second length; The first length is less than or equal to one third of the second length.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, wherein: The sacrificial layer includes a silicon germanium layer; and the semiconductor layer includes a silicon layer.

9. A semiconductor structure prepared according to the preparation method according to any one of claims 1 to 8, characterized in that: include: A substrate and a plurality of repeating units and a plurality of supporting structures arranged on the substrate; wherein, A plurality of the repeating units are arranged at intervals along a first direction on the substrate; the repeating units include: a plurality of semiconductor layers arranged in a direction perpendicular to the substrate, and an isolation structure located between any two adjacent semiconductor layers; The support structure is located in a space between two adjacent repeating units and contacts the semiconductor layer and the sidewall of the isolation structure extending along a second direction; the second direction intersects the first direction; The surface of the support structure contacting the isolation structure is an arc surface and protrudes toward the isolation structure, and the top and bottom surfaces of the protruding portion of the support structure toward the isolation structure respectively contact the opposite surfaces between two adjacent semiconductor layers.

10. The semiconductor structure according to claim 9, wherein: A maximum dimension of a portion of the support structure protruding toward the isolation structure in the first direction is less than or equal to one third of a dimension of the semiconductor layer in the first direction.

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