2T0C-DRAM storage unit, preparation method and storage array
By designing a 2T0C-DRAM memory cell with a ring write transistor and a cylindrical dual-gate read transistor, the problems of limited storage density and low array operation accuracy in the existing technology are solved, achieving higher storage density and more efficient read operations. .
Patent Information
- Application Number
- CN202411500507.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-01-24
AI Technical Summary
The existing 2T0C-DRAM memory cells have limited storage density and low array operation accuracy, resulting in increased power consumption and decreased accuracy of the device's read operation.
Design a 2T0C-DRAM storage unit that includes up and down stacked transistors and double grid reads transistors, the channel layer of the transistor is the four planes that surround the grid surrounding the crystal tube; The road layer is a cylindrical shape, surrounded by the side and bottom surface of the first gate of the double grid read the transistor.
Through this design, the density of transistors and storage density are increased, the impact of electrical signals on the channel layer during read operations is reduced, the problem of potential current and voltage path drop is reduced, and the working efficiency and resistance of the memory unit are improved. Interference ability.
Smart Images
Figure CN119364762A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of dynamic random access memory (DRAM), and more specifically, to a 2T0C-DRAM storage unit, a preparation method and a storage array. Background Art
[0002] In the 2T0C (2Transistor-0Capacitor)-DRAM architecture, the memory cell of the memory device is composed of two transistors. One transistor is responsible for the read operation and the other transistor is responsible for the write operation. This 2T0C-DRAM architecture avoids the presence of capacitors in the memory cell, so it is expected to overcome the problems that arise in 1T1C-DRAM when scaling the process size, mainly including that as the memory size decreases, the leakage risk of the capacitor increases further; and the complexity of the process increases exponentially as the capacitor size decreases, which greatly increases the cost.
[0003] However, the current 2T0C-DRAM architecture still has some problems, which hinders its manufacture and application. In the structure of the 2T0C-DRAM unit, the write transistor and the read transistor are located side by side on the same horizontal plane, and the drain of the write transistor is connected to the gate of the read transistor through the upper wiring to form a storage node (SN). Due to the relatively complex structure of the transistor, it is difficult to fold it like a capacitor to reduce the planar size of a single unit, which significantly reduces the storage density of the device; and the number of line connections required for the 2T0C-DRAM unit is more and the connection method is more complicated, which makes the 2T0C-DRAM have more obvious potential current and voltage path drop problems when forming a storage array, which in turn increases the power consumption and reduces the accuracy of the device's read operation.
[0004] Therefore, how to reduce the footprint of 2T0C-DRAM memory cells and solve a series of problems caused by the complex structure of the memory cells is of great significance to improving the storage capacity, energy efficiency and working performance of the memory. Summary of the invention
[0005] In view of the defects of the prior art, the purpose of the present application is to provide a 2T0C-DRAM storage unit, a preparation method and a storage array, aiming to solve the problems of limited storage density and low array operation accuracy of the existing 2T0C-DRAM storage unit.
[0006] To achieve the above objectives, in a first aspect, the present application provides a 2T0C-DRAM storage unit that is easy to integrate, including: a read transistor and a write transistor stacked on the read transistor;
[0007] The first gate of the read transistor and the second drain of the write transistor share the same structure;
[0008] The surrounding channel region of the read transistor surrounds and wraps around the side and bottom surfaces of the first gate / second drain;
[0009] The surrounding channel region of the write transistor completely wraps around the upper, left, lower and right four surfaces of the second gate of the write transistor.
[0010] Preferably, the same structure is a T-shaped structure with a rectangular parallelepiped at the upper end and a cylindrical body at the lower end; the surrounding channel region of the read transistor surrounds the bottom surface of the rectangular parallelepiped and the side and bottom surfaces of the cylinder.
[0011] Preferably, the write transistor comprises: a second source electrode, a second gate electrode, a second drain electrode, a second semiconductor thin film layer and a second gate dielectric layer;
[0012] The second gate is a rectangular parallelepiped structure;
[0013] The second semiconductor thin film layer and the second gate dielectric layer are nested in sequence from outside to inside to form a hollow rectangular parallelepiped structure, contacting and wrapping the upper, left, lower and right four surfaces of the second gate;
[0014] The surrounding channel region includes a second semiconductor thin film layer and a second gate dielectric layer.
[0015] Preferably, the second source electrode is arranged on the upper surface of the second semiconductor thin film layer, and penetrates in the left-right direction to serve as a write bit line; the second gate electrode penetrates in a direction perpendicular to the cross section to serve as a write word line.
[0016] Preferably, the read transistor comprises: a first gate, a first gate dielectric layer, a first semiconductor film layer, a first drain and a first source;
[0017] The cross section of the first gate is T-shaped, and the surface of the top end is in contact with the second semiconductor film layer of the write transistor;
[0018] The first semiconductor thin film layer and the first gate dielectric layer are nested in sequence from outside to inside to form a cross section of A cylindrical structure of the type surrounding the side and bottom surfaces of the first gate;
[0019] The surrounding channel region includes a first gate dielectric layer and a first semiconductor thin film layer.
[0020] Preferably, the read transistor further comprises: a third gate dielectric layer and a third gate;
[0021] The surrounding channel region further includes a third gate dielectric layer;
[0022] The third gate electrode and the third gate dielectric layer are nested in sequence from outside to inside to form a ring structure, and surround part of the side surface of the first semiconductor film layer, and are isolated from the first source electrode and the first drain electrode.
[0023] Preferably, the first source electrode is arranged on the lower surface of the first semiconductor thin film layer and penetrates in the left-right direction to serve as a read bit line; the first drain electrode contacts the step structure of the first semiconductor thin film layer and penetrates in the entire horizontal plane to serve as a ground line; the third gate electrode penetrates in a direction perpendicular to the cross section to serve as a read word line.
[0024] To achieve the above-mentioned object, in a second aspect, the present application provides a method for preparing a 2T0C-DRAM memory cell as described in the first aspect, comprising:
[0025] Forming the various layers of the read transistor on the surface of the semiconductor substrate substantially in a sequence from bottom to top and from outside to inside, until the first gate electrode / second drain electrode is formed;
[0026] forming an insulating layer above the first gate electrode / the second drain electrode and penetrating the insulating layer to form an opening;
[0027] filling the opening with a sacrificial layer sufficiently;
[0028] forming a second source electrode on the upper surface of the structure;
[0029] The sacrificial layer is removed to expose the opening to form a cavity;
[0030] Sequentially forming a second semiconductor thin film layer and a second gate dielectric layer on all surfaces of the cavity, and removing a portion of the second semiconductor thin film layer and the second gate dielectric layer;
[0031] forming a second gate by substantially filling the remaining portion of the cavity;
[0032] An insulating layer is formed on the upper surface of the above structure.
[0033] To achieve the above-mentioned purpose, in a third aspect, the present application provides a 2T0C-DRAM storage array, comprising: a plurality of 2T0C-DRAM storage strings stacked in a horizontal direction; the 2T0C-DRAM storage strings comprise a plurality of 2T0C-DRAM storage units as described in the first aspect arranged in parallel in a horizontal direction.
[0034] Preferably, the memory array further comprises: a plurality of read word lines, read bit lines, write word lines, write bit lines and ground lines;
[0035] Each read word line is formed by connecting the third gates of all 2T0C-DRAM memory cells in the same memory string;
[0036] Each read bit line is formed by connecting the first sources of all 2T0C-DRAM memory cells in the same memory string;
[0037] Each write word line is formed by connecting the second gates of all 2T0C-DRAM memory cells in the same memory string;
[0038] Each write bit line is formed by connecting the second sources of all 2T0C-DRAM memory cells in the same memory string;
[0039] Each ground line is formed by connecting the first drain electrodes of all 2T0C-DRAM memory cells in the same memory string.
[0040] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:
[0041] (1) The present application provides a 2T0C-DRAM storage unit, including a write transistor and a dual-gate read transistor stacked up and down; wherein the channel layer of the write transistor is annular, surrounding the four sides of the gate of the write transistor; and the channel layer of the dual-gate read transistor is cylindrical, surrounding the side and bottom surfaces of the first gate of the dual-gate read transistor; such a design greatly increases the space utilization in the vertical direction, so that the channel length per unit area of the transistor is higher, thereby increasing the density of the transistor, thereby increasing the storage density. The shape design of the channel layer of the write transistor and the dual-gate read transistor greatly increases the contact surface ratio between the gate and the insulating layer, which can reduce the influence of the electrical signal on the channel layer of the dual-gate read transistor during the read operation, that is, reduces the risk of abnormal working state of the storage unit due to size scaling. The third gate of the dual-gate read transistor replaces the role of the drain of the read transistor in the original 2T0C-DRAM unit, and plays a role in accurately regulating the channel state of the transistor, and the read word line no longer bears the task of data output, but is only responsible for the transistor shutdown work, thereby reducing the new channel path and potential current influence caused by the change of the transistor structure in the storage unit, and avoiding the problem of IR (current × resistance) reduction in the storage array. The memory cell arranges the structure and position of the gate, source and drain of the write transistor and the dual-gate read transistor so that the write word line, write bit line, read word line, read bit line and ground line of the memory array are staggered and spaced a sufficient distance apart, thereby reducing the coupling effect caused by signal changes in the memory array, alleviating the load of the dual-gate read transistor, increasing the read operation speed, increasing the charge retention rate of the storage node, and improving the working efficiency and anti-interference ability of the memory cell.
[0042] (2) The present application provides a method for preparing a 2T0C-DRAM memory cell, wherein the source, second gate and drain of a dual-gate read transistor are manufactured in sequence, and after the completion of this part of the manufacturing, the channel layer and the first gate are manufactured, which helps to ensure the shape accuracy of the channel layer and the stable contact between the channel layer and the source and the second source. The gate and channel layer of the write transistor are manufactured through the hole formed by the sacrificial layer, which can reduce the complexity and defects of the process, ensure the integrity of the channel layer and the stable contact with the source and the gate, and ensure the insulation stability between different structures of the transistor and between transistors. Due to the particularity of the memory cell structure design, the specific dimensions of some structures can be set to a certain extent according to the specific materials, equipment, and product tendencies during the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] Figure 1 This is a schematic diagram of the structure of a 2T0C-DRAM storage unit that is easy to integrate provided by the present application.
[0044] Figure 2 It is a structural diagram of the first part provided by this application.
[0045] Figure 3 It is a structural diagram of the second part provided by this application.
[0046] Figure 4-1 It is a schematic diagram of the structure formed by the preparation step S2 provided in this application.
[0047] Figure 4-2 It is a schematic top view of the structure formed in the preparation step S2 provided in the present application.
[0048] Figure 5-1 It is a schematic diagram of the structure formed by the preparation steps S3-S4 provided in this application.
[0049] Figure 5-2 It is a schematic top view of the structure formed by the preparation steps S3-S4 provided in this application.
[0050] Figure 6-1 It is a schematic diagram of the structure formed by the preparation step S5 provided in this application.
[0051] Figure 6-2 It is a schematic top view of the structure formed in the preparation step S5 provided in this application.
[0052] Figure 7-1 It is a schematic diagram of the structure formed by the preparation steps S6-S7 provided in this application.
[0053] Figure 7-2 It is a schematic top view of the structure formed by the preparation steps S6-S7 provided in this application.
[0054] Figure 8-1It is a schematic diagram of the structure formed by the preparation steps S8-S10 provided in this application.
[0055] Figure 8-2 It is a schematic top view of the structure formed by the preparation steps S8-S10 provided in this application.
[0056] Figure 9-1 It is a schematic diagram of the structure formed by the preparation steps S11-S12 provided in this application.
[0057] Figure 9-2 It is a schematic top view of the structure formed by the preparation steps S11-S12 provided in this application.
[0058] Figure 10-1 It is a schematic diagram of the structure formed by the preparation steps S13-S14 provided in this application.
[0059] Figure 10-2 It is a schematic top view of the structure formed by the preparation steps S13-S14 provided in this application.
[0060] Figure 11-1 It is a schematic diagram of the structure formed by the preparation step S15 provided in this application.
[0061] Figure 11-2 It is a schematic top view of the structure formed in the preparation step S15 provided in the present application.
[0062] Figure 12-1 It is a schematic diagram of the structure formed by the preparation steps S16-S17 provided in this application.
[0063] Figure 12-2 It is a schematic top view of the structure formed by the preparation steps S16-S17 provided in this application.
[0064] Figure 13-1 It is a schematic diagram of the structure formed by the preparation steps S18-S19 provided in this application.
[0065] Figure 13-2 It is a schematic top view of the structure formed by the preparation steps S18-S19 provided in this application.
[0066] Figure 14-1 It is a schematic diagram of the structure formed by the preparation steps S20-S21 provided in this application.
[0067] Figure 14-2 It is a schematic top view of the structure formed by the preparation steps S20-S21 provided in this application.
[0068] Throughout the drawings, the same reference numerals are used to denote the same elements or structures, wherein:
[0069] 11-write transistor, 111-second gate, 112-second gate dielectric layer, 113-second semiconductor film layer, 114-second source; 12-read transistor, 121-second drain / first gate, 122-first gate dielectric layer, 123-first semiconductor film layer, 124-first drain, 125-third gate dielectric layer, 126-third gate, 127-first source; 13-insulating layer, 131-first insulating layer, 132-second insulating layer. DETAILED DESCRIPTION
[0070] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.
[0071] like Figure 1 As shown, the present application provides a 2T0C-DRAM memory cell that is easy to integrate, including a first part and a second part stacked in sequence.
[0072] like Figure 2 As shown, the first part includes: a second insulating layer 132 and a write transistor 11. The write transistor 11 includes: a second gate 111, a second gate dielectric layer 112, a second semiconductor film layer 113, a second source 114 and a second drain 121. Among them, the second source 114 is away from the second part, located above the second semiconductor film layer 113 and in contact with the second semiconductor film layer 113; the central axis of the second source 114 extends in the left and right directions of the cross section; the central axis of the second gate 111 extends in a direction perpendicular to the cross section and intersects vertically with the central axis of the second source 114; the second drain 121 is located below the second semiconductor film layer 113 and in contact with the second semiconductor film layer 113, and the position of the second semiconductor film layer 113 in the left and right directions is adjustable to ensure that the contact area between the two is equal to the lower surface area of the second semiconductor film layer 113; the second drain 121 shares the same structure with the first gate of the read transistor. The second gate 111 is a write word line WWL, and the second source 114 is a write bit line WBL. The second insulating layer 132 occupies the space from the top of the first drain electrode 124 to the top of the second source electrode 114 and fills the gap in this part of the structure.
[0073] like Figure 3As shown, the second part includes: a first insulating layer 131 and a dual-gate read transistor 12. The dual-gate read transistor 12 includes: a first gate 121, a first gate dielectric layer 122, a first semiconductor film layer 123, a first drain 124, a third gate dielectric layer 125, a third gate 126 and a first source 127. Among them, the first gate 121 shares the same structure with the second drain of the write transistor; the central axis of the first gate 121 extends in the vertical direction of the cross section and intersects perpendicularly with the central axis of the second gate 111; the first drain 124 is close to the first part and contacts the first semiconductor thin film layer 123, and the central axis of the first drain 124 coincides with the central axis of the second source 114 in the plane direction; the central axis of the first gate 121 extends in the vertical direction of the cross section and intersects perpendicularly with the central axis of the first drain 124; the third gate dielectric layer 125 and the third gate 126 are located near the middle of the first part and contact the first semiconductor thin film layer 123 in turn, the central axis of the third gate 126 extends in a direction perpendicular to the cross section and intersects perpendicularly with the central axis of the first gate 121; the first source 127 is away from the first part, located below the first semiconductor thin film layer 123 and contacts the first semiconductor thin film layer 123, and the central axis of the first source 127 coincides with the central axis of the first drain 124. The first drain 124 is the ground line GND, the third gate 126 is the read word line RWL, and the first gate 127 is the read bit line RBL. The first insulating layer 131 occupies the space from the bottom of the first source 127 to the top of the first drain 124 and fills the gap in this part of the structure.
[0074] WWL and RWL extend in a direction perpendicular to the cross section; WBL, RBL and GND extend in a left-right direction of the cross section.
[0075] Preferably, the portion of the second gate dielectric layer 112 and the second semiconductor thin film layer 113 that overlaps with the planar direction of the second source electrode 114 sequentially wraps the upper, lower, left and right surfaces of the second gate dielectric layer 112 and the second semiconductor thin film layer 113, and the left, right and lower surfaces of the second gate dielectric layer 112 and the second semiconductor thin film layer 113 extend a certain distance forward and backward.
[0076] It should be noted that the present application prefers the above-mentioned structural design, the main purpose of which is to construct a transistor channel layer surrounding the second gate 111 of the write transistor 11, so as to significantly reduce the horizontal and vertical areas occupied by the write transistor 11, thereby improving the integration of the memory cell, and optimizing the arrangement of WWL and WBL, thereby reducing the problems caused by the sneak current in the memory array; in addition, the extended second gate dielectric layer 112 and the second semiconductor thin film layer separate the WWL and the WBL to avoid causing cross-circuit problems and affecting the normal operation of the memory cell.
[0077] Preferably, the first gate dielectric layer 122 and the first semiconductor thin film layer 123 sequentially wrap the side surface and the bottom surface of the first gate electrode 121, and extend a distance around the top of the first gate electrode 121 (which is also the bottom of the second drain electrode 121), and the boundary of the first gate dielectric layer 122, the first semiconductor thin film layer 123 and the upper surface portion of the second drain electrode 121 is a square that overlaps in the horizontal direction, and the side length is at least 40nm larger than the diameter of the cylindrical portion of the first semiconductor thin film layer 123.
[0078] It should be noted that the present application prefers the above-mentioned structure and size design, the main purpose of which is to significantly reduce the planar area occupied by the dual-gate read transistor 12, thereby improving the integration of the storage unit; the nested design of the first gate 121, the first gate dielectric layer 122, and the first semiconductor film layer 123 is mainly to ensure the uniformity of the first gate dielectric layer 122 and the first semiconductor film layer 123; in addition, the extended first gate dielectric layer 122, the first semiconductor film layer 123 and the second drain 121 effectively separate the lines of the write transistor 11 and the dual-gate read transistor 12 to avoid cross-circuit problems, and increase the contact area between the second drain 121 and the second semiconductor film layer 113, thereby ensuring the normal operation of the write transistor 11 and the stable connection with the dual-gate read transistor 12.
[0079] Preferably, the central axes of the second source 114, the first drain 124 and the first source 127 coincide in the horizontal direction and extend in the left-right direction, while the central axes of the second gate 111 and the third gate 126 coincide in the horizontal direction and extend in the direction perpendicular to the cross section; the first drain 124, the third gate 126 and the first source 127 are arranged in sequence from top to bottom, and the distance between the first drain 124 and the third gate 126, and the distance between the third gate 126 and the first source 127 are not less than 100 nm.
[0080] It should be noted that the present application prefers the above-mentioned structure and size design, the main purpose of which is to arrange WWL, RWL, WBL, RBL and GND in a staggered and cross-arranged manner, thereby optimizing the array wiring and reducing the coupling effect caused by the change of electrical signals during the operation of the storage array, thereby accelerating the reading operation; in addition, reducing the influence of the sneak current between WWL, RWL, WBL, RBL and GND, thereby improving the charge retention rate of the storage unit, and then improving the working stability of the unit.
[0081] Preferably, all gate dielectric layers have the same thickness, ranging from 5 to 10 nm. All semiconductor thin film layers have the same thickness, ranging from 10 to 20 nm.
[0082] Preferably, the width of the second gate 111 is not less than 40 nm, and the height thereof is in the range of 100-300 nm.
[0083] It should be noted that the present application prefers the above-mentioned size design, the main purpose of which is to make the second gate 111 fully contact with the second gate dielectric layer 112 and normally bear the electrical signal input capability of WWL, thereby ensuring the normal operation of the write transistor 11; in addition, the size design also makes the width-to-length ratio of the write transistor 11 greater than that of the dual-gate read transistor 12, and thus the saturation current of the write transistor 11 is higher than that of the read transistor, which can better control the read operation of the storage unit.
[0084] Preferably, the thickness of the first drain electrode 124 is not less than 50 nm.
[0085] Preferably, the thickness of the third gate 126 and the height of the third gate dielectric layer 125 are in the range of 50-100 nm.
[0086] It should be noted that the present application prefers the above-mentioned size design, the main purpose of which is to make the first drain 124 and the third gate dielectric layer 125 fully contact with the first semiconductor film layer 123, normally assume the current grounding function of GND and the electrical signal input capability of RWL, thereby ensuring the normal operation of the dual-gate read transistor 12.
[0087] Preferably, the thickness of the second source electrode 114 and the first source electrode 127 is in the range of 10-50 nm.
[0088] The insulating layer 13 is the first structure filled when manufacturing each layer of the storage unit, and plays the role of supporting the subsequent process and electrically insulating the various structures of the finished unit and between the units. Preferably, the first insulating layer 131 and the second insulating layer 132 can each independently use one of ethyl silicate, phosphate glass, doped silicon glass, borophosphosilicate glass, silazane polymer ceramics, and silicon nitride as a material.
[0089] The gate dielectric layer is used to prevent leakage current between the gate and the semiconductor film layer due to the semiconductor film layer being too thin. Preferably, the first gate dielectric layer 122, the second gate dielectric layer 112 and the third gate dielectric layer 125 can each independently use one of aluminum oxide, silicon oxide and hafnium oxide as a material.
[0090] The semiconductor film layer is a key material for the normal operation of the transistor and the storage unit to maintain the electrical signal data. Preferably, the first semiconductor film layer 123 is made of indium tin oxide (ITO) and the second semiconductor film layer 113 is made of ITO or indium gallium zinc oxide (IGZO).
[0091] The sacrificial layer is a special material layer, which is used to provide a temporary substrate for the second gate 111 in the manufacturing process of the 2TOC-DRAM memory cell, reduce the complexity of the process, and is removed in subsequent steps to help complete the manufacturing of the annular second semiconductor film layer 113 and the second gate dielectric layer 112. Preferably, the sacrificial layer is made of one of polyimide (PI) and polymethyl methacrylate (PMMA).
[0092] The second drain of the write transistor is integrated with the first gate of the dual-gate read transistor and serves as the storage node of the data in the storage unit; by applying an electrical signal to the gate and source of the write transistor, the charge in the gate capacitance of the dual-gate read transistor is changed, thereby affecting the resistance state between the source and drain of the dual-gate read transistor, thereby realizing the distinction between data "0" and "1". The specific principle is as follows:
[0093] In the process of writing "1", a positive bias turn-on voltage (which is greater than the threshold voltage V of the write transistor) is applied to the second gate 111 (write word line WWL). TH ) turns on the write transistor, applies a positive bias write voltage to the second source 114 (write bit line WBL), injects charges to the second drain / first gate 121, removes the voltage applied to the second gate 111 and the second source 114 after the charge injection, and at this time, part of the charge in the second drain / first gate 121 is separated from other structures by the first semiconductor film layer 123 and the second semiconductor film layer 113, and serves as a storage node to save the "1" state; this part of the charge will slowly lose over time, and when the charge amount is reduced to a certain level, the storage node will lose the saved "1" state, and at this time, the charge refresh of the storage array is required to restore the charge storage state of the storage node. Compared with general DRAM storage cells, this cycle is significantly longer, so the data retention capability and data refresh load are significantly better than those of general DRAM storage cells;
[0094] In the process of reading "1", a higher positive bias read voltage is applied to the third gate 126 (read word line RWL) so that the gate has a higher threshold voltage V TH The dual-gate read transistor is turned on. Since a certain charge is stored in the second drain / first gate 121 and the dual-gate read transistor structure is in a relatively low resistance state, a read current is obtained at the first source 127 (read bit line RBL). This current can be amplified and identified by the peripheral circuit to complete the process of reading "1";
[0095] In the process of writing "0", a positive bias turn-on voltage (greater than the threshold voltage V TH) turns on the write transistor, applies a negative bias write voltage to the second source (write bit line WBL), extracts charges from the second drain / first gate 121, and after the charges in the second drain / first gate 121 are completely released, the voltages applied to the second gate and the second source can be removed, and the second drain / first gate 121 serves as a storage node to store the "0" state;
[0096] In the process of reading "0", a lower positive bias read voltage is applied to the third gate (read word line RWL) to make the gate have a lower threshold voltage V TH The dual-gate read transistor is turned on. Since no charge is stored in the second drain / first gate 121 and the dual-gate read transistor structure is in a relatively high resistance state, a very small read current is obtained, which can be recognized by the peripheral circuit to complete the "0" reading process.
[0097] Based on the above storage unit, the present application provides a method for preparing a 2T0C-DRAM storage unit that is easy to integrate, comprising:
[0098] S1. Providing a semiconductor substrate;
[0099] S2. Figure 4-1 and Figure 4-2 As shown, a first source electrode is formed on the surface of a semiconductor substrate (the semiconductor substrate is not shown in the figure);
[0100] S3. Figure 5-1 and Figure 5-2 As shown, a portion of a first insulating layer is formed above the semiconductor substrate and the first source electrode, and the first insulating layer contacts and completely covers the upper surface and all side surfaces of the first source electrode;
[0101] S4. Figure 5-1 and Figure 5-2 As shown, a first opening is formed on a portion of the surface of the first insulating layer, the horizontal position of the first opening is located on the central axis of the first source electrode, and is separated from the first source electrode by a certain distance through the first insulating layer;
[0102] S5. Figure 6-1 and Figure 6-2 As shown, a third gate is formed in the first opening, and the third gate completely fills the first opening;
[0103] S6. Figure 7-1 and Figure 7-2 As shown, a second opening is formed on the surface of the third grid; the second opening is located in the middle of the third grid and passes through the third grid from top to bottom;
[0104] S7. Figure 7-1 and Figure 7-2As shown, a third gate dielectric layer is formed on the side of the second opening, the third gate dielectric layer completely covers the side of the second opening, and the top of the third gate dielectric layer is at the same height as the upper surface of the third gate;
[0105] S8. Figure 8-1 and Figure 8-2 As shown, a portion of a first insulating layer is formed above the structure, and the first insulating layer contacts and completely covers the upper exposed surface of the structure;
[0106] S9. Figure 8-1 and Figure 8-2 As shown, a first drain electrode is formed above the first insulating layer, and the first drain electrode contacts and completely covers the upper surface of the first insulating layer;
[0107] S10. Figure 8-1 and Figure 8-2 As shown, a third opening is formed on the surface of the first drain electrode, the horizontal position and size of the third opening are the same as those of the second opening, and the third opening passes through the first drain electrode and the first insulating layer, and the bottom is in contact with the upper surface of the first source electrode;
[0108] S11. Figure 9-1 and Figure 9-2 As shown, a first semiconductor film layer and a first gate dielectric layer are sequentially formed on the bottom surface and side surfaces of the third opening, and on the upper surface of a portion of the first drain electrode close to the third opening, the first semiconductor film layer and the first gate dielectric layer contact and completely cover the bottom surface and side surfaces of the third opening, and the first semiconductor film layer and the first gate dielectric layer are at the same horizontal position of the boundary covering the upper surface portion of the first drain electrode;
[0109] S12. Figure 9-1 and Figure 9-2 As shown, a first gate electrode and a second drain electrode are formed in the remaining space of the third opening and on the upper surface of the first gate dielectric layer, the first gate electrode and the second drain electrode are in full contact with each other, completely fill the remaining portion of the third opening, and the boundary covering the upper surface portion of the first gate dielectric layer is at the same horizontal position as the first gate dielectric layer;
[0110] S13. Figure 10-1 and Figure 10-2 As shown, a partial second insulating layer is formed above the structure, and the second insulating layer contacts and completely fills the upper exposed surface of the structure;
[0111] S14. Figure 10-1 and Figure 10-2 As shown, a fourth opening is formed on the upper surface of the second insulating layer, the central axis of the fourth opening coincides with the central axis of the third gate, and passes through the second insulating layer, and the plane where the bottom is located coincides with the upper surface of the second drain;
[0112] S15. Figure 11-1 and Figure 11-2As shown, a sacrificial layer is formed in the fourth opening, and the sacrificial layer completely fills the fourth opening;
[0113] S16. Figure 12-1 and Figure 12-2 As shown, a second source electrode is formed on the upper surface of the above structure, and the central axis of the second source electrode coincides with the central axis of the first source electrode;
[0114] S17. Figure 12-1 and Figure 12-2 As shown, the sacrificial layer is removed to expose the fourth opening to form a cavity;
[0115] S18. Figure 13-1 and Figure 13-2 As shown, a second semiconductor film layer and a second gate dielectric layer are sequentially formed on all surfaces of the cavity, and the second semiconductor film layer and the second gate dielectric layer contact and completely cover the bottom surface, left and right sides of the cavity, and the lower surface of the second source electrode in contact with the cavity;
[0116] S19. Figure 13-1 and Figure 13-2 As shown, a portion of the second semiconductor film layer and the second gate dielectric layer is etched away, and the remaining second semiconductor film layer and the second gate dielectric layer cover the bottom surface and the side boundary of the cavity at the same position on the horizontal plane;
[0117] S20. Figure 14-1 and Figure 14-2 As shown, a second gate is formed in the remaining space of the cavity, the second gate completely fills the cavity, is fully in contact with the upper, lower, left and right surfaces of the second gate dielectric layer, and the exposed upper surface is located on the same horizontal plane as the upper surface of the second insulating layer;
[0118] S21. Figure 14-1 and Figure 14-2 As shown, a portion of the second insulating layer is formed on the upper surface of the above structure, and the second insulating layer contacts and at least fully covers the portion of the second insulating layer and the second gate formed above.
[0119] It should be noted that, among Figures 4 to 14, all Figure 2 shows a top view of the integrated 2T0C-DRAM memory cell preparation method, and all Figure 1 shows a cross-sectional view of the integrated 2T0C-DRAM memory cell preparation method along the dotted line AA' in Figure 2.
[0120] The present application also provides an integrated 2T0C-DRAM storage array, comprising: a plurality of 2T0C-DRAM storage strings stacked in a horizontal direction; the 2T0C-DRAM storage strings comprise a plurality of the above-mentioned integrated 2T0C-DRAM storage units arranged in parallel in a horizontal direction.
[0121] Preferably, the memory array further comprises: a plurality of read word lines, read bit lines, write word lines, write bit lines and ground lines; each read word line is formed by connecting the third gates (located at the double-gate read transistor) of all 2T0C-DRAM memory cells located in the same memory string; each read bit line is formed by connecting the first sources (located at the double-gate read transistor) of all 2T0C-DRAM memory cells located in the same memory string; each write word line is formed by connecting the second gates (located at the write transistor) of all 2T0C-DRAM memory cells located in the same memory string; each write bit line is formed by connecting the second sources (located at the write transistor) of all 2T0C-DRAM memory cells located in the same memory string; and each ground line is formed by connecting the first drains (located at the double-gate read transistor) of all 2T0C-DRAM memory cells located in the same memory string.
[0122] Preferably, the storage cells in the bottom 2T0C-DRAM storage string are provided with a substrate, and adjacent storage cells are basically electrically isolated by shallow trenches on the substrate, and storage cells in other 2T0C-DRAM storage layers may not be provided with a substrate.
[0123] It should be understood that expressions such as "including" and "may include" that may be used in the present application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In the present application, terms such as "including" and / or "having" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.
[0124] In addition, in the present application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.
[0125] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. Among them, "fixed connection" means that the relative position relationship after connection remains unchanged. "Rotational connection" means that the two are connected to each other and can rotate relative to each other after connection. "Sliding connection" means that the two are connected to each other and can slide relative to each other after connection. The directional terms mentioned in the embodiments of the present application, such as "top", "bottom", "inside", "outside", "left", "right", etc., are only reference directions of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.
[0126] In addition, in the embodiments of the present application, the mathematical concepts mentioned are symmetry, equality, parallelism, verticality, etc. These limitations are all for the current state of the art, rather than being absolutely strict definitions in a mathematical sense, and allow a small amount of deviation, approximation to symmetry, approximation to equality, approximation to parallelism, approximation to verticality, etc. are all possible. For example, A and B are parallel, which means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. A and B are perpendicular, which means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.
[0127] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A 2T0C-DRAM storage unit that is easy to integrate, characterized in that: include: a read transistor and a write transistor stacked on the read transistor; The first gate of the read transistor and the second drain of the write transistor share the same structure; The surrounding channel region of the read transistor surrounds and wraps around the side and bottom surfaces of the first gate / second drain; The surrounding channel region of the write transistor completely wraps around the upper, left, lower and right four surfaces of the second gate of the write transistor.
2. The 2T0C-DRAM memory cell according to claim 1, wherein: The same structure is a T-shaped structure with a rectangular parallelepiped at the upper end and a cylindrical body at the lower end; the surrounding channel region of the read transistor surrounds the bottom surface of the rectangular parallelepiped and the side and bottom surfaces of the cylinder.
3. The 2T0C-DRAM memory cell according to claim 1, wherein: The write transistor comprises: a second source electrode, a second gate electrode, a second drain electrode, a second semiconductor thin film layer and a second gate dielectric layer; The second gate is a rectangular parallelepiped structure; The second semiconductor thin film layer and the second gate dielectric layer are nested in sequence from outside to inside to form a hollow rectangular parallelepiped structure, contacting and wrapping the upper, left, lower and right four surfaces of the second gate; The surrounding channel region includes a second semiconductor thin film layer and a second gate dielectric layer.
4. The 2T0C-DRAM memory cell according to claim 3, wherein: The second source electrode is arranged on the upper surface of the second semiconductor thin film layer, and penetrates in the left-right direction to serve as a write bit line; the second gate electrode penetrates in a direction perpendicular to the cross section to serve as a write word line.
5. The 2T0C-DRAM memory cell according to claim 1, wherein: The read transistor comprises: a first gate, a first gate dielectric layer, a first semiconductor film layer, a first drain and a first source; The cross section of the first gate is T-shaped, and the surface of the top end is in contact with the second semiconductor film layer of the write transistor; The first semiconductor thin film layer and the first gate dielectric layer are nested in sequence from outside to inside to form a cross section of A cylindrical structure of the type surrounding the side and bottom surfaces of the first gate; The surrounding channel region includes a first gate dielectric layer and a first semiconductor thin film layer.
6. The 2T0C-DRAM memory cell according to claim 5, wherein: The read transistor further includes: a third gate dielectric layer and a third gate; The surrounding channel region further includes a third gate dielectric layer; The third gate electrode and the third gate dielectric layer are nested in sequence from outside to inside to form a ring structure, and surround part of the side surface of the first semiconductor film layer, and are isolated from the first source electrode and the first drain electrode.
7. The 2T0C-DRAM memory cell according to claim 6, wherein: The first source electrode is arranged on the lower surface of the first semiconductor thin film layer and penetrates in the left-right direction to serve as a read bit line; the first drain electrode contacts the step structure of the first semiconductor thin film layer and penetrates on the entire horizontal plane to serve as a ground line; the third gate electrode penetrates in a direction perpendicular to the cross section to serve as a read word line.
8. A method for preparing a 2TOC-DRAM memory cell according to any one of claims 1 to 7, characterized in that: include: Forming the various layers of the read transistor on the surface of the semiconductor substrate substantially in a sequence from bottom to top and from outside to inside, until the first gate electrode / second drain electrode is formed; forming an insulating layer above the first gate electrode / the second drain electrode and penetrating the insulating layer to form an opening; filling the opening with a sacrificial layer sufficiently; forming a second source electrode on the upper surface of the structure; The sacrificial layer is removed to expose the opening to form a cavity; Sequentially forming a second semiconductor thin film layer and a second gate dielectric layer on all surfaces of the cavity, and removing a portion of the second semiconductor thin film layer and the second gate dielectric layer; forming a second gate by substantially filling the remaining portion of the cavity; An insulating layer is formed on the upper surface of the above structure.
9. A 2T0C-DRAM storage array, characterized in that: include: A plurality of 2T0C-DRAM memory strings stacked in a horizontal direction; The 2T0C-DRAM memory string includes a plurality of 2T0C-DRAM memory cells according to any one of claims 1 to 7 arranged in parallel along a horizontal direction.
10. The 2TOC-DRAM memory array according to claim 9, wherein: The storage array further includes: a plurality of read word lines, read bit lines, write word lines, write bit lines and ground lines; Each read word line is formed by connecting the third gates of all 2T0C-DRAM memory cells in the same memory string; Each read bit line is formed by connecting the first sources of all 2T0C-DRAM memory cells in the same memory string; Each write word line is formed by connecting the second gates of all 2T0C-DRAM memory cells in the same memory string; Each write bit line is formed by connecting the second sources of all 2T0C-DRAM memory cells in the same memory string; Each ground line is formed by connecting the first drain electrodes of all 2T0C-DRAM memory cells in the same memory string.