Manufacturing method of SONOS flash memory device selection tube

Abstract

The present application relates to the field of semiconductor integrated circuit manufacturing technology, and specifically to a method for manufacturing a SONOS flash memory device selector of a SONOS device. The method comprises providing a semiconductor substrate with a control gate structure, wherein each control gate structure comprises a control gate polysilicon layer, an ONO layer formed between the control gate polysilicon layer and the semiconductor substrate, and a silicon oxide hard mask layer and a silicon nitride hard mask layer formed on the control gate polysilicon layer; forming silicon nitride isolation layers on the left and right sides of the control gate structure; depositing polysilicon, the polysilicon covering the surface of the control gate structure with the silicon nitride isolation layer, filling the gaps between adjacent control gate structures, and covering the semiconductor substrate; depositing a polysilicon sidewall hard mask layer, the polysilicon sidewall hard mask layer covering the upper surface of the polysilicon based on the surface morphology of the polysilicon; etching the polysilicon sidewall hard mask layer and the polysilicon as a whole, retaining the polysilicon covering the vertical region on the side of the control gate structure; and removing the remaining polysilicon sidewall hard mask layer.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a SONOS flash memory device selection tube of a SONOS device. Background Art

[0002] SONOS, an acronym for Silicon-Oxide-Nitride-Oxide-Silicon, is a non-volatile memory closely associated with flash memory. It differs from mainstream flash memory in that it uses silicon nitride as the storage material instead of polysilicon. One of its offshoots is SHINOS (Silicon-High Dielectric-Nitride-Oxide-Silicon). SONOS allows for lower programming voltages and higher program-erase cycles than polysilicon flash memory, making it an active research and development hotspot.

[0003] Figure 1 A schematic cross-sectional view of a SONOS flash memory device selection tube provided by a related art is shown. Figure 1 As can be seen from the figure, the SONOS flash memory device selection transistor includes a control gate structure 10 located in the middle and selection gate structures 20 located on both sides of the control gate structure. Figure 1 The surface morphology of the select gate structure 20 shown is a sidewall morphology.

[0004] As process dimensions gradually shrink, the critical dimensions of select gate structures also continue to decrease. To ensure the connection performance of subsequent contact holes, the select gate structures on both sides of the control gate structure are generally required to have a vertical morphology. However, existing etching processes cannot guarantee the formation of a vertical morphology for small-sized devices, which is not conducive to the reliable connection of subsequent contact holes. Summary of the Invention

[0005] The present application provides a method for manufacturing a selection tube of a SONOS flash memory device, which can solve the problem that the etching process in the prior art is difficult to ensure that a vertical morphology is formed when etching a small-sized device.

[0006] In order to solve the technical problems in the background technology, the present application provides a method for manufacturing a selector tube of a SONOS flash memory device, and the method for manufacturing a selector tube of a SONOS flash memory device comprises the following steps:

[0007] Providing a semiconductor substrate with a control gate structure, wherein two adjacent control gate structures are spaced apart, each control gate structure comprises a control gate polysilicon layer, an ONO layer formed between the control gate polysilicon layer and the semiconductor substrate, and a silicon oxide hard mask layer and a silicon nitride hard mask layer formed on the control gate polysilicon layer, and a gate oxide layer is formed on the exposed semiconductor substrate;

[0008] forming a silicon nitride isolation layer on the left and right sides of the control gate structure;

[0009] Depositing polysilicon, wherein the polysilicon covers the surface of the control gate structure with the silicon nitride isolation layer, fills the space between adjacent control gate structures, and covers the semiconductor substrate;

[0010] Depositing a polysilicon sidewall hard mask layer, wherein the polysilicon sidewall hard mask layer covers the upper surface of the polysilicon based on the surface morphology of the polysilicon;

[0011] Etching the polysilicon sidewall hard mask layer and the polysilicon as a whole, leaving the polysilicon covering the side of the control gate structure in a vertical region;

[0012] The remaining polysilicon sidewall hard mask layer is removed.

[0013] Optionally, the step of forming silicon nitride isolation layers on the left and right sides of the control gate structure includes:

[0014] Depositing a silicon nitride layer on the semiconductor substrate with the control gate structure, so that the silicon nitride layer covers the surface of the control gate structure and the exposed semiconductor substrate;

[0015] The silicon nitride layer is etched to retain the silicon nitride layer located on the side of the control gate structure as silicon nitride isolation layers formed on the left and right sides of the control gate structure.

[0016] Optionally, in the step of depositing a silicon nitride layer on a semiconductor substrate with a control gate structure so that the silicon nitride layer covers the surface of the control gate structure and the exposed semiconductor substrate, the silicon nitride layer covering the surface of the control gate structure covers the upper surface and side surfaces of the control gate structure, and the silicon nitride layer covering the exposed semiconductor substrate covers the gate oxide layer located on the surface of the semiconductor substrate.

[0017] Optionally, in the step of etching the silicon nitride layer and retaining the silicon nitride layer located on the side of the control gate structure as a silicon nitride isolation layer formed on the left and right sides of the control gate structure, the exposed semiconductor substrate located on the upper surface of the control gate structure and the exposed semiconductor substrate are etched away.

[0018] Optionally, the polysilicon surface morphology formed after the steps of depositing polysilicon, covering the surface of the control gate structure with the silicon nitride isolation layer, filling the space between adjacent control gate structures, and covering the semiconductor substrate include:

[0019] It covers the flat area formed on the semiconductor substrate, the vertical area on the side of the control gate structure, the top arc surface area on the control gate structure, and fills the recessed area formed in the space between adjacent control gate structures.

[0020] Optionally, in the step of depositing the polysilicon sidewall hard mask layer, wherein the polysilicon sidewall hard mask layer covers the upper surface of the polysilicon based on the surface morphology of the polysilicon, the polysilicon sidewall hard mask layer covers the polysilicon located in a flat area on the semiconductor substrate, covers the polysilicon located in a vertical area on the side of the control gate structure, covers the polysilicon located in a top arc surface area above the control gate structure, and covers the polysilicon in a recessed area filling the gap between adjacent control gate structures.

[0021] Optionally, the etching selectivity of the polysilicon sidewall hard mask layer in dry etching is greater than the etching selectivity of polysilicon.

[0022] Optionally, the material of the polysilicon sidewall hard mask layer may be any one or more combinations of silicon nitride, titanium nitride and titanium oxide.

[0023] Optionally, the step of integrally etching the polysilicon sidewall hard mask layer and the polysilicon to retain the polysilicon covering the side of the control gate structure in a vertical region includes:

[0024] The polysilicon sidewall hard mask layer and the polysilicon are etched integrally to remove the polysilicon and the polysilicon sidewall hard mask layer located in the flat area and the top arc surface area, and the polysilicon sidewall hard mask layer located in the vertical area is retained as an etching barrier layer to block the integral etching of the side surface of the control gate structure, so as to retain the polysilicon in the vertical area covering the side surface of the control gate structure.

[0025] Optionally, the step of integrally etching the polysilicon sidewall hard mask layer and the polysilicon to retain the polysilicon covering the side of the control gate structure in a vertical region includes:

[0026] By vertically bombarding the polysilicon sidewall hard mask layer and the polysilicon with plasma, the etching rate of the polysilicon sidewall hard mask layer and the polysilicon located on the front is greater than the etching rate of the polysilicon sidewall hard mask layer and the polysilicon located on the side, so as to etch the polysilicon sidewall hard mask layer and the polysilicon as a whole, and retain the polysilicon covering the side of the control gate structure as a vertical area;

[0027] The polysilicon sidewall hard mask layer and polysilicon located on the front include polysilicon and polysilicon sidewall hard mask layer located in the flat area and the top arc surface area, and the polysilicon sidewall hard mask layer and polysilicon located on the side include polysilicon sidewall hard mask layer and polysilicon located in the vertical area.

[0028] The technical solution of the present application includes at least the following advantages: after depositing polysilicon, a polysilicon sidewall hard mask layer is deposited according to the surface morphology of the polysilicon, and then the polysilicon sidewall hard mask layer and the polysilicon are integratedly etched, so that the polysilicon sidewall hard mask layer located on the side of the control gate structure is retained to act as an etching barrier, protecting the side of the control gate structure from being etched to ensure the vertical morphology of the side of the control gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 A schematic cross-sectional view of a selection tube of a SONOS flash memory device provided by a related art is shown;

[0031] Figure 2 A flow chart of a method for manufacturing a selection transistor of a SONOS flash memory device provided in one embodiment of the present application is shown;

[0032] Figure 3 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S1 is completed;

[0033] Figure 4 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S2 is completed;

[0034] Figure 5 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S3 is completed;

[0035] Figure 6 FIG4 shows a schematic diagram of a cross-sectional structure of the device after step S4 is completed;

[0036] Figure 7 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S5 is completed;

[0037] Figure 8 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S6 is completed. DETAILED DESCRIPTION

[0038] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0039] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0040] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0041] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0042] Figure 2 The flowchart of the manufacturing method of the SONOS flash memory device selection tube provided by an embodiment of the present application is shown. Figure 2 As can be seen from the figure, the method for manufacturing the selection tube of the SONOS flash memory device includes the following steps:

[0043] Step S1: Refer to Figure 3 A semiconductor substrate 100 with a control gate structure 200 is provided, wherein two adjacent control gate structures 200 are spaced apart, and each control gate structure 200 includes a control gate polysilicon layer 210, an ONO layer formed between the control gate polysilicon layer 210 and the semiconductor substrate 100, and a silicon oxide hard mask layer and a silicon nitride hard mask layer formed on the control gate polysilicon layer 210, and a gate oxide layer 400 is formed on the exposed semiconductor substrate 100.

[0044] The silicon nitride hard mask layer covers the silicon oxide hard mask layer, and the ONO layer includes a lower oxide layer, a nitride layer and an upper oxide layer stacked in sequence from bottom to top.

[0045] Among them, the semiconductor substrate 100 includes a bulk semiconductor substrate 100 or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer located below a thin semiconductor layer serving as an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0046] Step S2: Refer to Figure 4 , a silicon nitride isolation layer 300 is formed on the left and right sides of the control gate structure 200 .

[0047] For example, the above step S2 can be implemented by following steps S21 to S22 to form silicon nitride isolation layers 300 on the left and right sides of the control gate structure 200:

[0048] Step S21: Depositing a silicon nitride layer on the semiconductor substrate 100 with the control gate structure 200, the silicon nitride layer covering the surface of the control gate structure 200 and the exposed semiconductor substrate 100. The surface of the control gate structure 200 includes the upper surface and side surfaces of the control gate structure 200, the silicon nitride layer located on the exposed semiconductor substrate 100 covers the gate oxide layer 400, the silicon nitride layer located on the upper surface of the control gate structure 200 covers the silicon nitride hard mask layer, and the silicon nitride layer located on the side surfaces of the control gate polysilicon layer 210 covers the side surfaces of the control gate polysilicon layer 210 and extends upward along the side surfaces of the control gate polysilicon layer 210 to cover the side surfaces of the silicon oxide hard mask layer and the side surfaces of the silicon nitride hard mask layer.

[0049] Step S22 : etching the silicon nitride layer, and retaining the silicon nitride layer located on the side of the control gate structure 200 as the silicon nitride isolation layer 300 formed on the left and right sides of the control gate structure 200 .

[0050] The exposed semiconductor substrate 100 located on the upper surface of the control gate structure 200 and the exposed semiconductor substrate 100 are removed by etching.

[0051] Exemplarily, step S22 may be implemented by a plasma dry etching process, that is, by vertically bombarding the silicon nitride layer with plasma so that the etching rate of the silicon nitride layer on the front side is greater than the etching rate of the silicon nitride layer on the side.

[0052] Step S3: Refer to Figure 5 , polysilicon 500 is deposited. The polysilicon 500 covers the surface of the control gate structure 200 with the silicon nitride isolation layer 300 , fills the space between adjacent control gate structures 200 , and covers the semiconductor substrate 100 .

[0053] The surface morphology of the polysilicon 500 formed in step S3 includes a flat area formed on the semiconductor substrate 100, a vertical area covering the side of the control gate structure 200, a top arc surface area covering the control gate structure 200, and a recessed area formed in the space between adjacent control gate structures 200.

[0054] Step S4: Refer to Figure 6 , depositing a polysilicon sidewall hard mask layer 600 , wherein the polysilicon sidewall hard mask layer 600 covers the upper surface of the polysilicon 500 based on the surface morphology of the polysilicon 500 .

[0055] The polysilicon sidewall hard mask layer 600 covers the polysilicon 500 located in a flat area on the semiconductor substrate 100, covers the polysilicon 500 located in a vertical area on the side of the control gate structure 200, covers the polysilicon 500 located in a top arc surface area on the control gate structure 200, and covers the polysilicon 500 in a recessed area filling the gap between adjacent control gate structures 200.

[0056] For example, during dry etching, the etching selectivity of the polysilicon sidewall hard mask layer 600 is greater than the etching selectivity of the polysilicon 500. For example, the material of the polysilicon sidewall hard mask layer 600 can be a combination of any one or more of silicon nitride, titanium nitride, and titanium oxide. The various combinations include the polysilicon sidewall hard mask layer 600 being a stacked structure of silicon nitride and titanium nitride, a stacked structure of silicon nitride and titanium oxide, a stacked structure of titanium nitride and titanium oxide, or a stacked structure of silicon nitride, titanium nitride, and titanium oxide.

[0057] Illustratively, the polysilicon sidewall hard mask layer 600 has a thickness of 100 Å to 150 Å.

[0058] Step S5: Refer to Figure 7 The polysilicon sidewall hard mask layer 600 and the polysilicon 500 are integrally etched, leaving the polysilicon 500 covering the vertical region on the side of the control gate structure 200. By removing the polysilicon 500 and the polysilicon sidewall hard mask layer 600 located in the flat region and the top curved surface region, the polysilicon sidewall hard mask layer 600 located in the vertical region serves as an etch stop layer to block the integral etching of the side of the control gate structure 200, thereby leaving the polysilicon 500 covering the vertical region on the side of the control gate structure 200.

[0059] Exemplarily, step S5 can be implemented by a plasma dry etching process, that is, by vertically bombarding the polysilicon sidewall hard mask layer 600 and the polysilicon 500 with plasma, so that the etching rate of the polysilicon sidewall hard mask layer 600 and the polysilicon 500 located on the front is greater than the etching rate of the polysilicon sidewall hard mask layer 600 and the polysilicon 500 located on the side, so as to etch the polysilicon sidewall hard mask layer 600 and the polysilicon 500 as a whole, retaining the polysilicon 500 covering the side morphology of the control gate structure 200 as a vertical area. The polysilicon sidewall hard mask layer 600 and polysilicon 500 located on the front include the polysilicon 500 and polysilicon sidewall hard mask layer 600 located in the flat area and the top arc surface area, and the polysilicon sidewall hard mask layer 600 and polysilicon 500 located on the side include the polysilicon sidewall hard mask layer 600 and polysilicon 500 located in the vertical area.

[0060] Step S6: removing the remaining polysilicon sidewall hard mask layer 600 .

[0061] Figure 8 The schematic diagram of the cross-sectional structure of the device after step S6 is completed is shown. Figure 8 As can be seen in FIG, the polysilicon sidewall hard mask layer 600 located in the vertical region is removed, so that the side surface of the remaining polysilicon 500 is a vertical surface.

[0062] For example, the remaining polysilicon spacer hard mask layer 600 may be removed by wet etching.

[0063] The present application deposits a polysilicon sidewall hard mask layer according to the surface morphology of the polysilicon after depositing the polysilicon, and then etches the polysilicon sidewall hard mask layer and the polysilicon as a whole, so that the polysilicon sidewall hard mask layer located on the side of the control gate structure is retained to act as an etching barrier, protecting the side of the control gate structure from being etched to ensure the vertical morphology of the side of the control gate structure.

[0064] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for manufacturing a selector tube of a SONOS flash memory device, characterized in that: The manufacturing method of the SONOS flash memory device selection tube comprises the following steps: Providing a semiconductor substrate with a control gate structure, wherein two adjacent control gate structures are spaced apart, each control gate structure comprises a control gate polysilicon layer, an ONO layer formed between the control gate polysilicon layer and the semiconductor substrate, and a silicon oxide hard mask layer and a silicon nitride hard mask layer formed on the control gate polysilicon layer, and a gate oxide layer is formed on the exposed semiconductor substrate; forming a silicon nitride isolation layer on the left and right sides of the control gate structure; Depositing polysilicon, wherein the polysilicon covers the surface of the control gate structure with the silicon nitride isolation layer, fills the space between adjacent control gate structures, and covers the semiconductor substrate; Depositing a polysilicon sidewall hard mask layer, wherein the polysilicon sidewall hard mask layer covers the upper surface of the polysilicon based on the surface morphology of the polysilicon; Etching the polysilicon sidewall hard mask layer and the polysilicon as a whole, leaving the polysilicon covering the side of the control gate structure in a vertical region; The remaining polysilicon sidewall hard mask layer is removed.

2. The method for manufacturing a selection transistor of a SONOS flash memory device according to claim 1, wherein: The step of forming silicon nitride isolation layers on the left and right sides of the control gate structure includes: Depositing a silicon nitride layer on the semiconductor substrate with the control gate structure, so that the silicon nitride layer covers the surface of the control gate structure and the exposed semiconductor substrate; The silicon nitride layer is etched to retain the silicon nitride layer located on the side of the control gate structure as silicon nitride isolation layers formed on the left and right sides of the control gate structure.

3. The method for manufacturing a selection transistor of a SONOS flash memory device according to claim 1, wherein: In the step of depositing a silicon nitride layer on a semiconductor substrate with a control gate structure so that the silicon nitride layer covers the surface of the control gate structure and the exposed semiconductor substrate, the silicon nitride layer covering the surface of the control gate structure covers the upper surface and side surfaces of the control gate structure, and the silicon nitride layer covering the exposed semiconductor substrate covers the gate oxide layer located on the surface of the semiconductor substrate.

4. The method for manufacturing a selection transistor of a SONOS flash memory device according to claim 1, wherein: In the step of etching the silicon nitride layer and retaining the silicon nitride layer located on the side of the control gate structure as the silicon nitride isolation layer formed on the left and right sides of the control gate structure, the exposed semiconductor substrate located on the upper surface of the control gate structure and the exposed semiconductor substrate are etched away.

5. The method for manufacturing a selection transistor of a SONOS flash memory device according to claim 1, wherein: The polysilicon surface morphology formed after the steps of depositing polysilicon, covering the surface of the control gate structure with the silicon nitride isolation layer, filling the space between adjacent control gate structures, and covering the semiconductor substrate are completed includes: It covers the flat area formed on the semiconductor substrate, the vertical area on the side of the control gate structure, the top arc surface area on the control gate structure, and fills the recessed area formed in the space between adjacent control gate structures.

6. The method for manufacturing a selection transistor of a SONOS flash memory device according to claim 5, wherein: In the step of depositing the polysilicon sidewall hard mask layer, wherein the polysilicon sidewall hard mask layer covers the upper surface of the polysilicon based on the surface morphology of the polysilicon, the polysilicon sidewall hard mask layer covers the polysilicon located in a flat area on the semiconductor substrate, covers the polysilicon located in a vertical area on the side of the control gate structure, covers the polysilicon located in a top arc surface area on the control gate structure, and covers the polysilicon in a recessed area filling the gap between adjacent control gate structures.

7. The method for manufacturing a selection transistor of a SONOS flash memory device according to claim 1, wherein: The etching selectivity of the polysilicon sidewall hard mask layer in dry etching is greater than the etching selectivity of polysilicon.

8. The method for manufacturing a selection transistor of a SONOS flash memory device according to claim 1, wherein: The material of the polysilicon sidewall hard mask layer can be any one or more combinations of silicon nitride, titanium nitride and titanium oxide.

9. The method for manufacturing a selection transistor of a SONOS flash memory device according to claim 6, wherein: The step of integrally etching the polysilicon sidewall hard mask layer and the polysilicon to retain the polysilicon covering the side of the control gate structure as a vertical region includes: The polysilicon sidewall hard mask layer and the polysilicon are etched integrally to remove the polysilicon and the polysilicon sidewall hard mask layer located in the flat area and the top arc surface area, and the polysilicon sidewall hard mask layer located in the vertical area is retained as an etching barrier layer to block the integral etching of the side surface of the control gate structure, so as to retain the polysilicon in the vertical area covering the side surface of the control gate structure.

10. The method for manufacturing a selection transistor of a SONOS flash memory device according to claim 1, wherein: The step of integrally etching the polysilicon sidewall hard mask layer and the polysilicon to retain the polysilicon covering the side of the control gate structure as a vertical region includes: By vertically bombarding the polysilicon sidewall hard mask layer and the polysilicon with plasma, the etching rate of the polysilicon sidewall hard mask layer and the polysilicon located on the front is greater than the etching rate of the polysilicon sidewall hard mask layer and the polysilicon located on the side, so as to etch the polysilicon sidewall hard mask layer and the polysilicon as a whole, and retain the polysilicon covering the side of the control gate structure as a vertical area; The polysilicon sidewall hard mask layer and polysilicon located on the front include polysilicon and polysilicon sidewall hard mask layer located in the flat area and the top arc surface area, and the polysilicon sidewall hard mask layer and polysilicon located on the side include polysilicon sidewall hard mask layer and polysilicon located in the vertical area.

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