Semiconductor memory device

Abstract

The embodiment of the invention relates to a semiconductor memory device. The semiconductor memory device includes: a first chip; and a second chip attached to the first direction side with respect to the first chip. The first chip has a plurality of first bonding electrodes provided on a first bonding surface bonded to the second chip. The second chip has a plurality of second bonding electrodes provided on a second bonding surface bonded to the first chip. The plurality of first bonding electrodes and the plurality of second bonding electrodes are bonded to each other to form a plurality of bonding electrodes. The plurality of bonding electrodes includes, as first bonding electrodes, bonding electrodes disposed adjacent to the second insulating layer on one side in the third direction, and includes, as second bonding electrodes, bonding electrodes disposed adjacent to the second insulating layer on the other side in the third direction. The plurality of first bonding electrodes and the plurality of second bonding electrodes are arranged in a staggered shape in the second direction and the third direction.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-119236 (filing date: July 21, 2023). The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Art

[0004] A NAND flash memory in which memory cell transistors are arranged three-dimensionally is known. Summary of the invention

[0005] The semiconductor memory device of the embodiment comprises: a first chip; and a second chip, which is bonded to the first direction side relative to the first chip. The first chip has: a stacked body formed by alternately stacking a plurality of first conductive layers and first insulating layers in the first direction; a storage column, which penetrates the stacked body in the first direction and functions as a memory cell transistor at the intersection with the first conductive layer; and a plurality of first bonding electrodes arranged on the first bonding surface bonded to the second chip. The second chip has a plurality of second bonding electrodes arranged on the second bonding surface bonded to the first chip. The plurality of first bonding electrodes and the plurality of second bonding electrodes are bonded to each other to form a plurality of bonding electrodes. The stacked body has a second insulating layer, which is arranged in a manner extending along a second direction intersecting the first direction, and divides at least a portion of the stacked body in a third direction intersecting both the first direction and the second direction. The plurality of bonding electrodes include a first bonding electrode and a second bonding electrode, the first bonding electrode being adjacently arranged on one side of the third direction relative to the second insulating layer and being arranged at a predetermined interval in the second direction, and the second bonding electrode being adjacently arranged on the other side of the third direction relative to the second insulating layer and being arranged at a predetermined interval in the second direction. The plurality of first bonding electrodes and the plurality of second bonding electrodes are arranged in a staggered pattern in the second direction and the third direction.

[0006] According to the disclosed embodiment, a semiconductor memory device capable of suppressing the generation of voids is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing a schematic configuration of a storage system according to the first embodiment.

[0008] Figure 2 1 is a circuit diagram showing an equivalent circuit of a memory cell array included in the semiconductor memory device according to the first embodiment.

[0009] Figure 3This is a cross-sectional view showing the cross-sectional structure of the semiconductor memory device according to the first embodiment.

[0010] Figure 4 This is an enlarged cross-sectional view showing the cross-sectional structure of the periphery of the memory pillar of the semiconductor memory device according to the first embodiment.

[0011] Figure 5 It is shown Figure 3 A cross-sectional view of the cross-sectional structure along the VV line.

[0012] Figure 6 It is a cross-sectional view showing the cross-sectional structure of the bonding pad and the surrounding areas of the dummy pad according to the first embodiment.

[0013] Figure 7 It is shown Figure 6 A cross-sectional view of the cross-sectional structure along line VII-VII.

[0014] Figure 8 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to a comparative example.

[0015] Fig. 9 It is a cross-sectional view showing the cross-sectional structure of the bonding pad and its surroundings according to the second embodiment.

[0016] Fig.10 This is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to a second embodiment.

[0017] Fig.11 This is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to a first modification of the second embodiment.

[0018] Fig.12 This is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to a second modification of the second embodiment.

[0019] Fig.13 This is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to a third modification of the second embodiment. DETAILED DESCRIPTION

[0020] In order to facilitate understanding of the description, the same components are denoted by the same reference numerals as much as possible in the drawings, and repeated descriptions are omitted.

[0021] 1. First Embodiment

[0022] A semiconductor storage device according to a first embodiment will be described. The semiconductor storage device according to this embodiment is a nonvolatile storage device configured as a NAND flash memory.

[0023] 1.1 Structure of semiconductor memory devices

[0024] Figure 1 1 is a block diagram showing an example of a schematic configuration of a storage system 3 including a semiconductor storage device 1 according to the first embodiment. The semiconductor storage device 1 is controlled by an external memory controller 2. The combination of the semiconductor storage device 1 and the memory controller 2 can constitute the storage system 3. The storage system 3 is, for example, a memory card such as an SDTM card, or an SSD (Solid State Drive).

[0025] The communication between the semiconductor memory device 1 and the memory controller 2 supports, for example, the NAND interface standard. In the communication between the semiconductor memory device 1 and the memory controller 2, for example, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, and an input / output signal I / O are used.

[0026] The input / output signal I / O is, for example, an 8-bit signal, and may include a command CMD, address information ADD, and data DAT. In the following, both write data and read data are labeled with reference symbol DAT for explanation. The semiconductor memory device 1 receives the command CMD, address information ADD, and write data DAT from the memory controller 2 via the input / output signal I / O.

[0027] The command latch enable signal CLE is used to notify the semiconductor memory device 1 of the period during which the command CMD is sent via the signal I / O. The address latch enable signal ALE is used to notify the semiconductor memory device 1 of the period during which the address information ADD is sent via the signal I / O. The write enable signal WEn is used to enable the semiconductor memory device 1 to input the signal I / O. The read enable signal REn is used to enable the semiconductor memory device 1 to output the signal I / O. The ready / busy signal RBn is used to notify the memory controller 2 of whether the semiconductor memory device 1 is in the ready state or the busy state. In the ready state, the semiconductor memory device 1 can accept commands from the memory controller 2. In the busy state, the semiconductor memory device 1 does not accept commands from the memory controller 2 except in exceptional circumstances.

[0028] The semiconductor memory device 1 includes a memory cell array 11 and a peripheral circuit PRC. The peripheral circuit PRC includes a row decoder 12, a sense amplifier 13, and a sequencer 14. The memory cell array 11 includes blocks BLK0 to BLK(n-1) (n is an integer greater than 1). The block BLK includes a plurality of nonvolatile memory cells associated with a bit line and a word line, and the block BLK is, for example, a data erasing unit.

[0029] The sequencer 14 controls the operation of the entire semiconductor memory device 1 according to the received command CMD. For example, the sequencer 14 controls the row decoder 12 and the sense amplifier 13, etc., and performs various operations such as a write operation and a read operation. In the write operation, the write data DAT received by the semiconductor memory device 1 is stored in the memory cell array 11. In the read operation, the read data DAT is read from the memory cell array 11.

[0030] The row decoder 12 selects a predetermined block BLK to be subjected to various operations such as a read operation and a write operation based on the received address information ADD. The row decoder 12 transmits a voltage to a word line of the selected block BLK.

[0031] The sense amplifier 13 performs a data DAT transmission operation between the memory controller 2 and the memory cell array 11 according to the received address information ADD. That is, in a write operation, the sense amplifier 13 holds the received write data DAT and applies a voltage to the bit line according to the write data DAT. In a read operation, the sense amplifier 13 applies a voltage to the bit line, reads the data stored in the memory cell array 11 as read data DAT, and outputs the read data DAT to the memory controller 2.

[0032] 1.2 Configuration of the Memory Cell Array 11

[0033] Figure 2 1 is a circuit diagram showing an example of an equivalent circuit of the memory cell array 11 included in the semiconductor memory device 1 according to the first embodiment. As an example of the circuit configuration of the memory cell array 11, an example of the circuit configuration of a predetermined block BLK of the memory cell array 11 is shown. Each of the other blocks BLK of the memory cell array 11 has, for example, Figure 2 The same circuit configuration as shown.

[0034] Block BLK includes, for example, 4 string units SU0 to SU3. Each string unit SU includes multiple NAND strings NS. Multiple NAND strings NS are associated one by one with m bit lines BL0 to BL(m-1) (m is an integer greater than 1). Each NAND string NS is connected to the associated bit line BL, and includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate (hereinafter also referred to as a gate) and a charge storage layer, and is capable of storing data in a non-volatile manner. The selection transistors ST1 and ST2 are respectively used for selecting the NAND string NS including the selection transistors ST1 and ST2 during various operations.

[0035] The drain of the selection transistor ST1 of each NAND string NS is connected to the bit line BL associated with the NAND string NS. Memory cell transistors MT0 to MT7 are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. The source of the selection transistor ST2 is connected to the source line SL.

[0036] The gates of the selection transistors ST1 of each NAND string NS included in the string units SU0 to SU3 are commonly connected to the selection gate lines SGD0 to SGD3. The gates of the selection transistors ST2 of each NAND string NS included in the block BLK are commonly connected to the selection gate line SGS. The gates of the memory cell transistors MT0 to MT7 of each NAND string NS included in the block BLK are commonly connected to the word lines WL0 to WL7.

[0037] Each bit line BL is connected to the drain of the selection transistor ST1 of the associated NAND string NS included in each string unit SU of the block BLK. The source line SL is commonly connected to the source of the selection transistor ST2 of each NAND string NS included in the block BLK, and is shared between the string units SU of the block BLK. The source line SL is similarly connected in different blocks BLK, for example, and is shared between the blocks BLK.

[0038] A set of memory cell transistors MT in a string unit SU that are commonly connected to a word line WL is called a unit unit CU, for example. For example, a set of 1-bit data of the same bit held in each memory cell transistor MT in the unit unit CU is called "1 page of data". For example, when multiple bits of data are held in each memory cell by an MLC method, a plurality of "1 page of data" can be held in one unit unit CU.

[0039] The circuit structure of the memory cell array 11 is described above, but the circuit structure of the memory cell array 11 is not limited to the above structure. For example, the number of string units SU included in each block BLK can also be designed to be an arbitrary number. In addition, the number of memory cell transistors MT and the number of selection transistors ST1 and ST2 included in each NAND string NS can be designed to be an arbitrary number. The number of word lines WL and the number of selection gate lines SGD and SGS can be changed according to the number of memory cell transistors MT and the number of selection transistors ST1 and ST2 in the NAND string NS. The NAND string NS may also include a dummy memory cell transistor having the same structure as the memory cell transistor MT and not storing valid data.

[0040] 1.3 Structure of Semiconductor Memory Device 1

[0041] Figure 31 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 1 according to the first embodiment. Figure 3 As shown, the semiconductor memory device 1 has a structure in which a peripheral circuit chip 30 and a unit chip 40 are bonded together in the Z direction. The peripheral circuit chip 30 is provided with a peripheral circuit PRC. The unit chip 40 is provided with a stacked body 410 that functions as a part of the memory cell array 11. In this embodiment, the unit chip 40 is equivalent to the first chip, and the peripheral circuit chip 30 is equivalent to the second chip.

[0042] In the following, for the sake of convenience, directions are defined with reference to the semiconductor substrate SB11 included in the peripheral circuit chip 30. Two directions parallel to a specified surface of the semiconductor substrate SB11, for example, orthogonal to each other, are defined as the X direction and the Y direction. A direction intersecting with a specified surface of the semiconductor substrate SB11 and forming peripheral circuit elements with reference to the surface is defined as the Z direction. The description is made with reference to the case where the Z direction is orthogonal to the X direction and the Y direction, but is not limited to this. In the following, the Z direction is set to "up" and the direction opposite to the Z direction is set to "down" for description, but this description is only for convenience and has nothing to do with, for example, the direction of gravity. In the present embodiment, the Z direction is equivalent to the first direction, the X direction is equivalent to the second direction intersecting with the first direction, and the Y direction is equivalent to the third direction orthogonal to both the first direction and the second direction.

[0043] 1.3.1 Structure of peripheral circuit chip

[0044] The semiconductor substrate SB11 of the peripheral circuit chip 30 contains, for example, silicon (Si). On the upper surface of the semiconductor substrate SB11, a plurality of MOS (Metal Oxide Semiconductor) transistors Tr11 and Tr12 are provided as peripheral circuit elements included in the peripheral circuit PRC. Each transistor Tr11 and Tr12 includes a gate insulator provided on the upper surface of the semiconductor substrate SB11, a gate electrode provided on the upper surface of the gate insulator, and a pair of source / drain regions sandwiching the region below the gate insulator in the semiconductor substrate SB11.

[0045] Conductive layers D11 and D12 are provided above the transistors Tr11 and Tr12. Each of the conductive layers D11 and D12 includes a plurality of mutually insulated wirings. Through such wirings, the source, drain, and gate of each of the transistors Tr11 and Tr12 can be electrically connected to other components.

[0046] A path V11 is provided above a predetermined source region, a drain region, and a gate region of the transistor Tr11. The upper surface of the path V11 is in contact with a predetermined wiring in the conductive layer D11. A path V12 is provided on the upper surface of the predetermined wiring in the conductive layer D11. The upper surface of the path V12 is in contact with a predetermined wiring in the conductive layer D12. A path V13 is provided on the upper surface of the predetermined wiring in the conductive layer D12. The conductive layer PD11 is provided on the upper surface of the path V13.

[0047] The conductive layer PD11 includes, for example, a metal material such as copper (Cu). The upper surface of the conductive layer PD11 constitutes a part of the upper surface 300 of the peripheral circuit chip 30 and is located at substantially the same position as the upper surface 300 of the peripheral circuit chip 30 in the Z direction. The conductive layer PD11 functions as an electrode pad for electrical connection with other chips. Hereinafter, the conductor provided on the upper surface 300 of the peripheral circuit chip 30 and functioning as an electrode pad is referred to as a bonding pad PD11. In addition, the conductor functioning as such an electrode pad is given the reference numeral PD.

[0048] In addition to the bonding pad PD11, a bonding pad PD12 is provided on the upper surface 300 of the peripheral circuit chip 30. The bonding pad PD12 is electrically connected to the transistor Tr12 via the via V13, the conductive layer D12, the via V12, the conductive layer D11, and the via V11.

[0049] In this specification, for example, the via V12 and the wiring in the conductive layer D12 are distinguished, but they may be integrated. The same applies to other vias and conductive layers. In this embodiment, the bonding pads PD11 and PD12 correspond to the second bonding electrodes.

[0050] The connection via the wiring in the conductive layers D11 and D12 is only an example. In the peripheral circuit chip 30, the various vias V11 to V13, the wiring in the conductive layers D11 and D12, and the bonding pad PD11 described above are also provided in other locations. Figure 3 In the figure, for the sake of convenience, all of the various vias V11 to V13 , wirings in the conductive layers D11 and D12 , and the bonding pads PD11 and PD12 are not necessarily shown.

[0051] An interlayer insulating layer 31 is provided between the semiconductor substrate SB11 and the upper surface of the peripheral circuit chip 30. The interlayer insulating layer 31 is provided, for example, in a portion where the transistors Tr11 and Tr12, various vias V11 to V13, wirings in the conductive layers D11 and D12, and the bonding pads PD11 and PD12 are not provided. The interlayer insulating layer 31 contains, for example, oxygen and silicon (e.g., SiO 2) In addition, the interlayer insulating layer 31 may further contain nitrogen or carbon.

[0052] 1.3.2 Structure of unit chip

[0053] The bottom surface 400 of the unit chip 40 is bonded to the upper surface 300 of the peripheral circuit chip 30. In the present embodiment, the bottom surface 400 of the unit chip 40 corresponds to the first bonding surface, and the upper surface of the peripheral circuit chip 30 corresponds to the second bonding surface. The unit chip 40 includes a stacked body 410 that functions as a part of the memory cell array 11. More specifically, each storage column PL included in the stacked body 410 functions as, for example, one NAND string NS. The storage column PL is formed in a manner that penetrates the stacked body 410 in the Z direction.

[0054] The stack 410 has a plurality of conductive layers 411 and insulating layers 412 alternately stacked in the Z direction. The conductive layer 411 is formed in a plate shape extending in the X direction. The conductive layer 411 may also include a stacked film of a barrier conductive film containing nitrogen and titanium (e.g., TiN) and a metal film such as tungsten (W). In addition, the conductive layer 411 may also include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The plurality of conductive layers 411 function, for example, as word lines and gate electrodes of a plurality of storage transistors connected thereto. The insulating layer 412 contains oxygen and silicon (e.g., SiO 2 ) etc. In this embodiment, the conductive layer 411 corresponds to a first conductive layer, and the insulating layer 412 corresponds to a first insulating layer.

[0055] One or more conductive layers 411 at the upper and lower ends of the stack 410 in the Z direction function as, for example, a selection gate line SGS on the source side and a selection gate line SGD on the drain side. The selection gate line SGS on the source side is provided in the upper region of the stack 410, and the selection gate line SGD on the drain side is provided in the lower region of the stack 410. The conductive layer 411 disposed between the selection gate line SGS on the source side and the selection gate line SGD on the drain side functions as a word line WL.

[0056] Figure 4 It is shown Figure 3 The enlarged cross-sectional view of the cross-sectional structure of the periphery of the memory pillar PL is shown. When the memory pillar PL is cut along the XY plane, the memory pillar PL has, for example, a circular or elliptical cross-sectional shape. The memory pillar PL has a core 81, a semiconductor layer 82, and a gate insulating film 83.

[0057] The core portion 81 is provided at the center portion of the memory pillar PL and is formed in a substantially cylindrical shape. The core portion 81 uses an insulator containing silicon, oxygen, and the like.

[0058] The semiconductor layer 82 is formed in a substantially cylindrical shape and is provided so as to surround the outer periphery of the core portion 81. For example, polysilicon (Poly-Si) is used for the semiconductor layer 82. The semiconductor layer 82 is a portion that forms a channel of the memory cell transistor MT or the like.

[0059] The gate insulating film 83 is formed in a substantially cylindrical shape and is provided so as to surround the outer periphery of the semiconductor layer 82. The gate insulating film 83 includes a tunnel insulating film 831, a charge storage film 832, and a blocking insulating film 833 which are stacked and arranged between the semiconductor layer 82 and the conductive layer 411.

[0060] The tunnel insulating film 831 is provided in a manner covering the periphery of the semiconductor layer 82. The tunnel insulating film 831 uses, for example, a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen. The tunnel insulating film 831 functions as a potential barrier between the semiconductor layer 82 and the charge storage film 832. For example, when electrons are injected from the semiconductor layer 82 to the charge storage film 832 (during a write operation), the electrons pass through the potential barrier of the tunnel insulating film 831 (tunnel effect). In addition, when holes are injected from the semiconductor layer 82 to the charge storage film 832 (during an erase operation), the holes pass through the potential barrier of the tunnel insulating film 831.

[0061] The charge storage film 832 is provided in a manner covering the periphery of the tunnel insulating film 831. The charge storage film 832 is, for example, a film containing silicon and nitrogen. The charge storage film 832 has a trapping site for trapping charges in the film. The portion of the charge storage film 832 sandwiched between the conductive layer 411 and the semiconductor layer 82 is used as a storage region of the memory cell transistor MT.

[0062] The blocking insulating film 833 is provided so as to cover the periphery of the charge storage film 832. The blocking insulating film 833 is a film for suppressing reverse tunneling of charges from the conductive layer 411 to the gate insulating film 83 side. The blocking insulating film 833 is, for example, a film containing silicon and nitrogen or a metal and oxygen. The film containing metal and oxygen is, for example, a film containing aluminum oxide.

[0063] The outer periphery of the conductive layer 411 is covered with a barrier insulating film 413. For example, when tungsten is used in the conductive layer 411, the barrier insulating film 413 is selected as a laminated structure film of a film containing silicon and nitrogen and a film containing titanium. Instead of the barrier insulating film 413, a conductive film such as a film containing titanium and nitrogen may be used.

[0064] In the storage column PL, the portion located inside each conductive layer 411, in other words, the intersection portion with the conductive layer 411 functions as a transistor. That is, in the storage column PL, a plurality of transistors are electrically connected in series along the long side direction thereof. Each conductive layer 411 functions as a gate of each transistor. The semiconductor layer 82 functions as a channel of each transistor.

[0065] A portion of each transistor arranged in series along the long side direction of the memory column PL is used as Figure 2 The plurality of memory cell transistors MT shown in the figure function as transistors. In addition, the transistors provided at both ends of the plurality of memory cell transistors MT arranged in series serve as Figure 2 The selection transistors ST1 and ST2 shown are functional.

[0066] like Figure 3 As shown, a bonding pad PD21 is provided on the bottom surface 400 of the unit chip 40. The bonding pad PD21 is bonded to the upper surface of the bonding pad PD11 of the peripheral circuit chip 30. The bottom surface of each bonding pad PD21 constitutes a part of the bottom surface 400 of the unit chip 40, and is located at substantially the same position as the bottom surface of the unit chip 40 in the Z direction. The bonding pad PD21 includes a metal material such as copper (Cu), for example.

[0067] A via V21 is provided on the upper surface of the bonding pad PD21. The upper surface of the via V21 is connected to a prescribed wiring in the conductive layer D12. A via V22 is provided on the upper surface of a prescribed wiring in the conductive layer D21. The upper surface of the via V22 is connected to a prescribed wiring in the conductive layer D22. A via V23 is provided on the upper surface of a prescribed wiring in the conductive layer D22. The upper surface of the via V23 is connected to the lower end of a prescribed storage column PL of the stack 410. Among the wirings in the conductive layer D22, the wiring electrically connected to the via V23 functions as a part of the bit line BL. In the conductive layer D22, the portion that functions as the bit line BL is formed so as to extend along the Y direction.

[0068] A step portion 414 is formed at the end of the stacked body 410. The conductive layer 411 functioning as the word line WL in the step portion 414 is electrically connected to the bonding pad PD22 via the contact C20, the conductive layer D22, the via V22, the conductive layer D21, and the via V21. The bottom surface of the bonding pad PD22 constitutes a part of the bottom surface 400 of the unit chip 40 and is located at substantially the same position as the bottom surface of the unit chip 40 in the Z direction.

[0069] Figure 5 It is shown Figure 3 The cross-sectional view of the cross-sectional structure along the VV line. Figure 5 As shown in FIG. 1 , a portion of the stacked body 410 is divided along the X direction by the inter-block insulating layer 106. Each portion divided by the inter-block insulating layer 106 constitutes Figure 2 In the present embodiment, the inter-block insulating layer 106 corresponds to the second insulating layer.

[0070] like Figure 3 and Figure 5As shown, the unit chip 40 includes a semiconductor layer 100 , an insulating layer 101 , and an insulating layer 102 in this order above a stacked body 410 .

[0071] The semiconductor layer 100 is, for example, a semiconductor layer such as silicon (Si) into which N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) are injected. In addition, a metal such as tungsten (W) or a silicide such as tungsten silicide (WSi) may be provided between the semiconductor layer 100 and the insulating layer 101. The insulating layer 101 is, for example, a layer containing oxygen and silicon (e.g., SiO 2 ) or the like. The insulating layer 101, for example, covers the entire upper surface of the semiconductor layer 100. The insulating layer 102, for example, is a passivation layer made of polyimide or the like.

[0072] In the unit chip 40, an interlayer insulating layer 44 is provided in at least a portion of a portion where the bonding pads PD21, PD22, the vias V21 to V23, the conductive layers D21, D22, and the stacked body 410 are not provided. The interlayer insulating layer 44 contains, for example, oxygen and silicon. In addition, the interlayer insulating layer 44 may further contain nitrogen or carbon.

[0073] 1.3.3 Structure of Bonding Pad

[0074] Next, the structure of the bonding pad is described in detail. In addition, since the bonding structure of the bonding pad PD11 of the peripheral circuit chip 30 and the bonding pad PD21 of the unit chip 40 is the same as or similar to the bonding structure of the bonding pad PD12 of the peripheral circuit chip 30 and the bonding pad PD22 of the unit chip 40, the bonding structure of the bonding pad PD11 of the peripheral circuit chip 30 and the bonding pad PD21 of the unit chip 40 is described as a representative.

[0075] Figure 6 4 is a cross-sectional view showing the cross-sectional structure of the bonding pad PD21 and the dummy pad DP surrounding the unit chip 40. Figure 6 As shown, the interlayer insulating layer 31 includes insulating layers 31a to 31f. Each insulating layer 31a, 31c, and 31e is formed using, for example, dTEOS and contains silicon and oxygen (eg, SiO 2 ). The insulating layer 31b is arranged so as to be sandwiched between the two insulating layers 31a and 31c in the Z direction. The insulating layer 31d is arranged so as to be sandwiched between the two insulating layers 31c and 31e in the Z direction. The insulating layer 31f is arranged below the insulating layer 31e in the Z direction. The insulating layers 31b, 31d, and 31f are, for example, insulating layers containing silicon and nitrogen (for example, SiN).

[0076] In the insulating layers 31a and 31b, recessed portions 32 are formed in a form of opening on the upper surface of the insulating layer 31a. In the insulating layers 31c and 31d, recessed portions 33 are formed in a form of opening on the bottom surface of the recessed portions 32. In the insulating layers 31e and 31f, recessed portions 34 are formed in a form of opening on the bottom surface of the recessed portions 33.

[0077] The bonding pad PD11 is embedded in the recess 32. The bonding pad PD11 includes a barrier metal layer PD11a and a pad material layer PD11b. The barrier metal layer PD11a is formed in a thin film on the inner wall surface and the bottom surface of the recess 32. Insulating layers 31a and 31b are provided outside the barrier metal layer PD11a. The pad material layer PD11b is provided inside the recess 32 via the barrier metal layer PD11a. In the present embodiment, the bonding pad PD11 is equivalent to the second bonding electrode and the second pad.

[0078] A via V13 is embedded in the recess 33. The via V13 includes a barrier metal layer V13a and a via material layer V13b. The barrier metal layer V13a is formed in a thin film on the inner wall surface of the recess 33 and the boundary portion between the via V13 and the conductive layer D12. Insulating layers 31c and 31d are provided outside the barrier metal layer V13a. The via material layer V13b is embedded in the recess 33 via the barrier metal layer V13a. In this embodiment, the conductive layer D12 is equivalent to the third conductive layer, and the via V13 is equivalent to the second via.

[0079] The conductive layer D12 is embedded in the recess 34. The conductive layer D12 includes a barrier metal layer D12a and a conductive material layer D12b. The barrier metal layer D12a is formed in a thin film on the inner wall surface of the recess 34. The conductive material layer D12b is embedded in the recess 34 via the barrier metal layer D12a.

[0080] The interlayer insulating layer 44 includes insulating layers 44a to 44f, similarly to the interlayer insulating layer 31. Each of the insulating layers 44a, 44c, and 44e is formed of, for example, dTEOS and contains silicon and oxygen (eg, SiO 2 ). The insulating layer 44b is arranged so as to be sandwiched between the two insulating layers 44a and 44c in the Z direction. The insulating layer 44d is arranged so as to be sandwiched between the two insulating layers 44c and 44e in the Z direction. The insulating layer 44f is arranged above the insulating layer 44e in the Z direction. The insulating layers 44b, 44d, and 44f are, for example, insulating layers containing silicon and nitrogen (for example, SiN).

[0081] In the insulating layers 44a and 44b, recessed portions 45 are formed to open at the bottom surface of the insulating layer 44a. In the insulating layers 44c and 44d, recessed portions 46 are formed to open at the bottom surface of the recessed portions 45. In the insulating layer 44e, recessed portions 47 are formed to open at the bottom surface of the recessed portions 46.

[0082] A bonding pad PD21 is embedded in the recess 45. The bonding pad PD21 includes a barrier metal layer PD21a and a pad material layer PD21b. The barrier metal layer PD21a is formed in a thin film on the inner wall surface and the bottom surface of the recess 45. Insulating layers 44a and 44b are provided on the outside of the barrier metal layer PD21a. The pad material layer PD21b is provided inside the recess 45 via the barrier metal layer PD21a. The pad material layer PD21b is bonded to the pad material layer PD11b provided therebelow. That is, the bonding pad PD11 and the bonding pad PD21 are electrically connected. In the present embodiment, the bonding pad PD21 is equivalent to the first bonding electrode and the first pad.

[0083] A via V21 is embedded in the recess 46. The via V21 includes a barrier metal layer V21a and a via material layer V21b. The barrier metal layer V21a is formed in a thin film on the inner wall surface of the recess 46 and the boundary between the via V21 and the conductive layer D21. Insulating layers 44c and 44d are provided outside the barrier metal layer V21a. The via material layer V21b is embedded in the recess 46 via the barrier metal layer V21a. In the present embodiment, the via V21 corresponds to the first via.

[0084] A conductive layer D21 is embedded in the recess 47. The conductive layer D21 includes a barrier metal layer D21a and a conductive material layer D21b. The barrier metal layer D21a is formed in a thin film on the inner wall surface of the recess 47. The conductive material layer D21b is embedded in the recess 47 via the barrier metal layer D21a. In this embodiment, the conductive layer D21 corresponds to the second conductive layer.

[0085] In the peripheral circuit chip 30, a recess 35 is also formed in a manner that opens on the upper surface 300. A pad PD13 is embedded in the recess 35. Like the bonding pad PD11, the pad PD13 includes a barrier metal layer PD13a and a pad material layer PD13b. Unlike the bonding pad PD11, the pad PD13 is not connected to the conductive layer D12. In addition, the pad PD13 is Figure 3 and Figure 5 Not shown in the figure.

[0086] In the unit chip 40, a recess 48 is formed in a manner that opens at the bottom surface 400. A pad PD23 is embedded in the recess 48. Like the bonding pad PD21, the pad PD23 includes a barrier metal layer PD23a and a pad material layer PD23b. Unlike the bonding pad PD21, the pad PD23 is not connected to the conductive layer D21. Figure 3 and Figure 5 Not shown in the figure.

[0087] The pad material layer PD13b of the pad PD13 and the pad material layer PD23b of the pad PD23 are bonded to each other. As described above, the pads PD13 and PD23 are not electrically connected to the conductive layers D12 and D21, so the pads PD13 and PD23 are hereinafter referred to as "dummy pads".

[0088] Each barrier metal layer D12a, V13a, PD11a, PD13a, PD21a, PD23a, V21a, D21a is a metal layer containing Ti (titanium) or Ta (tantalum), for example. The pad material layer PD11b, PD13b, PD21b, PD23b, the via material layer V13b, V21b and the conductive material layer D12b, D21b are metal layers containing Cu, for example.

[0089] Hereinafter, the bonding pads PD11 and PD21 bonded to each other are collectively referred to as “bonding pads BP.” In addition, the dummy pads PD13 and PD23 bonded to each other are collectively referred to as “dummy pads DP.” In the present embodiment, the bonding pads BP correspond to bonding electrodes, and the dummy pads DP correspond to dummy electrodes.

[0090] Figure 7 It is shown Figure 6 VII-VII line, in other words, a cross-sectional view of the bottom surface 400 of the unit chip 40. Figure 7 As shown in FIG. 1 , the cross-sectional shape of the bonding pad BP and the dummy pad DP perpendicular to the Z direction is formed into a polygonal shape, specifically, a quadrilateral shape. More specifically, the bonding pad BP is formed into a quadrilateral shape in which two sides S11 and S12 facing each other are parallel to the X direction, and the other two sides S13 and S14 facing each other are parallel to the Y direction. The same is true for the dummy pad DP.

[0091] In the unit chip 40, a plurality of inter-block insulating layers 106a and 106b are arranged at predetermined intervals in the Y direction. Each of the inter-block insulating layers 106a and 106b is formed to extend in the X direction.

[0092] A bonding pad configuration region A10 is provided between the inter-block insulating layers 106a and 106b. In the bonding pad configuration region A10, a plurality of bonding pads BPa are arranged in a staggered manner in the X direction and the Y direction. A plurality of bonding pads BPa are arranged at a predetermined pitch Px10 in the X direction. A plurality of bonding pads BPa are arranged at a predetermined pitch Py10 in the Y direction. The pitch Px10 and the pitch Py10 are set to the same value as each other, for example.

[0093] A bonding pad arrangement region A11 is provided on the opposite side of the inter-block insulating layer 106a from the portion provided with the bonding pads BPa in the Y direction. In the bonding pad arrangement region A11, a plurality of bonding pads BPb are arranged in a staggered pattern similarly to the bonding pad arrangement region A10.

[0094] A dummy pad configuration area A21 is provided in a portion on the opposite side of the portion where the inter-block insulating layer 106a is provided with respect to the bonding pad configuration area A11 in the Y direction. A plurality of dummy pads DPa are provided in the dummy pad configuration area A21. The dummy pads DPa are arranged in a staggered manner in the X direction and the Y direction. The plurality of dummy pads DPa are arranged at a predetermined pitch Px11 in the X direction. The plurality of dummy pads DPa are arranged at a predetermined pitch Py11 in the Y direction. The pitch Px11 and the pitch Py11 are set to different values ​​from each other, for example.

[0095] A bonding pad arrangement region A12 is provided on the opposite side of the inter-block insulating layer 106b from the portion provided with the bonding pads BPa in the Y direction. In the bonding pad arrangement region A12, a plurality of bonding pads BPc are arranged in a staggered pattern similarly to the bonding pad arrangement region A10.

[0096] A dummy pad arrangement region A22 is provided in the portion opposite to the portion where the inter-block insulating layer 106b is provided with respect to the bonding pad arrangement region A12 in the Y direction. In the dummy pad arrangement region A22, a plurality of dummy pads DPb are arranged in a staggered manner similarly to the dummy pad arrangement region A21.

[0097] exist Figure 7In the figure, among the plurality of bonding pads BPa arranged in the bonding pad arrangement area A10, the bonding pad BPa arranged adjacent to the inter-block insulating layer 106a is shown by the reference numeral BPa10. In addition, among the plurality of bonding pads BPb arranged in the bonding pad arrangement area A11, the bonding pad BPb arranged adjacent to the inter-block insulating layer 106a is shown by the reference numeral BPb10. The plurality of bonding pads BPa10 and the plurality of bonding pads BPb10 are arranged in a staggered manner in the X direction and the Y direction. The plurality of bonding pads BPa10 and the plurality of bonding pads BPb10 are arranged at a predetermined pitch Px10 in the X direction. The plurality of bonding pads BPa10 and the plurality of bonding pads BPb10 are arranged at a predetermined pitch Py10 in the Y direction. In this case, the bonding pad BPa10 is equivalent to the first bonding electrode, and the bonding pad BPb10 is equivalent to the second bonding electrode.

[0098] exist Figure 7 In the figure, among the plurality of bonding pads BPa arranged in the bonding pad arrangement region A10, the bonding pad arranged adjacent to the inter-block insulating layer 106b is indicated by the reference numeral BPa11. In addition, among the plurality of bonding pads BPc arranged in the bonding pad arrangement region A12, the bonding pad BPc arranged adjacent to the inter-block insulating layer 106b is indicated by the reference numeral BPc10. The plurality of bonding pads BPa11 and the plurality of bonding pads BPc10 are also arranged in a staggered manner in the X direction and the Y direction, similarly to the bonding pads BPa10 and BPb10. In this case, the bonding pads BPa11 correspond to the first bonding electrode, and the bonding pads BPc10 correspond to the second bonding electrode.

[0099] 1.4 Functions and effects of the semiconductor memory device of this embodiment.

[0100] Figure 8 FIG. 2 shows a cross-sectional structure of a semiconductor memory device 200 according to a comparative example. Figure 8 In the semiconductor memory device 200 of the comparative example shown, a plurality of bonding pads BPa10 arranged in the bonding pad arrangement region A10 and a plurality of bonding pads BPb10 arranged in the bonding pad arrangement region A11 are arranged adjacent to each other in the Y direction. In such an arrangement, the bonding pads BPa10 and the bonding pads BPb10 are arranged close to each other. Therefore, for example Figure 8The coverage of the bonding pads BPa10 and BPb10 in the area A30 shown by the double-dashed line will increase. In addition, the coverage is the ratio of the area of ​​the bonding pads BPa10, BPb10 and other pads to the total area of ​​the area shown by the double-dashed line. If the coverage of the bonding pads BPa10 and BPb10 increases, for example, when the bottom surface 400 of the unit chip 40 is polished using CMP (Chemical Mechanical Polishing), in the interlayer insulating layer 44, the area A31 arranged between the bonding pad BPa10 and the bonding pad BPb10 may be cut more. When the upper surface 300 of the peripheral circuit chip 30 is polished using CMP, the same technical problem may also occur. In the case where the area A31 is cut more, a gap may be formed in this part, resulting in a defective product.

[0101] In this regard, in the semiconductor memory device 1 of the present embodiment, as shown in FIG. Figure 7 As shown, the plurality of bonding pads BPa10 and the plurality of bonding pads BPb10 disposed via the inter-block insulating layer 106a are arranged in a staggered manner in the X direction and the Y direction. In other words, the plurality of bonding pads BPa10 and the plurality of bonding pads BPb10 are alternately disposed in the X direction and alternately disposed in the Y direction.

[0102] According to this configuration, it is possible to reduce Figure 7 1 and 2. The coverage of the bonding pads BPa10 and BPb10 in the region A30 indicated by the two-dot chain line in FIG. As a result, the formation of voids in the region A30 can be suppressed.

[0103] 2 Second Embodiment

[0104] Next, a second embodiment of the semiconductor storage device 1 will be described. The following description will focus on differences from the semiconductor storage device 1 of the first embodiment.

[0105] 2.1 Structure of Bonding Pad

[0106] Fig. 9 1 is a cross-sectional view showing a cross-sectional structure around the bonding pad PD21 of the unit chip 40 according to the present embodiment. Fig.10 is equivalent to Figure 6 The cross-sectional structure along the VII-VII line of FIG. 4 is a cross-sectional view of the cross-sectional structure of the unit chip 40 of this embodiment. Fig. 9As shown, the bonding pad PD11 is not provided in the peripheral circuit chip 30 of the present embodiment. The via V13 is exposed on the upper surface 300 of the peripheral circuit chip 30. The via V13 is bonded to the bonding pad PD21 of the unit chip 40. In the present embodiment, the bonding pad BP includes the via V13 and the bonding pad PD21. In the present embodiment, the via V13 is equivalent to the second bonding electrode.

[0107] The semiconductor memory device 1 of this embodiment is different from the semiconductor memory device 1 of the first embodiment in that no dummy pad DP is provided. Fig.10 As shown, the dummy pads DPa and DPb are not arranged in the dummy pad arrangement areas A21 and A22.

[0108] 2.2 Functions and effects of the semiconductor memory device of this embodiment.

[0109] In the semiconductor memory device 1 of the first embodiment, as Figure 6 and Figure 7 As shown in FIG. 1 , a dummy pad DP is provided at a portion where the bottom surface 400 of the unit chip 40 and the upper surface 300 of the peripheral circuit chip 30 are bonded to each other. Fig. 9 and Fig.10 As shown, no dummy pad DP is provided at the portion where the bottom surface 400 of the unit chip 40 and the upper surface 300 of the peripheral circuit chip 30 are bonded to each other.

[0110] According to this configuration, since the dummy pad DP is not arranged in the dummy pad arrangement area A22, for example, the difference between the coverage of the pads in the bonding pad arrangement area A12 where the bonding pads BPc are arranged and the coverage of the pads in the dummy pad arrangement area A22, i.e., the coverage difference, can be increased. Thus, the formation of a gap on the bonding surface between the unit chip 40 and the peripheral circuit chip 30 can be further suppressed.

[0111] (First Modification)

[0112] Next, a first modification of the semiconductor memory device 1 according to the second embodiment will be described.

[0113] Fig.11 is equivalent to Figure 6 The cross-sectional structure along the VII-VII line of FIG. 4 is a cross-sectional view of the cross-sectional structure of the unit chip 40 of this embodiment. Fig.11 As shown, the cross-sectional shape of the bonding pad BP of this variant example, which is orthogonal to the Z direction, is formed into a quadrilateral shape as follows: two opposite sides S11 and S12 intersect at an angle of 45 degrees relative to the X direction, and the other two opposite sides S13 and S14 intersect at an angle of 45 degrees relative to the Y direction.

[0114] According to this configuration, the distance between, for example, the bonding pad BP30 and the bonding pad BP31 that are adjacently arranged among the plurality of bonding pads BP can be increased, and thus the formation of a void in the region between the bonding pad BP30 and the bonding pad BP31 can be suppressed.

[0115] (Second Modification)

[0116] Next, a second modification of the semiconductor memory device 1 according to the second embodiment will be described.

[0117] Fig.12 is equivalent to Figure 6 The cross-sectional structure along the VII-VII line of FIG. 4 is a cross-sectional view of the cross-sectional structure of the unit chip 40 of this embodiment. Fig.12 As shown, the bonding pad BP of this modified example is formed such that the cross-sectional shape orthogonal to the Z direction is circular. According to this configuration, the distance between the bonding pads BP30 and BP31 arranged adjacent to each other among the plurality of bonding pads BP can be increased, thereby suppressing the formation of a gap in the area between the bonding pads BP30 and BP31.

[0118] (Third Modification)

[0119] Next, a third modification of the semiconductor memory device 1 according to the second embodiment will be described.

[0120] Fig.13 is equivalent to Figure 6 The cross-sectional structure along the VII-VII line of FIG. 4 is a cross-sectional view of the cross-sectional structure of the unit chip 40 of this embodiment. Fig.13 As shown, in the semiconductor memory device 1 of this modification, the pitch Px10 and the pitch Py10 are set to different values. Even with such a configuration, the same or similar operations and effects as those of the semiconductor memory device 1 of the second embodiment can be obtained.

[0121] 3 Other Implementations

[0122] The present disclosure is not limited to the above-mentioned specific examples.

[0123] For example, Figure 5 The inter-block insulating layer 106 shown is formed in a manner that cuts the stacked body 410 along the Z direction, more specifically, cuts all the conductive layers 411 that function as the selection gate line SGS, the word line WL, and the selection gate line SGD. Alternatively, the inter-block insulating layer 106 may be formed in the stacked body 410 in a manner that cuts only the conductive layer 411 that functions as the selection gate line SGD.

[0124] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the scope equivalent to the invention described in the claims.

[0125] [Explanation of Reference Numerals]

[0126] BP: bonding pad (bonding electrode), BPa10: bonding pad (first bonding electrode), BPa11: bonding pad (first bonding electrode), BPb10: bonding pad (second bonding electrode), BPc10: bonding pad (second bonding electrode), D12: conductive layer (third conductive layer), D21: conductive layer (second conductive layer), PL: storage column, PD11: bonding pad (second bonding electrode, second pad), PD21: bonding pad (first bonding electrode, first pad), V13: via (second via, second bonding electrode), V21: via (first via), 1: semiconductor storage device, 30: peripheral circuit chip (second chip), 40: unit chip (first chip), 106: inter-block insulating layer (second insulating layer), 410: stacked body, 411: conductive layer (first conductive layer), 412: insulating layer (first insulating layer).

Claims

1. A semiconductor storage device comprising: a first chip; and A second chip is attached to the first chip on the first direction side. The first chip has: A laminated body formed by alternately stacking a plurality of first conductive layers and first insulating layers in the first direction; a memory pillar that penetrates the stacked body in the first direction and functions as a memory cell transistor at a portion intersecting the first conductive layer; and a plurality of first bonding electrodes provided on a first bonding surface bonded to the second chip, The second chip has a plurality of second bonding electrodes arranged on a second bonding surface bonded to the first chip, The plurality of first bonding electrodes and the plurality of second bonding electrodes are bonded to each other to form a plurality of bonding electrodes. The laminate has a second insulating layer that is provided in a manner extending along a second direction intersecting the first direction, and divides at least a portion of the laminate in a third direction intersecting both the first direction and the second direction. The plurality of bonding electrodes include a first bonding electrode and a second bonding electrode, the first bonding electrode being adjacently arranged on one side of the second insulating layer in the third direction and being arranged at a predetermined interval in the second direction, the second bonding electrode being adjacently arranged on the other side of the second insulating layer in the third direction and being arranged at a predetermined interval in the second direction, The plurality of first bonding electrodes and the plurality of second bonding electrodes are arranged in a staggered pattern in the second direction and the third direction.

2. The semiconductor memory device according to claim 1, wherein: The first chip also has: a second conductive layer electrically connected to the first bonding electrode; and a first path provided between the first bonding electrode and the second conductive layer, The second chip also has a third conductive layer electrically connected to the second bonding electrode, The second bonding electrode is a second via connected to the third conductive layer.

3. The semiconductor memory device according to claim 1, wherein: The first chip also has: a second conductive layer; and a first path provided between the first bonding electrode and the second conductive layer, The second chip also has: a third conductive layer; and A second path is provided between the second bonding electrode and the third conductive layer.

4. The semiconductor memory device according to claim 1, wherein: The first chip also has a second conductive layer electrically connected to the first bonding electrode, The second chip also has a third conductive layer electrically connected to the second bonding electrode, A dummy electrode which is not electrically connected to the second conductive layer and the third conductive layer is further provided at a portion where the first bonding surface of the first chip and the second bonding surface of the second chip are bonded to each other.

5. The semiconductor memory device according to claim 1, wherein: The first chip also has a second conductive layer electrically connected to the first bonding electrode, The second chip also has a third conductive layer electrically connected to the second bonding electrode, In a portion where the first bonding surface of the first chip and the second bonding surface of the second chip are bonded to each other, a dummy electrode which is not electrically connected to the second conductive layer and the third conductive layer is not provided.

6. The semiconductor memory device according to claim 1, wherein: The plurality of first bonding electrodes and the plurality of second bonding electrodes are arranged in a staggered pattern at the same pitch in the second direction and the third direction.

7. The semiconductor memory device according to claim 1, wherein: The plurality of first bonding electrodes and the plurality of second bonding electrodes are arranged in a staggered pattern at different pitches in the second direction and the third direction.

8. The semiconductor memory device according to claim 1, wherein: The bonding electrode has a polygonal cross-sectional shape perpendicular to the first direction.

9. The semiconductor memory device according to claim 8, wherein: The bonding electrode has a quadrilateral cross-sectional shape perpendicular to the first direction.

10. The semiconductor memory device according to claim 9, wherein: The cross-sectional shape of the bonding electrode orthogonal to the first direction is formed into a quadrilateral shape in which two sides facing each other are parallel to the second direction and the other two sides facing each other are parallel to the first direction.

11. The semiconductor memory device according to claim 9, wherein: The cross-sectional shape of the bonding electrode orthogonal to the first direction is formed into a quadrilateral shape in which two sides facing each other intersect the first direction and the second direction and the other two sides facing each other intersect the first direction and the second direction.

12. The semiconductor memory device according to claim 1, wherein: The bonding electrode has a circular cross-sectional shape perpendicular to the first direction.

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