Logic device based on MoS2-Si heterojunction and preparation method thereof

Abstract

The invention relates to a logic device based on a MoS2-Si heterojunction and a preparation method of the logic device. The device comprises a Si substrate layer; the source electrode is located on the lower surface of the Si substrate layer; an isolation region extending from the upper surface of the Si substrate layer to the inside of the Si substrate layer; the MoS2 channel layer is positioned on the upper surfaces of the Si substrate layer and the isolation region; the MoS2 channel layer and the Si substrate layer are bonded to form a MoS2-Si heterojunction; the drain electrode is positioned on the upper surfaces of the isolation region and the MoS2 channel layer; the oxide layer is positioned on the upper surfaces of the MoS2 channel layer and the drain electrode; the grid is located on the upper surface of the oxide layer. According to the device, the MoS2-Si heterojunction can be utilized, and the tunneling current can be increased; and the isolation region is used for blocking the leakage current between the source electrode and the drain electrode, so that the logic device has the advantages of extremely small off-state current, extremely low sub-threshold swing, low interface state and high carrier mobility.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and in particular relates to a logic device based on a MoS2-Si heterojunction and a preparation method thereof. Background Art

[0002] As the basic unit of integrated circuits, in order to continuously increase the transistor density of integrated circuits and steadily improve performance, the device size of field effect transistors has entered the nanometer level. However, the reduction in device size has made the short channel effect and quantum effect problems more serious, which has brought serious power consumption and made it difficult to further reduce the size. To solve this problem, tunneling field effect transistors were proposed. Tunneling field effect transistors are devices that use the phenomenon of band-to-band tunneling (BTBT) between the conduction band and the valence band of carriers in the channel region controlled by the gate electrode to achieve the performance of field effect transistors. Traditional field effect transistors use an external gate voltage to control the channel on the surface of the device channel region to achieve the conversion of the on and off states between the drain and the source, while tunneling field effect transistors use the gate voltage to control the band-to-band tunneling process of carriers in the channel region to achieve the on and off state of the device. Tunneling field effect transistors can break through the subthreshold swing limit of field effect transistors, and the leakage current can be effectively reduced, which is expected to become an ultra-low power semiconductor device.

[0003] However, the existing tunneling field effect transistor has the problem that the tunneling current generated is too small to meet the application requirements. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a logic device based on MoS2-Si heterojunction and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] In the first aspect, the present invention provides a logic device based on MoS2-Si heterojunction, comprising: a Si substrate layer; a source electrode, located on the lower surface of the Si substrate layer; an isolation region, extending from the upper surface of the Si substrate layer to the interior of the Si substrate layer; a MoS2 channel layer, located on the upper surfaces of the Si substrate layer and the isolation region; the MoS2 channel layer is bonded to the Si substrate layer to form a MoS2-Si heterojunction; a drain electrode, located on the upper surfaces of the isolation region and the MoS2 channel layer; an oxide layer, located on the upper surfaces of the MoS2 channel layer and the drain electrode; and a gate electrode, located on the upper surface of the oxide layer.

[0006] In some embodiments, the MoS2 channel layer is formed by stacking 1 to 20 layers of MoS2 thin films.

[0007] In some embodiments, the thickness of each layer of MoS2 film ranges from 0.68 nm to 0.73 nm.

[0008] In some embodiments, a length of the isolation region is greater than a length of the drain.

[0009] In some embodiments, the region of the MoS2 channel layer covered by the vertical projection of the gate constitutes a device tunneling region.

[0010] In some embodiments, the material of the Si substrate layer is a material with a doping concentration of 4e19cm -3 P-type Si substrate.

[0011] In some embodiments, the thickness of the drain electrode located on the upper surface of the MoS2 channel layer is less than the thickness of the oxide layer.

[0012] In some embodiments, the material of the isolation region is SiO2.

[0013] In some embodiments, the material of the drain electrode includes Mo, Al, and Au stacked sequentially from bottom to top.

[0014] In a second aspect, the present invention provides a method for preparing a logic device based on a MoS2-Si heterojunction, which is used to prepare the logic device based on the MoS2-Si heterojunction in the first aspect above; the method comprises: S1, preparing a source electrode on the lower surface of a pretreated Si substrate layer; S2, etching on the upper surface of the Si substrate layer to form a groove, and preparing an isolation region in the groove, wherein the upper surface of the isolation region is flush with the upper surface of the Si substrate layer; S3, preparing a MoS2 channel layer on the upper surfaces of the Si substrate layer and the isolation region by wet transfer; the MoS2 channel layer is bonded to the Si substrate layer to form a MoS2-Si heterojunction; S4, preparing a drain electrode on the upper surfaces of the isolation region and the MoS2 channel layer; S5, preparing an oxide layer on the upper surfaces of the MoS2 channel layer and the drain electrode; S6, preparing a gate electrode on the upper surface of the oxide layer.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] (1) In view of the problem that the tunneling current generated by the existing tunneling field effect transistor is too small to meet the application requirements, the present invention provides a logic device based on MoS2-Si heterojunction, in which a MoS2 channel layer is directly prepared on a Si substrate layer, so that the overlapping area of ​​the two is bonded to form a MoS2-Si heterojunction; since the MoS2 channel layer has good gate control ability, the tunneling width can be reduced, the tunneling area and tunneling probability can be increased, and the tunneling current can be increased by vertical tunneling through the MoS2-Si heterojunction; and an isolation region is used to block the leakage current between the source and the drain, so that the logic device has the advantages of extremely small off-state current, extremely low subthreshold swing, low interface state and high carrier mobility;

[0017] (2) Using a wet transfer method, a MoS2 film of a certain thickness is prepared, and a PMMA film is used. The prepared MoS2 film is transferred to the upper surface of the Si substrate layer and the isolation area, and the rigidity of the polymer PMMA layer is used to ensure that the MoS2 film remains ultra-flat after transfer;

[0018] (3) The thickness of the prepared MoS2 channel layer is very small, at the atomic level, so that the device has a higher channel layer quality and gate control capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the structure of a logic device based on MoS2-Si heterojunction provided in an embodiment of the present invention;

[0020] Figure 2 It is a schematic flow chart of a method for preparing a logic device based on a MoS2-Si heterojunction provided in an embodiment of the present invention.

[0021] Reference numerals:

[0022] 1. Si substrate layer; 2. Source; 3. Isolation region; 4. MoS2 channel layer; 5. Drain; 6. Oxide layer; 7. Gate. DETAILED DESCRIPTION

[0023] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0024] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0025] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0026] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0027] The logic device based on MoS2-Si heterojunction and the preparation method thereof provided by the present invention are now described in detail with reference to the accompanying drawings. Figure 1 Schematic diagram of the structure of a logic device based on MoS2-Si heterojunction provided by an embodiment of the present invention. Figure 1 As shown, the device includes: a Si substrate layer 1; a source electrode 2, located on the lower surface of the Si substrate layer 1; an isolation region 3, extending from the upper surface of the Si substrate layer 1 to the interior of the Si substrate layer 1; a MoS2 channel layer 4, located on the upper surfaces of the Si substrate layer 1 and the isolation region 3; the MoS2 channel layer 4 is bonded to the Si substrate layer 1 to form a MoS2-Si heterojunction; a drain electrode 5, located on the upper surfaces of the isolation region 3 and the MoS2 channel layer 4; an oxide layer 6, located on the upper surfaces of the MoS2 channel layer 4 and the drain electrode 5; and a gate electrode 7, located on the upper surface of the oxide layer 6.

[0028] Here, the MoS2 channel layer 4 is formed by stacking 1 to 20 layers of MoS2 thin film. The MoS2 thin film is N-type MoS2. Moreover, the thickness of each layer of MoS2 thin film ranges from 0.68nm to 0.73nm, preferably 0.71nm. MoS2 thin film is a two-dimensional semiconductor material with an S-Mo-S sandwich layered structure. In each layer, Mo and S atoms are bonded by covalent bonds, and the layers are bonded by weak van der Waals forces. MoS2 thin film has better chemical stability than graphene. At the same time, in high temperature and high humidity environments, the surface of MoS2 thin film is not easily oxidized, corroded, and deactivated, and can maintain excellent performance. In addition, the resistivity of MoS2 thin film changes little with temperature, so it can be used in a wide temperature range.

[0029] It should be noted that the number of layers of the MoS2 thin film corresponding to the MoS2 channel layer 4 is 1 to 20. That is, the thickness of the MoS2 channel layer 4 in the present invention is very small. By using a MoS2 thin film with a very small thickness, the quality of the channel layer and the gate control capability can be improved.

[0030] Here, the material of the Si substrate layer 1 is a doping concentration of 4e19cm -3 P-type Si substrate. N-type MoS2 and P-type Si substrate form a MoS2-Si heterojunction, that is, the area where the MoS2 channel layer 4 is covered by the vertical projection of the gate 7 constitutes the device tunneling area. To ensure that the MoS2 channel layer 4 is completely covered by the vertical projection of the gate 7, the vertical projection of the gate 7 partially covers the isolation region 3. When tunneling occurs, the direction of the electric field is directed from MoS2 to Si, and electrons tunnel from Si to the channel of MoS2 and are swept to the drain region by the electric field, generating a tunneling current. The MoS2-Si heterojunction is a vertical tunneling structure. Compared with the conventional horizontal tunneling method, this vertical tunneling method can reduce the tunneling width while ensuring that the thickness of the MoS2 channel layer 4 is very small, increase the tunneling probability and tunneling area, and thus increase the tunneling current.

[0031] Here, the Si substrate layer 1 adjacent to the source electrode 2 constitutes a source region, the area of ​​the MoS2 channel layer 4 covered by the drain electrode 5 constitutes a drain region, and the oxide layer 6 serves as a dielectric layer of the gate electrode 7. The material of the source electrode 2 is Ni and Au, the material of the gate electrode 7 is TiN, the material of the oxide layer 6 is Al2O3, and the material of the isolation region 3 is SiO2.

[0032] Here, the materials of the drain 5 are Mo, Al and Au stacked in sequence from bottom to top. Metal Mo is a contact metal, and the resistivity of metal Al is lower than that of Mo, which can reduce the parasitic resistance of the metal electrode during testing. Au is used as a contact pad (PAD) surface metal to prevent oxidation and corrosion in subsequent processes. And. The thickness of the drain 5 located on the upper surface of the MoS2 channel layer 4 is less than the thickness of the oxide layer 6, and the height of the drain 5 located on the upper surface of the isolation layer 3 is flush with the height of the drain 5 located on the upper surface of the MoS2 channel layer 4.

[0033] Here, the length of the isolation region 3 is greater than the length of the drain 5. The isolation region 3 can prevent vertical leakage current between the source 2 and the drain 5, so that the current conduction must pass through the channel region under the gate 7 to ensure the device is turned off.

[0034] Corresponding to the aforementioned logic device based on MoS2-Si heterojunction, the present invention also provides a method for preparing a logic device based on MoS2-Si heterojunction. Figure 2 FIG. 1 is a flow chart of a method for preparing a logic device based on a MoS2-Si heterojunction according to an embodiment of the present invention. Figure 2 As shown, the preparation method includes steps S1 to S6. Specifically:

[0035] S1. Prepare a source electrode 2 on the lower surface of the pretreated Si substrate layer 1.

[0036] Here, a P-type Si substrate with a resistivity of 0.001Ω·cm is cleaned by a standard wet method to obtain a pretreated Si substrate layer 1. Specifically, an acetone water bath is used for 5 minutes, an ethanol water bath is used for 5 minutes, and finally, deionized water is used for cleaning and nitrogen is blown dry to obtain a clean substrate surface.

[0037] Here, an electron beam evaporation process (abbreviated as EBE in English) is used to directly heat and evaporate metal Ni and Au to coat the lower surface of the pretreated Si substrate layer 1 to generate the source 2; then, the source 2 is quickly annealed in an atmosphere filled with nitrogen at a temperature of 550°C for 30 seconds to eliminate internal stress.

[0038] S2 . Etching is performed on the upper surface of the Si substrate layer 1 to generate a groove, and an isolation region 3 is prepared in the groove, wherein the upper surface of the isolation region 3 is flush with the upper surface of the Si substrate layer 1 .

[0039] Here, a reactive ion etching process (RIE in English) is used to etch the upper surface of the Si substrate layer 1 to form a square groove; then, a plasma enhanced chemical vapor deposition process (PECVD in English) is used to generate a stacked multilayer SiO2 film in the groove until the thickness of the SiO2 film exceeds the height of the groove, and the preparation is stopped; a chemical mechanical polishing process (CMP in English) is used to polish the SiO2 film until the thickness of the SiO2 film is flush with the height of the groove, and the isolation region 3 is obtained.

[0040] S3. On the upper surface of the Si substrate layer 1 and the isolation region 3, a MoS2 channel layer 4 is prepared by wet transfer; the MoS2 channel layer 4 is bonded to the Si substrate layer 1 to form a MoS2-Si heterojunction.

[0041] Here, the quartz substrate is polished; a certain number of MoS2 thin films are grown on the surface of the polished quartz substrate using a metal-organic chemical vapor deposition (MOCVD) method, and then a layer of 2% polymethyl methacrylate (PMMA) is spin-coated on the surface of the MoS2 thin film, which is then placed on a baking table for baking at a temperature of 100°C for 5-10 minutes to solidify the PMMA film and form a quartz substrate-MoS2-PMMA structure; the quartz substrate / MoS2 / PMMA structure is placed in a 10% by mass NaOH etching solution and heated to 80°C and then kept warm for 2 hours to etch away the quartz substrate to obtain a MoS2 / PMMA thin film; subsequently, polyethylene terephthalate is used (abbreviated as PET in English), transfer the film floating on the surface of NaOH etching solution to deionized water and soak it for 30 minutes to remove the residual etching solution; after cleaning the film, transfer the MoS2 film to the upper surface of Si substrate layer 1 and isolation area 3. The rigidity of the polymer PMMA layer makes the MoS2 film still maintain ultra-flat characteristics after transfer; take it out and let it stand to dry. In order to produce MoS2-Si heterojunction, the device is baked at high temperature for 30 minutes to bond the MoS2 film and Si substrate layer 1, and then slowly cooled to room temperature; here, in order to solve the PMMA residue, acetone vapor is used to steam wash the device for 10 minutes; then, anhydrous ethanol is used to clean the acetone residue on the surface, and after waiting for the anhydrous ethanol to evaporate naturally, the MoS2 channel layer 4 is obtained.

[0042] S4 . Prepare a drain electrode 5 on the upper surface of the isolation region 3 and the MoS 2 channel layer 4 .

[0043] Here, after patterning the upper surface of the MoS2 channel layer 4, an ion beam etching process (EBE in English) is used to etch the upper surface of the MoS2 channel layer 4 using a photoresist as a mask, and then plasma stripping is used to remove the photoresist at the edge of the pattern, and then the surface of the MoS2 channel layer 4 is cleaned; using a metal stripping process, Mo, Al and Au stacked metals are sequentially prepared on the upper surface of the isolation region 3 and the MoS2 channel layer 4 to form a drain 5; wherein Mo is a contact metal, Al is an intermediate metal, and Au is a surface metal for contacting the PAD.

[0044] S5. Prepare an oxide layer 6 on the upper surfaces of the MoS 2 channel layer 4 and the drain electrode 5 .

[0045] Here, firstly, an electron beam evaporation process is used to directly heat and evaporate metal Al to coat a 1 nm metal aluminum film on the upper surface of the MoS2 channel layer 4 and the drain 5. Subsequently, the growth of the aluminum oxide seed layer is completed by natural oxidation, and then the atomic layer deposition process (ALD in English) is used to grow aluminum oxide to generate an oxide layer 6.

[0046] S6 , preparing a gate 7 on the upper surface of the oxide layer 6 .

[0047] Here, a physical vapor deposition process (abbreviated as PVD in English) is used to grow TiN with a metal work function of 4.33 eV on the upper surface of the oxide layer 6 to obtain the gate 7. The length of the gate 7 is greater than the length of the tunneling region formed by the MoS2-Si heterojunction, that is, there is a non-tunneling region inside the logic device, and the non-tunneling region is covered by the gate 7.

[0048] After completing S6, a buffered oxide etchant (BOE) is used to remove the residual oxide on the device surface to obtain a logic device based on the MoS2-Si heterojunction. The device can use its own MoS2-Si heterojunction to reduce the tunneling width, increase the tunneling probability and tunneling area, and thus increase the tunneling current.

[0049] It should be noted that when connected to an external device for testing, it is necessary to sequentially grow Ti, Al and Au metal stacks on the upper surface of the gate 7 .

[0050] In view of the problem that the tunneling current generated by the existing tunneling field effect transistor is too small to meet the application requirements, the present invention provides a logic device based on MoS2-Si heterojunction and a preparation method thereof. The device directly prepares a MoS2 channel layer with a very small thickness on the Si substrate layer, so that the overlapping area of ​​the two is bonded to form a MoS2-Si heterojunction; since the MoS2 channel layer is very thin and has good gate control ability, the tunneling width can be reduced, the tunneling area and tunneling probability can be increased, and the tunneling current can be increased by vertical tunneling through the MoS2-Si heterojunction; and the isolation region is used to block the leakage current between the source and the drain, so that the logic device has the advantages of extremely small off-state current, extremely low subthreshold swing, low interface state and high carrier mobility.

[0051] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A logic device based on MoS2-Si heterojunction, characterized in that: include: Si substrate layer (1); A source electrode (2) located on the lower surface of the Si substrate layer (1); An isolation region (3) extending from the upper surface of the Si substrate layer (1) to the interior of the Si substrate layer (1); A MoS2 channel layer (4) is located on the upper surfaces of the Si substrate layer (1) and the isolation region (3); the MoS2 channel layer (4) is bonded to the Si substrate layer (1) to form a MoS2-Si heterojunction; A drain electrode (5) located on the upper surface of the isolation region (3) and the MoS2 channel layer (4); An oxide layer (6) located on the upper surfaces of the MoS2 channel layer (4) and the drain electrode (5); The gate (7) is located on the upper surface of the oxide layer (6).

2. The logic device based on MoS2-Si heterojunction according to claim 1, characterized in that: The MoS2 channel layer (4) is formed by stacking 1 to 20 layers of MoS2 thin films.

3. The logic device based on MoS2-Si heterojunction according to claim 2, characterized in that: The thickness of each layer of MoS2 film ranges from 0.68nm to 0.73nm.

4. The logic device based on MoS2-Si heterojunction according to claim 1, characterized in that: The length of the isolation region (3) is greater than the length of the drain (5).

5. The logic device based on MoS2-Si heterojunction according to claim 1, characterized in that: The area of ​​the MoS2 channel layer (4) covered by the vertical projection of the gate (7) constitutes the device tunneling area.

6. The logic device based on MoS2-Si heterojunction according to claim 1, characterized in that: The material of the Si substrate layer (1) is a doping concentration of 4e19cm -3 P-type Si substrate.

7. The logic device based on MoS2-Si heterojunction according to claim 1, characterized in that: The thickness of the drain electrode (5) located on the upper surface of the MoS2 channel layer (4) is smaller than the thickness of the oxide layer (6).

8. The logic device based on MoS2-Si heterojunction according to claim 1, characterized in that: The material of the isolation region (3) is SiO2.

9. The logic device based on MoS2-Si heterojunction according to claim 1, characterized in that: The material of the drain electrode (5) comprises Mo, Al and Au stacked in sequence from bottom to top.

10. A method for preparing a logic device based on a MoS2-Si heterojunction, characterized in that: The preparation method is used to prepare a logic device based on a MoS2-Si heterojunction according to any one of claims 1 to 9; the preparation method comprises: S1, preparing a source electrode (2) on the lower surface of the pretreated Si substrate layer (1); S2, etching the upper surface of the Si substrate layer (1) to form a groove, and preparing an isolation region (3) in the groove, wherein the upper surface of the isolation region (3) is flush with the upper surface of the Si substrate layer (1); S3, preparing a MoS2 channel layer (4) on the upper surface of the Si substrate layer (1) and the isolation region (3) by wet transfer; the MoS2 channel layer (4) is bonded to the Si substrate layer (1) to form a MoS2-Si heterojunction; S4, preparing a drain electrode (5) on the upper surface of the isolation region (3) and the MoS2 channel layer (4); S5, preparing an oxide layer (6) on the upper surfaces of the MoS2 channel layer (4) and the drain electrode (5); S6. Preparing a gate (7) on the upper surface of the oxide layer (6).

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