Power device and manufacturing method thereof

Abstract

The invention discloses a power device, a gate structure comprises a gate dielectric layer and a gate conductive material layer, and a gate trench is formed in a first epitaxial layer. A channel region is formed in a bottom region of the first epitaxial layer and a bottom region of the gate trench passes through the channel region. A drift region is formed by the first epitaxial layer located at the top of the channel region. And a drain region which is self-aligned with the side surface of the gate trench is formed in the surface region of the drift region. The top of the drain region is connected to drain electrode metal composed of the front face metal layer. The top of the gate conductive material layer is connected to a gate metal composed of the front metal layer. The source region is composed of a semiconductor substrate, and source electrode metal is formed on the back face of the source region. The invention further discloses a manufacturing method of the power device. According to the invention, a vertical device structure in which the drain metal is led out from the front surface and the source metal is led out from the back surface can be realized, so that the structure can be suitable for source bottom packaging, the back metal layer can be directly connected with the heat dissipation plate through the conductive solder, and the thermal resistance can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a power device. The present invention also relates to a method for manufacturing a power device. Background Art

[0002] Power devices usually adopt a vertical structure. Compared with the lateral structure, the vertical structure has a smaller chip area and lower cost. However, the back side is usually the drain, which is a high potential. Therefore, in the package, it is usually necessary to stick it on the heat sink through thermal conductive insulating glue. The thermal conductivity of insulating glue is not good, which increases the thermal resistance of the chip. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a power device that can realize a vertical device structure in which the drain metal is led out from the front and the source metal is led out from the back, so that it can be suitable for source down packaging, so that the back metal layer can be directly connected to the heat sink through conductive solder, which can greatly reduce thermal resistance. To this end, the present invention also provides a method for manufacturing a power device.

[0004] In order to solve the above technical problems, the power device provided by the present invention comprises:

[0005] A semiconductor substrate heavily doped with a first conductivity type is provided, and a first epitaxial layer doped with a first conductivity type is formed on a top surface of the semiconductor substrate.

[0006] The gate structure comprises a gate dielectric layer formed on the inner surface of a gate trench and a gate conductive material layer filled in the gate trench, wherein the gate trench is formed in the first epitaxial layer.

[0007] A channel region doped with the second conductivity type is formed in a bottom region of the first epitaxial layer, and a bottom region of the gate trench passes through the channel region.

[0008] The first epitaxial layer located on the top of the channel region forms a drift region.

[0009] A drain region heavily doped with the first conductivity type is formed in the surface area of ​​the drift region, and the drain region is self-aligned with the side surface of the corresponding gate trench.

[0010] The top of the drain region is connected to a drain metal composed of a front metal layer through a contact hole penetrating the interlayer film.

[0011] The top of the gate conductive material layer is connected to the gate metal composed of the front metal layer through a contact hole.

[0012] The source region is composed of the semiconductor substrate, and a source metal composed of a back metal layer is formed on the back side of the source region.

[0013] A further improvement is that the channel region is diffused from an ion implantation region formed in a self-aligned manner at the bottom region of the gate trench.

[0014] A further improvement is that the power device comprises a device unit region and a gate lead-out region, and the contact hole on the top of the gate conductive material layer is located in the gate lead-out region.

[0015] A further improvement is that the power device is a trench gate MOSFET or a shield gate trench (SGT) MOSFET.

[0016] When the power device is the SGT MOSFET, the gate structure further includes a source conductive material layer.

[0017] A further improvement is that when the power device is the SGT MOSFET, in each device unit, the source conductive material layer and the gate conductive material layer are formed in the same gate trench, the source conductive material layer is located on top of the gate conductive material layer, the source conductive material layer and the gate conductive material layer are separated by an inter-gate dielectric layer, and the source conductive material layer and the gate trench are separated by a shielding dielectric layer.

[0018] In the gate lead-out region, the source conductive material layer is in direct contact with the gate conductive material layer at the bottom and serves as a part of the gate conductive material layer. The source conductive material layer and the gate trench are isolated by the shielding dielectric layer.

[0019] A further improvement is that the power device also includes a source lead-out area, in which the top of the source conductive material layer is connected to a source connection metal line composed of a front metal layer through a contact hole, and the source connection metal line is connected to the source metal on the back side.

[0020] A further improvement is that, in the source lead-out region, a first doped region heavily doped with the first conductivity type is further formed on the surface of the drift region, and the top of the first doped region is connected to the source connection metal line through a contact hole.

[0021] A further improvement is that the power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0022] In order to solve the above technical problems, the present invention provides a method for manufacturing a power device, comprising the following steps:

[0023] A semiconductor substrate heavily doped with a first conductivity type is provided and a first epitaxial layer doped with a first conductivity type is formed on a top surface of the semiconductor substrate.

[0024] A hard mask layer is formed and the hard mask layer is pattern-etched to define a formation area of ​​a gate trench.

[0025] The first epitaxial layer is etched using the hard mask layer as a mask to form a gate trench.

[0026] Ions of the second conductivity type are implanted into the first epitaxial layer at the bottom region of the gate trench to form a channel region, and then the hard mask layer is removed; the first epitaxial layer at the top of the channel region constitutes a drift region.

[0027] A gate structure is formed in the gate trench, including: forming a gate dielectric layer on the inner surface of the gate trench and filling a gate conductive material layer.

[0028] Ion implantation of heavy doping of the first conductivity type is performed to form a drain region in a surface area of ​​the drift region located in a device cell region, and the drain region is self-aligned with a side surface of the gate trench.

[0029] An interlayer film, a contact hole and a front metal layer are formed, and the front metal layer is patterned to form a drain metal and a gate metal; the top of the drain region is connected to the drain metal through a contact hole; and the top of the gate conductive material layer is connected to the gate metal through a contact hole.

[0030] The source region is composed of the semiconductor substrate, a back metal layer is formed on the back side of the source region and the back metal layer is used to form a source metal.

[0031] A further improvement is that the power device comprises the device unit region and a gate lead-out region, and the contact hole on the top of the gate conductive material layer is located in the gate lead-out region.

[0032] A further improvement is that the power device is a trench gate MOSFET or a SGT MOSFET.

[0033] When the power device is the SGT MOSFET, the gate structure further includes a source conductive material layer.

[0034] A further improvement is that when the power device is the SGT MOSFET, in the step of forming the gate structure in the gate trench, the top surface of the formed gate conductive material layer is lower than the top surface of the gate trench, and the gate conductive material layer is located in the bottom area of ​​the gate trench. After forming the gate conductive material layer, the method further includes:

[0035] An inter-gate dielectric layer is formed on the top surface of the gate conductive material layer in each of the gate trenches outside the gate lead-out region, and the top surface of the gate conductive material layer in the gate trenches in the gate lead-out region is exposed.

[0036] A shielding dielectric layer is formed, wherein the shielding dielectric layer is formed on the side surface of each gate trench located above the top surface of the gate conductive material layer.

[0037] A source conductive material layer is filled in the gate trench; in each device unit, the source conductive material layer and the gate conductive material layer are formed in the same gate trench, the source conductive material layer is located on the top of the gate conductive material layer, an inter-gate dielectric layer is separated between the source conductive material layer and the gate conductive material layer, and a shielding dielectric layer is separated between the source conductive material layer and the gate trench; in the gate lead-out region, the source conductive material layer is in direct contact with the gate conductive material layer at the bottom and serves as a part of the gate conductive material layer, and the source conductive material layer and the gate trench are separated by the shielding dielectric layer.

[0038] A further improvement is that the power device also includes a source lead-out area, in which the top of the source conductive material layer is connected to a source connection metal line composed of a front metal layer through a contact hole, and the source connection metal line is connected to the source metal on the back side.

[0039] A further improvement is that in the source lead-out region, a first doped region heavily doped with a first conductive type is also formed on the surface of the drift region, the first doped region and the drain region are formed simultaneously using the same ion implantation process, and the top of the first doped region is connected to the source connection metal line through a contact hole.

[0040] A further improvement is that the process conditions for ion implantation to form the channel region include: an implantation energy of 40keV to 120keV, an implantation dose of 1e12cm -2 ~1e13cm -2 .

[0041] A further improvement is that the power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0042] The present invention adopts a structure in which the channel region is formed in the bottom region of the gate trench by self-alignment, and the drift region is composed of an epitaxial layer located at the top of the channel region, namely, a first epitaxial layer. In this way, the source region is realized by a semiconductor substrate located at the bottom of the channel region, and the drain region is realized by a front injection region. Therefore, the present invention can realize a vertical device structure in which the drain metal is led out from the front and the source metal is led out from the back, so that it can be suitable for source bottom packaging, so that the back metal layer can be directly connected to the heat sink through conductive solder, which can greatly reduce thermal resistance. In addition, the source is directly led out from the back, which can also reduce the parasitic inductance of the source, which is conducive to improving the switching speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0044] Figure 1 A schematic diagram of the structure of a power device according to an embodiment of the present invention;

[0045] Figure 2A-2E It is a schematic diagram of the device structure in each step of the method for manufacturing a power device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] like Figure 1 As shown, a schematic diagram of the structure of a power device according to an embodiment of the present invention is shown; the power device according to an embodiment of the present invention comprises:

[0047] A semiconductor substrate 1 is heavily doped with a first conductivity type, and a first epitaxial layer 2 doped with a first conductivity type is formed on the top surface of the semiconductor substrate 1 .

[0048] In the embodiment of the present invention, the higher the doping concentration of the first epitaxial layer 2 and the lower the thickness of the first epitaxial layer 2, the lower the breakdown voltage that the device can withstand, and vice versa; the doping concentration of the first epitaxial layer 2 can be uniform, or it can be multi-layer, two-layer or three-layer, or it can be gradual.

[0049] The semiconductor substrate 1 includes a silicon substrate.

[0050] The gate structure includes a gate dielectric layer 5 formed on the inner surface of a gate trench and a gate conductive material layer 6 filled in the gate trench. The gate trench is formed in the first epitaxial layer 2 .

[0051] In the embodiment of the present invention, the gate conductive material layer 6 is made of polysilicon, namely gate polysilicon (gatepoly), and the gate conductive material layer 6 is obtained by Gate Poly deposition and etching back. In other embodiments, the gate conductive material layer 6 may be made of metal such as tungsten.

[0052] In the embodiment of the present invention, the gate dielectric layer 5 is a gate oxide layer. In some embodiments, for a low voltage MOSFET with a breakdown voltage of 12V to 60V, the thickness of the gate oxide is usually For higher voltage MOSFETs such as those with a breakdown voltage above 60V, the thickness of the common Gate Oxide is usually between.

[0053] A channel region 4 doped with the second conductivity type is formed in the bottom region of the first epitaxial layer 2 , and the bottom region of the gate trench passes through the channel region 4 .

[0054] The drift region is composed of the first epitaxial layer 2 located on top of the channel region 4.

[0055] A drain region 10 heavily doped with the first conductivity type is formed in the surface area of ​​the drift region, and the drain region 10 is self-aligned with the side surface of the corresponding gate trench.

[0056] The top of the drain region 10 is connected to the drain metal composed of the front metal layer through a contact hole, i.e., a through hole 13a, which passes through the interlayer film 11. Figure 1 The metal trace 12a formed by patterning a front metal layer shown in the figure is a drain metal trace, which is a component of the drain metal. The drain metal usually also includes a block-shaped drain pad, and the drain metal trace will eventually be connected to the drain pad.

[0057] The top of the gate conductive material layer 6 is connected to the gate metal composed of the front metal layer through the contact hole 13b.

[0058] Figure 1 The metal trace 12b formed by patterning a front metal layer shown in the figure is a gate metal trace. The gate metal trace, as a component of the gate metal, usually also includes a block-shaped gate pad, and the gate metal trace will finally be connected to the gate pad.

[0059] The source region is composed of a semiconductor substrate 1, and a source metal composed of a back metal layer (not shown) is formed on the back side of the source region.

[0060] In the embodiment of the present invention, the channel region 4 is formed by diffusion of an ion implantation region which is self-aligned and formed in the bottom region of the gate trench. Figure 1, the structure of the ion implantation region after ion implantation of the channel region 4 and before impurity diffusion is shown. After the ion implantation impurities of the channel region 4 diffuse, the adjacent channel regions 4 will be laterally connected together; thus, the first epitaxial layer 2 located at the top of the channel region 4 constitutes a drift region. The first conductivity type heavily doped impurities of the source region will further diffuse upward to the bottom surface of the gate trench, so that the gate trench will pass through the channel region 4, and the channel region 4 will be completely covered by the side of the gate conductive material layer 6 and form a vertical longitudinal conductive channel, thereby realizing the control of the longitudinal conductive channel through the gate conductive material layer 6. The first conductivity type heavily doped impurities of the source region will further diffuse upward to the bottom surface of the gate trench, which can be realized by thermal annealing diffusion or further increasing the first conductivity type heavily doped ion implantation.

[0061] In the embodiment of the present invention, the power device includes a device unit region 101 and a gate lead-out region 102, and the contact hole on the top of the gate conductive material layer 6 is located in the gate lead-out region 102. Figure 1 In the cross-sectional position shown, the device unit region 101 is located on the left side of the dotted line AA, and the gate lead-out region 102 is located between the dotted line AA and the dotted line BB.

[0062] In the embodiment of the present invention, the power device is an SGT MOSFET. Figure 1 The SGT MOSFET is used as an example for description. In other embodiments, the power device may be a trench gate MOSFET.

[0063] like Figure 1 As shown, when the power device is an SGT MOSFET, the gate structure further includes a source conductive material layer 9 .

[0064] In each device unit, the source conductive material layer 9 and the gate conductive material layer 6 are formed in the same gate trench, the source conductive material layer 9 is located on the top of the gate conductive material layer 6, the source conductive material layer 9 and the gate conductive material layer 6 are separated by an inter-gate dielectric layer, and the source conductive material layer 9 and the gate trench are separated by a shielding dielectric layer 8. In the embodiment of the present invention, the inter-gate dielectric layer is also implemented by the shielding dielectric layer 8, and the two are formed at the same time. In other embodiments, it can also be that the process structure of the inter-gate dielectric layer is independent of the process structure of the shielding dielectric layer 8, and the formation processes of the two are separate.

[0065] In the embodiment of the present invention, the source conductive material layer 9 is made of polysilicon, namely source polysilicon (sourcepoly), and is formed by polysilicon deposition (deposition) and back etching. In other embodiments, the source conductive material layer 9 can also be made of metal such as tungsten.

[0066] The shielding dielectric layer 8 is usually formed by a thermal oxidation process. In this case, it is a shielding oxide layer (ShieldOxide). The thickness of the shielding dielectric layer 8 is related to the breakdown voltage of the device. The higher the breakdown voltage, the thicker the shielding dielectric layer 8 is required. For 20-30V devices, the thickness of the thermal oxidation or shielding dielectric layer 8 is usually between 0.1 and 0.2 V. This hot oxide can be used as the isolation between the subsequent source conductive material layer 9 such as the source polysilicon and the silicon of the semiconductor substrate 1, that is, as the shielding dielectric layer 8. The Source Poly depletes the drift region laterally, thereby greatly increasing the doping concentration of the drift region without reducing the breakdown voltage of the device; it can also be used as the isolation between the gate conductive material layer 6 such as the gate polysilicon (Gate Poly) and the Source Poly, that is, as the inter-gate dielectric layer. Because this thickness is usually thicker than the thickness of the Gate Oxide, it will not increase its gate leakage.

[0067] In the gate lead-out region 102 , the source conductive material layer 9 a is in direct contact with the bottom gate conductive material layer 6 a and serves as a part of the gate conductive material layer 6 a . The source conductive material layer 9 a and the gate trench are isolated by a shielding dielectric layer 8 . Figure 1 In the figure, the source conductive material layer 9a is marked with a mark 9a, and the gate conductive material layer 6a is marked with a mark 6a. In the formation process, the source conductive material layer 9a and the source conductive material layer 9 in the device unit area 101 are formed at the same time; the gate conductive material layer 6 in each gate trench will be interconnected, that is, the gate conductive material layer 6 in the device unit area 101 will be connected to the gate conductive material layer 6a and connected to the gate metal through the source conductive material layer 9a. The contact hole 13b connected to the gate metal is only set on the top of the source conductive material layer 9a, and the contact hole 13b is not set on the top of the gate conductive material layer 6 in the device unit area 101.

[0068] In an embodiment of the present invention, the power device further includes a source lead-out region 103, in which the top of the source conductive material layer 9 is connected to a source connection metal line composed of a front metal layer through a contact hole 13c, and the source connection metal line is connected to the source metal on the back. Figure 1 The metal trace 12c formed by patterning a front metal layer shown in the figure is a component of a source connection metal line, and the source connection metal line will eventually be connected to the source metal on the back side.

[0069] In the source lead-out region 103 , a first doped region 10 a heavily doped with the first conductivity type is further formed on the surface of the drift region, and the top of the first doped region 10 a is connected to the source connection metal line through a contact hole 13 d .

[0070] In order to increase the reliability of the product, the following front structures are also included: a passivation layer, a polyimide layer and other film layer structures.

[0071] In some embodiments, it also includes:

[0072] In the selected area, a channel contact region formed by multiple high-energy ion implantations and in contact with the channel region 4 is included, a contact hole is formed on the top of the channel contact region and connected to the source connection metal line 12c through the contact hole on the top, which can improve the single pulse avalanche energy (EAS) capability of the device. For N-type devices, the implanted impurities in the channel contact region include boron.

[0073] In the embodiment of the present invention, the power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the power device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0074] In the embodiment of the present invention, the channel region 4 is formed in the bottom region of the gate trench by self-alignment, and the drift region is composed of the epitaxial layer located at the top of the channel region 4, namely the first epitaxial layer 2. In this way, the source region is realized by the semiconductor substrate 1 located at the bottom of the channel region 4, and the drain region 10 is realized by the front injection region. Therefore, the embodiment of the present invention can realize a vertical device structure in which the drain metal is led out from the front and the source metal is led out from the back, so that it can be suitable for source bottom packaging, so that the back metal layer can be directly connected to the heat sink through the conductive solder, which can greatly reduce the thermal resistance. In addition, the source is directly led out from the back, which can also reduce the parasitic inductance of the source, which is conducive to improving the switching speed.

[0075] like FIG. 2A to FIG. 2E , which is a schematic diagram of the device structure in each step of the method for manufacturing a power device according to an embodiment of the present invention; the method for manufacturing a power device according to an embodiment of the present invention comprises the following steps:

[0076] Step 1: Figure 2A As shown, a semiconductor substrate 1 heavily doped with a first conductivity type is provided and a first epitaxial layer 2 doped with a first conductivity type is formed on a top surface of the semiconductor substrate 1 .

[0077] In the method of the embodiment of the present invention, the higher the doping concentration of the first epitaxial layer 2 and the lower the thickness of the first epitaxial layer 2, the lower the breakdown voltage that the device can withstand, and vice versa; the doping concentration of the first epitaxial layer 2 can be uniform, or it can be multi-layer, two-layer or three-layer, or it can be gradual.

[0078] The semiconductor substrate 1 includes a silicon substrate.

[0079] Step 2: Figure 2BAs shown, a hard mask layer (HM) 3 is formed and patterned and etched to define a formation region of a gate trench.

[0080] In some embodiments, the material of the hard mask layer 3 is SiO 2 .

[0081] Step 3: Figure 2B As shown, the first epitaxial layer 2 is etched using the hard mask layer 3 as a mask to form a gate trench.

[0082] The etching depth of the gate trench depends on the breakdown voltage of the device; the higher the breakdown voltage required by the device, the deeper the etching depth.

[0083] Step 4: Figure 2B As shown, ions of the second conductivity type are implanted to form a channel region 4 in the first epitaxial layer 2 at the bottom region of the gate trench, and then the hard mask layer 3 is removed; the first epitaxial layer 2 at the top of the channel region 4 constitutes a drift region.

[0084] In some embodiments, the process conditions for ion implantation to form the channel region 4 include: an implantation energy of 40 keV to 120 keV, an implantation dose of 1e12 cm -2 ~1e13cm -2 Taking an N-type device as an example, the implanted impurities of the ion implantation in the channel region 4 include boron.

[0085] In the mesa between the gate trenches, the first epitaxial layer 2 cannot be implanted into the area covered by the hard mask layer 3 because it is blocked by the hard mask layer 3.

[0086] The doping concentration distribution of the channel region 4 is related to the implanted energy dose and the subsequent thermal process; the channel region 4 can be implanted once, twice, or multiple times; it can be vertically implanted or angled.

[0087] Then the hard mask layer 3 is removed; then the sacrificial oxide layer (SAC Oxide) is grown and removed, which is used to repair the surface morphology of the semiconductor substrate 1 material such as silicon after etching during the gate trench etching. In some embodiments, the temperature condition for the thermal oxidation growth of SAC Oxide is 900 degrees Celsius, and the growth thickness is or

[0088] Step 5: forming a gate structure in the gate trench, including the following steps:

[0089] Step 51: Figure 2C As shown, a gate dielectric layer 5 is formed on the inner surface of the gate trench.

[0090] In the method of the embodiment of the present invention, the gate dielectric layer 5 is a gate oxide layer. In some embodiments, for a low voltage MOSFET with a breakdown voltage of 12V to 60V, the thickness of the gate oxide is usually For higher voltage MOSFETs such as those with a breakdown voltage above 60V, the thickness of the common Gate Oxide is usually between.

[0091] Step 52: Figure 2C As shown, the gate conductive material layer 6 is filled and etched back. In the method of the embodiment of the present invention, the power device includes a device unit area 101 and a gate lead-out area 102. The location of the device unit area 101 and the gate lead-out area 102 is shown in FIG. Figure 1 As shown; Figure 2C In the figure, the gate conductive material layer located in the gate lead-out region 102 is marked separately with a mark 6a.

[0092] In the embodiment of the present invention, the gate conductive material layer 6 is made of polysilicon, i.e., gate polysilicon (gatepoly), and the gate conductive material layer 6 is obtained by depositing Gate Poly and etching back (etch back). In other embodiments, the gate conductive material layer 6 may be made of metal such as tungsten.

[0093] In the method of the embodiment of the present invention, the power device is an SGT MOSFET. In other embodiments, the power device may be a trench gate MOSFET or an SGT MOSFET.

[0094] When the power device is an SGT MOSFET, the gate structure further includes a source conductive material layer 9. In step 52, as Figure 2C As shown, the top surface of the formed gate conductive material layer 6 is lower than the top surface of the gate trench, and the gate conductive material layer 6 is located in the bottom area of ​​the gate trench. After the gate conductive material layer 6 is formed, the following sub-steps are also included:

[0095] Step 53: Figure 2D As shown, an inter-gate dielectric layer is formed on the top surface of the gate conductive material layer 6 in each gate trench outside the gate lead-out region 102, and the top surface of the gate conductive material layer 6a in the gate trench of the gate lead-out region 102 is exposed.

[0096] A shielding dielectric layer 8 is formed. The shielding dielectric layer 8 is formed on the side surface of each gate trench located above the top surface of the gate conductive material layer 6 .

[0097] In the method of the embodiment of the present invention, the inter-gate dielectric layer and the shielding dielectric layer 8 are formed simultaneously by the same process. In step 53, before forming the shielding dielectric layer 8, the method further includes:

[0098] A protective dielectric layer 7 is formed and pattern-etched so that the protective dielectric layer 7 is only located on the top surface of the gate conductive material layer 6a in the gate lead-out region 102. The material of the protective dielectric layer 7 is different from that of the shielding dielectric layer 8.

[0099] Then, the shielding dielectric layer 8 is formed, and the shielding dielectric layer 8 will not be formed in the formation area of ​​the protective dielectric layer 7. In some embodiments, the protective dielectric layer 7 is a silicon nitride layer, and the shielding dielectric layer 8 is a shield oxide layer (Shield Oxide) formed by a thermal oxidation process, so that under the protection of the protective dielectric layer 7, the thermal oxidation process cannot form the shielding dielectric layer 8 on the top surface of the gate conductive material layer 6a in the gate lead-out area 102.

[0100] In some embodiments, the shielding dielectric layer 8 may be an oxide layer, and a portion of the shielding dielectric layer 8 may be formed by thermal oxygen growth and another portion may be formed by oxide deposition.

[0101] Afterwards, if Figure 2E As shown, the protective dielectric layer 7 is removed, so that the top surface of the gate conductive material layer 6a in the gate lead-out region 102 is exposed.

[0102] The thickness of the shielding dielectric layer 8 is related to the breakdown voltage of the device. The higher the breakdown voltage, the thicker the shielding dielectric layer 8 is required. For 20-30V devices, the thickness of the thermal oxide, i.e. the shielding dielectric layer 8, is usually This hot oxide can be used as the isolation between the subsequent source conductive material layer 9 such as the source polysilicon (Source Poly) and the silicon of the semiconductor substrate 1, that is, as the shielding dielectric layer 8. The Source Poly depletes the drift region laterally, thereby greatly increasing the doping concentration of the drift region without reducing the breakdown voltage of the device; it can also be used as the isolation between the gate conductive material layer 6 such as the gate polysilicon (Gate Poly) and the Source Poly, that is, as the inter-gate dielectric layer. Because this thickness is usually thicker than the thickness of the Gate Oxide, it will not increase its gate leakage.

[0103] Step 54: Figure 2EAs shown, a source conductive material layer 9 is filled in the gate trench; in each device unit, the source conductive material layer 9 and the gate conductive material layer 6 are formed in the same gate trench, the source conductive material layer 9 is located on the top of the gate conductive material layer 6, the source conductive material layer 9 and the gate conductive material layer 6 are separated by an inter-gate dielectric layer, and the source conductive material layer 9 and the gate trench are separated by a shielding dielectric layer 8; in the gate lead-out region 102, the source conductive material layer is represented by a single mark 9a, the source conductive material layer 9a is in direct contact with the bottom gate conductive material layer 6a and serves as a part of the gate conductive material layer 6a, and the source conductive material layer 9 and the gate trench are separated by a shielding dielectric layer 8. The gate conductive material layer 6 outside the gate lead-out region 102 will be connected to the gate conductive material layer 6a in the gate lead-out region 102.

[0104] In the embodiment of the present invention, the source conductive material layer 9 is made of polysilicon, i.e., source polysilicon (sourcepoly), and is formed by polysilicon deposition and etching back. In other embodiments, the source conductive material layer 9 may be made of metal, such as tungsten.

[0105] In some embodiments, the protective dielectric layer 7 can be omitted to achieve a structure in which the gate conductive material layer 6a and the source conductive material layer 9a are in direct contact, including:

[0106] After the gate conductive material layer 6 is formed, the shielding dielectric layer 8 is directly formed by a thermal oxidation process.

[0107] Then, the gate lead-out region 102 is opened by a photolithography process and the shielding dielectric layer 8 on the top of the gate conductive material layer 6a in the gate lead-out region 102 is removed, so that the top surface of the gate conductive material layer 6a in the gate lead-out region 102 is exposed.

[0108] In some embodiments, in order to realize a structure in which the gate conductive material layer 6a and the source conductive material layer 9a are in direct contact, the protective dielectric layer 7 can be omitted and the process of removing the shielding dielectric layer 8 on the top of the gate conductive material layer 6a in the gate lead-out region 102 can be further omitted. In this case, the steps in step five include:

[0109] After the gate conductive material layer 6 is formed, the shielding dielectric layer 8 is directly formed by a thermal oxidation process.

[0110] Then, a source conductive material layer 9 is formed.

[0111] Afterwards, a photolithography process is used to open the gate lead-out region 102 and remove the source conductive material layer 9a of the gate lead-out region 102. In the subsequent contact hole formation process, the contact hole 13b on the top of the gate conductive material layer 6a is a deep contact hole and reaches below the top surface of the gate conductive material layer 6a and contacts the gate conductive material layer 6a.

[0112] Step 6: Figure 1 As shown, ion implantation of a heavily doped first conductivity type is performed to form a drain region 10 in a surface region of a drift region in a device cell region 101 , and the drain region 10 is self-aligned with the side surface of a gate trench.

[0113] In the method of the embodiment of the present invention, the power device further includes a source lead-out region 103 .

[0114] The ion implantation of the drain region 10 also forms a first doped region 10 a heavily doped with the first conductivity type on the surface of the drift region in the source lead-out region 103 .

[0115] Step 7: Figure 1 As shown, an interlayer film 11, a contact hole and a front metal layer are formed, and the front metal layer is patterned to form a drain metal and a gate metal; Figure 1 Contact holes 103a, 103b, 103c and 103d are shown in FIG.

[0116] The top of the drain region 10 is connected to a drain metal wiring 12a through a contact hole 103a, and the drain metal wiring 12a is a component of the drain metal.

[0117] The contact hole 13c on the top of the gate conductive material layer 6 is only located in the gate lead-out region 102, and no contact hole is provided on the top of the gate conductive material layer 6 in the device unit region 101. The gate conductive material layer 6 is connected to the gate conductive material layer 106a in the gate lead-out region 102 and is connected to the gate metal wiring 12b through the contact hole 13b on the top of the source conductive material layer 9a, and the gate metal wiring 12b is a component of the gate metal.

[0118] In the source lead-out region 103, the top of the source conductive material layer 9 is connected to a source connection metal line 12c composed of a front metal layer through a contact hole 13c, and the source connection metal line 12c is connected to the source metal on the back side.

[0119] The top of the first doping region 10a is connected to the source connection metal line 12c through the contact hole 13d.

[0120] In some embodiments, in order to increase the reliability of the product, the following front processes may be included later:

[0121] Deposit film structures such as Passivation and Polyimide on the surface.

[0122] In some embodiment methods, further comprising:

[0123] In the selected area, a channel contact region in contact with the channel region 4 is formed by multiple high-energy ion implantations, and then a contact hole is formed on the top of the channel contact region and connected to the source connection metal line 12c, which can enhance the EAS capability of the device.

[0124] Step 8: Figure 1 As shown, the back side process is performed:

[0125] A source region is formed, and the source region is composed of the thinned semiconductor substrate 1. In some embodiments, the source region can be further formed by ion implantation of a first conductive type heavy doping on the basis of the thinning of the semiconductor substrate 1.

[0126] A back metal layer is formed on the back side of the source region and a source metal is formed from the back metal layer.

[0127] In the embodiment of the present invention, the power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the power device can be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0128] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A power device, characterized in that: include: A semiconductor substrate heavily doped with a first conductivity type, a first epitaxial layer doped with the first conductivity type formed on a top surface of the semiconductor substrate; A gate structure, comprising a gate dielectric layer formed on an inner surface of a gate trench and a gate conductive material layer filled in the gate trench, wherein the gate trench is formed in the first epitaxial layer; A channel region doped with a second conductivity type is formed in a bottom region of the first epitaxial layer, and a bottom region of the gate trench passes through the channel region; A drift region is formed by the first epitaxial layer located on the top of the channel region; A drain region heavily doped with a first conductivity type is formed in a surface region of the drift region, and the drain region is self-aligned with a side surface of the corresponding gate trench; The top of the drain region is connected to the drain metal composed of the front metal layer through a contact hole penetrating the interlayer film; The top of the gate conductive material layer is connected to the gate metal composed of the front metal layer through a contact hole; The source region is composed of the semiconductor substrate, and a source metal composed of a back metal layer is formed on the back side of the source region.

2. The power device according to claim 1, characterized in that: The channel region is diffused from an ion implantation region that is self-aligned and formed in the bottom region of the gate trench.

3. The power device according to claim 1, characterized in that: The power device comprises a device unit region and a gate lead-out region, and the contact hole on the top of the gate conductive material layer is located in the gate lead-out region.

4. The power device according to claim 3, characterized in that: The power device is a trench gate MOSFET or a SGTMOSFET; When the power device is the SGT MOSFET, the gate structure further includes a source conductive material layer.

5. The power device according to claim 4, characterized in that: When the power device is the SGT MOSFET, in each device unit, the source conductive material layer and the gate conductive material layer are formed in the same gate trench, the source conductive material layer is located on top of the gate conductive material layer, an inter-gate dielectric layer is separated between the source conductive material layer and the gate conductive material layer, and a shielding dielectric layer is separated between the source conductive material layer and the gate trench; In the gate lead-out region, the source conductive material layer is in direct contact with the gate conductive material layer at the bottom and serves as a part of the gate conductive material layer. The source conductive material layer and the gate trench are isolated by the shielding dielectric layer.

6. The power device according to claim 5, characterized in that: The power device also includes a source lead-out region, in which the top of the source conductive material layer is connected to a source connection metal line composed of a front metal layer through a contact hole, and the source connection metal line is connected to the source metal on the back side.

7. The power device according to claim 6, characterized in that: In the source lead-out region, a first doped region heavily doped with a first conductivity type is further formed on the surface of the drift region, and a top of the first doped region is connected to the source connection metal line through a contact hole.

8. The power device according to any one of claims 1 to 7, characterized in that: The power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

9. A method for manufacturing a power device, characterized in that: The steps include: Providing a semiconductor substrate heavily doped with a first conductivity type and forming a first epitaxial layer doped with a first conductivity type on a top surface of the semiconductor substrate; Forming a hard mask layer and pattern-etching the hard mask layer to define a formation area of ​​a gate trench; Using the hard mask layer as a mask, etching the first epitaxial layer to form a gate trench; Performing ion implantation of a second conductivity type to form a channel region in the first epitaxial layer at the bottom region of the gate trench, and then removing the hard mask layer; The first epitaxial layer at the top of the channel region constitutes a drift region; Forming a gate structure in the gate trench, including: forming a gate dielectric layer on the inner surface of the gate trench and filling a gate conductive material layer; Performing ion implantation of a first conductive type heavy doping to form a drain region in a surface area of ​​the drift region located in a device unit region, wherein the drain region is self-aligned with a side surface of the gate trench; An interlayer film, a contact hole and a front metal layer are formed, and the front metal layer is patterned to form a drain metal and a gate metal; the top of the drain region is connected to the drain metal through the contact hole; the top of the gate conductive material layer is connected to the gate metal through the contact hole; The source region is composed of the semiconductor substrate, a back metal layer is formed on the back side of the source region and the back metal layer is used to form a source metal.

10. The method for manufacturing a power device according to claim 9, wherein: The power device comprises the device unit region and a gate lead-out region, and the contact hole on the top of the gate conductive material layer is located in the gate lead-out region.

11. The method for manufacturing a power device according to claim 10, wherein: The power device is a trench gate MOSFET or a SGT MOSFET; When the power device is the SGT MOSFET, the gate structure further includes a source conductive material layer.

12. The method for manufacturing a power device according to claim 11, wherein: When the power device is the SGTMOSFET, in the step of forming the gate structure in the gate trench, the top surface of the formed gate conductive material layer is lower than the top surface of the gate trench, and the gate conductive material layer is located in the bottom area of ​​the gate trench. After forming the gate conductive material layer, the method further includes: forming an inter-gate dielectric layer on the top surface of the gate conductive material layer in each of the gate trenches outside the gate lead-out region, wherein the top surface of the gate conductive material layer in the gate trenches in the gate lead-out region is exposed; forming a shielding dielectric layer, wherein the shielding dielectric layer is formed on the side surface of each of the gate trenches and located above the top surface of the gate conductive material layer; A source conductive material layer is filled in the gate trench; in each device unit, the source conductive material layer and the gate conductive material layer are formed in the same gate trench, the source conductive material layer is located on the top of the gate conductive material layer, an inter-gate dielectric layer is separated between the source conductive material layer and the gate conductive material layer, and a shielding dielectric layer is separated between the source conductive material layer and the gate trench; in the gate lead-out region, the source conductive material layer is in direct contact with the gate conductive material layer at the bottom and serves as a part of the gate conductive material layer, and the source conductive material layer and the gate trench are separated by the shielding dielectric layer.

13. The method for manufacturing a power device according to claim 12, wherein: The power device also includes a source lead-out region, in which the top of the source conductive material layer is connected to a source connection metal line composed of a front metal layer through a contact hole, and the source connection metal line is connected to the source metal on the back side.

14. The method for manufacturing a power device according to claim 13, wherein: In the source lead-out region, a first doped region heavily doped with a first conductive type is also formed on the surface of the drift region. The first doped region and the drain region are formed simultaneously using the same ion implantation process, and the top of the first doped region is connected to the source connection metal line through a contact hole.

15. The method for manufacturing a power device according to claim 9, wherein: The process conditions for ion implantation to form the channel region include: an implantation energy of 40keV to 120keV, an implantation dose of 1e12cm -2 ~1e13cm -2 .

16. The method for manufacturing a power device according to any one of claims 9 to 15, characterized in that: The power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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