Manufacturing method of shield gate trench type metal oxide semiconductor field effect transistor

Abstract

The invention provides a manufacturing method of a shield gate trench type metal oxide semiconductor field effect transistor. Before the oxide layer in the trench is removed, wet etching is carried out at a specific angle, so that the oxide layer in the terminal trench can be prevented from being corroded by a wet process; carrying out an ANNEAL process (annealing process) to enhance the compactness of the silicon oxide; and carrying out wet etching to remove an oxide layer on the surface of the chip. By adopting the wet process and the oxide layer treatment, the technical problem that the chip area is sacrificed due to over-corrosion is solved, the effects of omitting a dummy trench and saving the chip area are achieved, and the online process stability of a product can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor. Background Art

[0002] The shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) has the advantages of lower Miller capacitance, higher breakdown voltage, low resistance, faster switching speed, etc. The existing manufacturing method includes the following steps: depositing SiO2 and SiN as hard masks on the epitaxial layer, then forming trenches by photolithography and etching, growing a thick oxide film in the deep trench, filling polysilicon, forming a shielded gate, then filling the oxide film, wet etching the thick oxide film, forming an oxide layer between the shielded gate and the gate, then growing a gate oxide film, filling the gate polysilicon and etching to form a gate flush with the silicon surface, and then performing subsequent processes such as body region injection and well pushing, source injection and annealing, interlayer dielectric deposition, etc., to finally form a complete SGTMOSFET. Since the oxide layer between the shielded gate and the gate needs to be formed by wet etching of the oxide layer, wet etching will drill the trench of the terminal area along the bottom of the photoresist. When the wet etching is excessive, the chip will fail due to gate-source leakage current (IGSS) and off-state voltage (i.e., maximum allowable drain-source voltage BVDSS). To solve this problem, existing SGT MOSFETs often introduce dummy trenches during layout design, which sacrifices chip area. In addition, due to the problem of over-corrosion in wet etching, the instability of the online process is increased, and higher requirements are placed on the process stability of the product. Therefore, a low chip area SGT MOSFET that is not affected by over-corrosion is needed. Summary of the invention

[0003] In view of the deficiencies in the prior art, the present invention provides a method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor, which solves the technical problem of sacrificing chip area due to over-corrosion in the prior art.

[0004] According to an embodiment of the present invention, a method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor is provided, comprising the following steps: S1, providing a substrate, growing an epitaxial layer, defining a trench using a first mask, and growing a first oxide layer; S2, filling the trench with polysilicon, and etching the polysilicon to form a shielded gate; S3, depositing a second oxide layer above the polysilicon in the trench; S4, removing the oxide layer and dielectric layer on the surface of the chip; S5, defining an etching area using a second mask, and sinking the chip into a wet etching acid tank at a specific angle to reduce the thickness of the second oxide layer, wherein the specific angle is an angle formed by the chip surface and a liquid flow direction in the wet etching acid tank, and the specific angle is within a preset angle range; S6, growing a gate, then filling the gate with polysilicon, and etching the polysilicon; S7, generating the remaining layers required to form a complete shielded gate trench metal oxide semiconductor field effect transistor.

[0005] According to an embodiment of the present invention, chemical mechanical polishing is used to remove the oxide layer and the dielectric layer on the surface of the chip.

[0006] According to an embodiment of the present invention, a method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor further includes: performing annealing after chemical mechanical polishing.

[0007] According to an embodiment of the present invention, the oxide layer and the dielectric layer on the surface of the chip are silicon oxide-silicon nitride-silicon oxide.

[0008] According to an embodiment of the present invention, the etched region only includes a trench for forming a shielding gate.

[0009] According to an embodiment of the present invention, the preset angle range is 175-250 degrees.

[0010] According to an embodiment of the present invention, the thickness of the second oxide layer after being trimmed is 0.25-0.35 um.

[0011] The manufacturing method of the shielded gate trench metal oxide semiconductor field effect transistor also includes: after etching polysilicon, performing body region implantation and well driving, source electrode implantation and annealing.

[0012] According to an embodiment of the present invention, the remaining layers required for forming a complete shielded gate trench metal oxide semiconductor field effect transistor include a growth medium layer and a front metal layer.

[0013] The method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor also includes forming a passivation layer outside the dielectric layer.

[0014] The technical principle of the present invention is: before removing the oxide layer in the groove, wet etching is performed at a specific angle to prevent the wet process from corroding the oxide layer in the terminal groove; an ANNEAL process (annealing process) is performed to enhance the density of silicon oxide; and wet etching is then performed to remove the oxide layer on the surface of the chip.

[0015] Compared with the prior art, the present invention has the following beneficial effects: by adopting the above-mentioned wet process and oxide layer treatment, it solves the technical problem of sacrificing chip area due to over-corrosion, produces the effect of omitting the dummy trench and saving chip area, and can increase the online process stability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 4 is a schematic structural diagram of a conventional SGT MOSFET according to an embodiment of the present invention.

[0017] Figure 2 The present invention is a flowchart of a method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor according to an embodiment of the present invention.

[0018] Figure 3 This is a structural diagram of the SGT MOSFET according to an embodiment of the present invention before the oxide layer and the dielectric layer are removed.

[0019] Figure 4 This is a structural diagram of the SGT MOSFET of an embodiment of the present invention after the oxide layer and the dielectric layer are removed.

[0020] Figure 5 Schematic diagram of a non-angle-rotation wet process according to an embodiment of the present invention.

[0021] Figure 6 Schematic diagram of an angled wet process according to an embodiment of the present invention.

[0022] Figure 7 This is a structural diagram of the SGT MOSFET after etching the second oxide layer according to an embodiment of the present invention.

[0023] Figure 8 FIG. 4 is a structural diagram of an SGT MOSFET after gate growth according to an embodiment of the present invention.

[0024] Fig. 9 FIG. 4 is a final structural diagram of the SGT MOSFET according to an embodiment of the present invention.

[0025] In the accompanying drawings, the following reference numerals are included: 1, N-type substrate; 2, epitaxial layer; 3, first oxide layer; 4 / 5 / 6, hard mask; 7, shielding gate polysilicon; 8, second oxide layer; 9, P-type region; 10, N+ region; 11, dielectric layer; 12, metal layer and 13 / 14 / 15 passivation layer; 16, gate polysilicon; 17, dummy trench; 18, terminal trench. The same reference numerals indicate the same or similar parts and structures. DETAILED DESCRIPTION

[0026] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0027] The SGT MOSFET in the prior art is as follows Figure 1 As shown, it can be seen that two dummy trenches 17 are shown, resulting in an increase in the chip area.

[0028] In order to solve the above problems, Figure 2 As shown, according to an embodiment of the present invention, a method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor is proposed, comprising the following steps: S1, providing a substrate, growing an epitaxial layer, defining a trench using a first mask, and growing a first oxide layer; S2, filling polysilicon in the trench, and etching the polysilicon to form a shielded gate; S3, depositing a second oxide layer above the polysilicon in the trench; S4, removing the oxide layer and dielectric layer on the surface of the chip; S5, defining an etching area through a second mask, and sinking the chip into a wet etching acid tank at a specific angle to reduce the thickness of the second oxide layer, wherein the specific angle is an angle formed by the chip surface and the liquid flow direction in the wet etching acid tank, and the specific angle is within a preset angle range; S6, growing a gate, then filling the gate polysilicon, and etching the polysilicon; S7, generating the remaining layers required to form a complete shielded gate trench metal oxide semiconductor field effect transistor. Before removing the oxide layer in the trench, wet etching is performed by rotating the electrode at a specific angle. This prevents the wet process from corroding the oxide layer in the terminal trench, omitting the dummy trench, saving chip area, and increasing the online process stability of the product.

[0029] According to an embodiment of the present invention, chemical mechanical polishing (CMP) is used to remove the oxide layer and dielectric layer on the chip surface. In addition, the chip structure before this removal step is as follows: Figure 3As shown. It can be seen that the chip already includes 1. N-type substrate; 2. epitaxial layer; 3. first oxide layer; 4 / 5 / 6. hard mask; 7. shielding gate polysilicon; 8. second oxide layer. In addition, wet etching is used to remove dielectrics such as silicon nitride. The purpose of removing silicon oxide on the surface of the chip is to prevent acid from corroding silicon oxide and thus corroding silicon oxide in the terminal groove during subsequent wet etching, so that the subsequent photolithography photoresist directly contacts the SI interface, further reducing the lateral corrosion ability during wet etching. In addition, the chip structure obtained after this removal step is as follows Figure 4 As shown, it can be seen that the chip surface is flat and the hard mask 4 / 5 / 6 is no longer there.

[0030] In addition, in order to increase the lateral corrosion resistance of wet etching, a manufacturing method of a shielded gate trench metal oxide semiconductor field effect transistor further includes: performing annealing after chemical mechanical polishing. The annealing process enhances the compactness of silicon oxide and enhances its corrosion resistance.

[0031] Reference again Figure 3 According to an embodiment of the present invention, the oxide layer and the dielectric layer on the surface of the chip are silicon oxide-silicon nitride-silicon oxide.

[0032] In addition, in order to protect the structure except the shielding gate from etching, such as Figure 5 As shown, according to an embodiment of the present invention, the etching area only includes the trench for forming the shielding gate. It can be seen that the yellow area on the chip ensures that only the shielding gate area is etched.

[0033] In addition, in order to ensure the effect of anti-lateral corrosion, according to an embodiment of the present invention, the preset angle range is 175-250 degrees. Among them, the acid flow direction is taken as the positive direction, and any angle is the angle formed by the chip surface and the acid flow direction (therefore, any angle between 0-360 degrees can be formed). Figure 5 , shows a wet process without angle rotation, where the chip surface is parallel to the acid flow direction, and the angle formed is 0 degrees. Figure 6 In the process, the chip surface forms an angle with the acid flow direction, which is within a preset angle range.

[0034] According to an embodiment of the present invention, the thickness of the second oxide layer after reduction is 0.25-0.35 um. Figure 7 As shown, it can be seen that a second oxide layer of desired thickness has been formed.

[0035] In addition, according to an embodiment of the present invention, the manufacturing method of the shielded gate trench metal oxide semiconductor field effect transistor further includes: after etching polysilicon, performing body region implantation and well driving, source electrode implantation and annealing. Figure 8As shown, the chip structure includes: 9, a P-type region and 10, an N+ region.

[0036] According to an embodiment of the present invention, the remaining layers required to form a complete shielded gate trench metal oxide semiconductor field effect transistor include a growth medium layer and a front metal layer. Fig. 9 As shown, the chip structure includes: 11, a dielectric layer; 12, a metal layer.

[0037] Reference again Figure 8 The manufacturing method of the shielded gate trench metal oxide semiconductor field effect transistor further includes forming a passivation layer 13 / 14 / 15 outside the dielectric layer. In addition, a gate polysilicon 16 is also shown.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor, characterized in that: The following steps are involved: S1, providing a substrate, growing an epitaxial layer, defining a groove using a first mask, and growing a first oxide layer; S2, filling the trench with polysilicon and etching the polysilicon to form a shielding gate; S3, depositing a second oxide layer on the polysilicon in the trench; S4, removing the oxide layer and dielectric layer on the surface of the chip; S5, defining an etching area by a second mask, and sinking the chip into a wet etching acid tank at a specific angle to reduce the thickness of the second oxide layer, wherein the specific angle is an angle formed by the chip surface and a liquid flow direction in the wet etching acid tank, and the specific angle is within a preset angle range; S6, growing a gate, then filling the gate polysilicon, and etching the polysilicon; S7. Generate the remaining layers required to form a complete shielded gate trench metal oxide semiconductor field effect transistor.

2. The method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor according to claim 1, characterized in that: Chemical mechanical polishing is used to remove the oxide layer and dielectric layer on the chip surface.

3. The method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor according to claim 2, characterized in that: Also includes: Annealing is performed after chemical mechanical polishing.

4. The method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The oxide layer and dielectric layer on the chip surface are silicon oxide-silicon nitride-silicon oxide.

5. The method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The etched region includes only the trench for forming the shielding gate.

6. The method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The preset angle range is 175-250 degrees.

7. The method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The thickness of the second oxide layer after cutting is 0.25-0.35um.

8. The method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor according to claim 1, characterized in that: Also includes: After etching the polysilicon, body region implantation and well driving, source implantation and annealing are performed.

9. A method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor according to any one of claims 1 to 8, characterized in that: The remaining layers required to form a complete shielded gate trench metal oxide semiconductor field effect transistor include a growth dielectric layer and a front metal.

10. The method for manufacturing a shielded gate trench metal oxide semiconductor field effect transistor according to claim 9, characterized in that: The method further includes forming a passivation layer outside the dielectric layer.

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