Superjunction semiconductor devices

Abstract

The present application relates to a superjunction semiconductor device, and relates to the field of semiconductor technology, comprising: a semiconductor material layer, comprising an upper surface and a lower surface opposite to each other; a superjunction structure, located in the semiconductor material layer, comprising a plurality of first conductive type columns and second conductive type columns arranged alternately; a first conductive type well region, located in the semiconductor material layer and located at the top of the first conductive type column, the first conductive type well region comprising a first type well region and a second type well region; a gate, located on the upper surface; a first conductive plug, conductively connected to the first type well region through the gate; a second conductive plug, located on the gate, conductively connected to the gate; the second type well region is covered by the gate, and the second type well region is insulated and isolated from the first conductive plug and the second conductive plug; the second type well region extends from the core region to the terminal region, and the second type well region is separately arranged from the first type well region in the core region and in the terminal region. Thus, the device's anti-electromagnetic interference capability is enhanced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a superjunction semiconductor device. Background Art

[0002] Compared with the traditional MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the superjunction MOSFET introduces alternating N-pillars and P-pillars in the drift region, which can significantly increase the doping concentration of the drift region without reducing the breakdown voltage. Unlike the existing VDMOS (Vertical Double-Diffused Metal Oxide Semiconductor) devices, the specific on-resistance of the superjunction MOSFET can be further reduced by continuously reducing the distance between the P-pillars. Under the same on-resistance, the chip area of ​​the superjunction MOSFET can be less than one-sixth of that of the VDMOS, and its capacitance is also sharply reduced.

[0003] During the switching process of the super-junction MOSFET, since the P-type and N-type columns in the super-junction structure only require a relatively low Vds (Voltage of drain-source) to be depleted, the Cgd (Capacitance of gate-drain) of the super-junction MOSFET drops sharply at a drain-source voltage of tens of volts, and then maintains a relatively small value, which can easily cause oscillations in the gate voltage and drain-source voltage. This oscillation affects the stability of the system and the EMI (Electromagnetic Interference) characteristics, resulting in more serious electromagnetic interference problems, which limits the large-scale use of super-junction MOSFET devices. In addition, as the device becomes smaller, Cgd will also become smaller as the device size decreases, exacerbating the electromagnetic interference problem. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a super junction semiconductor device to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a superjunction semiconductor device, including:

[0006] a semiconductor material layer including an upper surface and a lower surface opposite to each other;

[0007] A super junction structure, located in the semiconductor material layer, the super junction structure comprising a plurality of first conductivity type columns and second conductivity type columns arranged alternately;

[0008] A first conductive type well region, located in the semiconductor material layer and located at the top of the first conductive type column, the first conductive type well region comprising a first type well region and a second type well region;

[0009] a gate, located on the upper surface of the semiconductor material layer;

[0010] A first conductive plug, passing through the gate and conductively connected to the first type well region;

[0011] A second conductive plug, located on the gate and conductively connected to the gate;

[0012] The second-type well region is covered by the gate, and the second-type well region is insulated and isolated from the first conductive plug and the second conductive plug; the second-type well region extends from the core region to the terminal region of the superjunction semiconductor device, and the second-type well region is independently arranged from the first-type well region in the core region and in the terminal region.

[0013] In conjunction with the first aspect of the present application, in an optional implementation manner, the method further includes:

[0014] a dielectric layer, located between the gate and the upper surface of the semiconductor material layer;

[0015] The gate includes a first gate portion located directly above the first type of well region and a second gate portion located directly above the second type of well region, and the average thickness of the portion of the dielectric layer located between the second gate portion and the second type of well region is greater than the average thickness of the portion located between the first gate portion and the first type of well region.

[0016] In combination with the first aspect of the present application, in an optional embodiment, the dielectric layer includes a gate dielectric layer and an isolation dielectric layer, the gate dielectric layer is located between the first type of well region and the first gate portion and between the second type of well region and the second gate portion, and the isolation dielectric layer is located between the second type of well region and the gate dielectric layer.

[0017] In combination with the first aspect of the present application, in an optional implementation, the gate further includes a first gate connection portion located in the terminal region, and the first gate portion and the second gate portion are conductively connected in the terminal region through the first gate connection portion.

[0018] In combination with the first aspect of the present application, in an optional implementation manner, the gate further includes a second gate connection portion located in the core region, and the second gate connection portion is located directly above the second conductive type column;

[0019] The first gate portion includes a first sub-portion and a second sub-portion separated by the first conductive plug in the core region, and the first sub-portion and the second sub-portion are conductively connected in the terminal region through the first gate connecting portion;

[0020] For two first gate portions adjacent to the same second gate portion and respectively located on both sides of the second gate portion, the second sub-portion of one first gate portion is connected to the second gate portion via a second gate connecting portion, and the first sub-portion of the other first gate portion is connected to the second gate portion via another second gate connecting portion.

[0021] In combination with the first aspect of the present application, in an optional embodiment, the gate includes a first gate portion located directly above the first type of well region and a second gate portion located directly above the second type of well region, and the first gate portion is insulated and isolated from the second gate portion.

[0022] In conjunction with the first aspect of the present application, in an optional implementation manner, the gate further includes a first gate connection portion located in the terminal region;

[0023] The first gate portion includes a first sub-portion and a second sub-portion separated by the first conductive plug in the core region, and the first sub-portion and the second sub-portion are conductively connected in the terminal region through the first gate connecting portion;

[0024] For two first gate portions adjacent to the same second gate portion and respectively located on both sides of the second gate portion, a first gap dielectric layer exists between the second sub-portion of one first gate portion and the second gate portion, another first gap dielectric layer exists between the first sub-portion of the other first gate portion and the second gate portion, and each of the first gap dielectric layers is respectively located directly above a different second conductive type column;

[0025] The second sub-portion of one of the first gate portions is conductively connected to the first sub-portion of the other first gate portion in the terminal region through the first gate connecting portion.

[0026] In conjunction with the first aspect of the present application, in an optional implementation manner, the method further includes:

[0027] A source region, located in the first type of well region;

[0028] The source region is not disposed in the second-type well region.

[0029] In combination with the first aspect of the present application, in an optional implementation manner, the method further includes: a first through-groove passing through the gate, the first conductive plug being located in the first through-groove, and the first through-groove being further filled with a second gap dielectric layer;

[0030] In a plane parallel to the upper surface, the first conductive type columns and the second conductive type columns are alternately arranged along a first direction, and the first through grooves extend along a second direction, and the second direction is perpendicular to the first direction; along the second direction, a portion of the first type of well region is in contact with the first conductive plug, and a portion is in contact with the second gap dielectric layer.

[0031] In combination with the first aspect of the present application, in an optional implementation manner, the first conductive plug and the second gap dielectric layer are distributed in the same position in two adjacent first through grooves; or,

[0032] The distribution positions of the first conductive plug and the second gap dielectric layer in two adjacent first through grooves are opposite to each other.

[0033] The superjunction semiconductor device provided by the embodiment of the present application includes: a semiconductor material layer, including an upper surface and a lower surface opposite to each other; a superjunction structure, located in the semiconductor material layer, the superjunction structure including a plurality of first conductive type columns and second conductive type columns arranged alternately; a first conductive type well region, located in the semiconductor material layer and at the top of the first conductive type column, the first conductive type well region including a first type well region and a second type well region; a gate, located on the upper surface of the semiconductor material layer; a first conductive plug, conductively connected to the first type well region through the gate; a second conductive plug, located on the gate and conductively connected to the gate; the second type well region is covered by the gate, and the second type well region is insulated and isolated from the first conductive plug and the second conductive plug; the second type well region extends from the core region to the terminal region of the superjunction semiconductor device, and the second type well region is separately arranged from the first type well region in the core region and in the terminal region. In this way, the second type of well region is covered by the gate and is insulated and isolated from the first conductive plug and the second conductive plug, and the second type of well region is not connected to the potential; and in the core area and the terminal area of ​​the device, the second type of well region is separately arranged from the first type of well region to avoid the second type of well region being affected by the first type of well region to which voltage is applied, so that the second type of well region is in a completely floating state. Then, when the device is working, no voltage is applied to the first conductive type column corresponding to the second type of well region below, and no depletion will occur with the adjacent second conductive type column. Only the first conductive type column corresponding to the first type of well region is depleted toward the adjacent second conductive type column due to the applied voltage, so that only unidirectional depletion occurs between the first conductive type column corresponding to the second type of well region below and the first conductive type column corresponding to the first type of well region, which greatly prolongs the time for the second conductive type column between the two to be completely depleted, thereby increasing Cgd, and at the same time slowing down the trend of Cgd decrease, reducing voltage oscillation, and suppressing electromagnetic interference.

[0034] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0036] Figure 1 A schematic cross-sectional structure diagram of a superjunction semiconductor device provided for related technologies;

[0037] Figure 2 A schematic cross-sectional structure diagram of a superjunction semiconductor device provided in an embodiment of the present application;

[0038] Figure 3A layout of a portion of the structural layers in the superjunction semiconductor device provided in an embodiment of the present application;

[0039] Figure 4 A layout of another part of the structural layer in the superjunction semiconductor device provided in an embodiment of the present application;

[0040] Figure 5 A layout of another part of the structural layer in the superjunction semiconductor device provided in the comparative example;

[0041] Figure 6 A comparison diagram of Cgd-Vds curves of the superjunction semiconductor device provided in the embodiment of the present application and the superjunction semiconductor device provided in the comparative example;

[0042] Figure 7 A schematic cross-sectional structure diagram of a superjunction semiconductor device provided as an optional specific implementation manner;

[0043] Figure 8 For Figure 7 A layout of a portion of the structural layers in the corresponding superjunction semiconductor device;

[0044] Fig. 9 A partial enlarged view of the cross-sectional structure of a superjunction semiconductor device provided as an optional specific implementation manner;

[0045] Fig.10 A schematic cross-sectional structure diagram of a superjunction semiconductor device provided as an optional specific implementation manner;

[0046] Fig.11 A schematic cross-sectional structure diagram of a superjunction semiconductor device provided for another optional specific implementation manner;

[0047] Fig.12 For Fig.11 A layout of a portion of the structural layers in the corresponding superjunction semiconductor device;

[0048] Fig.13 A layout of a portion of a structural layer in a superjunction semiconductor device of an optional specific example;

[0049] Fig.14 A layout of a portion of a structural layer in a superjunction semiconductor device of another optional specific example;

[0050] Fig.15 A layout of a portion of a structural layer in a superjunction semiconductor device of another optional specific example;

[0051] Fig.16 The present invention is a layout of a portion of a structural layer in a superjunction semiconductor device according to yet another optional specific example.

[0052] Description of reference numerals:

[0053] 100, semiconductor material layer; 101, upper surface; 102, lower surface; 110, first conductive type column; 120, second conductive type column; 130, first conductive type well region; 131, first type well region; 132, second type well region; 140, source region; 200, gate; 210, first gate portion; 211, first sub-portion; 212, second sub-portion; 220, second gate portion; 230, first gate connection portion; 240, second gate connection portion; 310, first conductive plug; 320, second conductive plug; 400, dielectric layer; 410, isolation dielectric layer; 420, gate dielectric layer; 430, first gap dielectric layer; 440, second gap dielectric layer; 510, first conductive layer; 600, first through groove; 10a, core region; 20a, terminal region. DETAILED DESCRIPTION

[0054] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0055] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0056] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0057] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0058] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0059] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0061] Figure 1 A cross-sectional structural diagram of a superjunction semiconductor device provided for related technologies. As shown in the figure, the semiconductor material layer 100 includes a plurality of first conductive type columns 110 and second conductive type columns 120 arranged alternately; a first conductive type well region 130 located in the semiconductor material layer 100 and at the top of the first conductive type columns 110; a source region 140 located in the first conductive type well region 130; a gate 200 located on the upper surface 101 of the semiconductor material layer 100; and a first conductive plug 310 passing through the gate 200 and conductively connected to the source region 140.

[0062] When the device starts to work, the channel is opened, and the first conductive plug 310 is energized. At this time, the source region 140 applies zero potential, and the electrons pass through the channel in the first conductive type well region 130 from the source region 140 and enter the second conductive type column 120 until they reach the drain region (not shown in the figure) located on the lower surface 102 side of the semiconductor material layer 100. The first conductive type column 110 and the second conductive type column 120 form a PN junction. In this process, a depletion region appears at the interface between the first conductive type column 110 and the second conductive type column 120, and as the applied voltage continues to increase, the range of the depletion region gradually increases. Since the depletion region is formed on both sides of the second conductive type column 120, the depletion lines of the depletion regions on both sides gradually approach and merge; after the lateral depletion is completed, the depletion region will further diffuse to the bottom of the first conductive type column 110, and finally the depletion line will form a straight line parallel to the lower surface 102 near the lower surface 102 of the semiconductor material layer 100.

[0063] It can be understood that the Cgd of the device is positively correlated with the size of the depletion region. In this device, depletion occurs in the second conductive type column 120. During the switching process, as the drain voltage increases, the depletion region gradually expands from the source downward, and the Cgd of the device gradually decreases; when the depletion lines on both sides merge, the second conductive type column 120 is completely depleted, Cgd mutates, and the device drain voltage mutates in a short time, forming a voltage spike, causing voltage oscillation, and causing verified EMI noise.

[0064] In view of this, the present application embodiment provides a super junction semiconductor device, please refer to Figures 2 to 4The super junction semiconductor device comprises: a semiconductor material layer 100, comprising an upper surface 101 and a lower surface 102 opposite to each other; a super junction structure, located in the semiconductor material layer 100, the super junction structure comprising a plurality of first conductive type columns 110 and second conductive type columns 120 arranged alternately; a first conductive type well region 130, located in the semiconductor material layer 100 and at the top of the first conductive type columns 110, the first conductive type well region 130 comprising a first type well region 131 and a second type well region 132; a gate 200, located on the upper surface 101 of the semiconductor material layer 100; 1; a first conductive plug 310 passes through the gate 200 and is conductively connected to the first type well region 131; a second conductive plug 320 is located on the gate 200 and is conductively connected to the gate 200; the second type well region 132 is covered by the gate 200, and the second type well region 132 is insulated and isolated from the first conductive plug 310 and the second conductive plug 320; the second type well region 132 extends from the core region 10a to the terminal region 20a of the super junction semiconductor device, and the second type well region 132 is separately arranged from the first type well region 131 in the core region 10a and in the terminal region 20a.

[0065] In the embodiment of the present application, the second-type well region 132 is covered by the gate 200 and insulated and isolated from the first conductive plug 310 and the second conductive plug 320, and the second-type well region 132 is not connected to the potential; and in the core area 10a and the terminal area 20a of the device, the second-type well region 132 is separately arranged from the first-type well region 131, so as to avoid the second-type well region 132 being affected by the first-type well region 131 to which the voltage is applied, so that the second-type well region 132 is in a completely floating state, and then when the device is working, no voltage is applied to the first conductive type column 110 corresponding to the second-type well region 132, and no Depletion will occur with the adjacent second conductive type column 120, and only the first conductive type column 110 corresponding to the first type well region 131 will be depleted toward the adjacent second conductive type column 120 due to the applied voltage, so that only unidirectional depletion occurs between the first conductive type column 110 corresponding to the second type well region 132 below and the first conductive type column 110 corresponding to the first type well region 131, which greatly prolongs the time for the second conductive type column 120 to be completely depleted between the two, thereby increasing Cgd and slowing down the downward trend of Cgd, reducing voltage oscillation and suppressing electromagnetic interference.

[0066] The superjunction semiconductor device includes a core region 10a and a terminal region 20a. The core region 10a is also called a cell region or a device unit region. A plurality of parallel device units (cells) are formed in the core region 10a. The terminal region 20a surrounds the outer periphery of the core region 10a. Superjunction structures are formed in both the core region 10a and the terminal region 20a. Figure 4As shown, the first conductive type column 110 and the first conductive type well region 130 extend from the core region 10a to the terminal region 20a. In this embodiment, the first type well region 131 is conductively connected to the first conductive plug 310, and the cell corresponding to the first type well region 131 can be understood as a real cell. When the device is working, the current passes through the real cell; while the second type well region 132 covers the gate 200 and is insulated from the first conductive plug 310, and no potential is applied to it. In addition, in the core region 10a and the terminal region 20a, the second type well region 132 is separately arranged from the first type well region 131, and the second type well region 132 becomes a floating well region. The cell corresponding to the second type well region 132 can be understood as a dummy cell. When the device is working, the current does not pass through the dummy cell.

[0067] The "floating well region" here refers to a well region that is electrically isolated from the surrounding area and does not have a fixed potential. In the embodiment of the present application, the second-type well region 132 is insulated from the conductive plug, no voltage is applied to it, and the second-type well region 132 is not connected to the first conductive plug 310 on the layout, so that it will not be affected when a voltage is applied to the first-type well region 131. In this way, the second-type well region 132 is in a completely floating state. It should be further emphasized that, with reference to Figure 4 In the embodiment of the present application, the second-type well region 132 is separately arranged from the first-type well region 131 in the core region 10a and the terminal region 20a. The second-type well region 132 is not connected to the first-type well region 131 at any position, so that they are completely independent on the layout, thereby avoiding the second-type well region 132 being affected when a voltage is applied to the first-type well region 131 through the first conductive plug 310.

[0068] Therefore, it is not difficult to understand that in the device, only the real unit is applied with voltage and participates in the process of the device conducting current, while the virtual unit is not applied with voltage, and the second type well region 132 is in a completely floating state, and the virtual unit will not be affected by the real unit and conduct current. Since depletion usually occurs at the junction of the PN junction to which the voltage is applied, expanding from the P-type doping area to the N-type doping area, then only the first conductive type column 110 in the real unit can produce depletion with the adjacent second conductive type column 120, and the first conductive type column 110 in the virtual unit and the adjacent second conductive type column 120 cannot produce depletion. Therefore, in the device, depletion only occurs from one side of the second conductive type column 120. Compared with the bidirectional depletion in the related art, the unidirectional depletion in this embodiment takes longer time, so that Cgd will take longer time to mutate, the trend of Cgd decreases, and the mutation of Cgd will occur when the voltage is higher, thereby increasing the Cgd of the device under high voltage to avoid voltage overshoot.

[0069] Figure 5 FIG. 1 shows a layout diagram of a superjunction semiconductor device provided in a comparative example. It should be noted that the cross-sectional structure diagram of the superjunction semiconductor device provided in the comparative example is similar to FIG. Figure 2 Specifically, in the comparative example, the second type well region 132 of the superjunction semiconductor is covered by the gate 200, and the second type well region 132 is insulated and isolated from the first conductive plug 310 and the second conductive plug 320, thereby forming a virtual unit. Figure 5 As shown, in the terminal region 20a of the device, the first type well region 131 and the second type well region 132 are connected, rather than insulated and isolated. Then, the first conductive plug 310 and the second type well region 132 can be conductively connected through the first type well region 131. When the device is working, current may also pass through the virtual unit, and both sides of the second conductive type column 120 will begin to be depleted, affecting the improvement effect of Cgd. Please refer to Figure 6 , under the same voltage value, the Cgd of the superjunction semiconductor device provided by the embodiment of the present application is greater than the Cgd of the superjunction semiconductor device provided by the comparative example. It can be seen that the embodiment of the present application sets the second-type well region 132 to be separated from the first-type well region 131 in both the core region 10a and the terminal region 20a, so that the second-type well region 132 is in a completely floating state, which can effectively improve the Cgd of the device and slow down the downward trend of Cgd.

[0070] In this embodiment, the semiconductor material layer 100 may be a semiconductor layer doped with N-type ions or P-type ions formed on a substrate (not shown in the figure) well known to those skilled in the art, such as a silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate, etc. The semiconductor material layer 100 may be a structure of stacking multiple epitaxial layers. As a specific optional implementation, the semiconductor material layer 100 is doped with N-type ions, and the semiconductor material layer 100 is an N-type doped layer.

[0071] Please refer to Figure 2 and Figure 4In the semiconductor material layer 100, in a plane parallel to the upper surface 101, the first conductive type columns 110 and the second conductive type columns 120 are alternately arranged along the first direction; the first conductive type columns 110 and the second conductive type columns 120 extend from the core area 10a to the terminal area 20a along the second direction; the first conductive type columns 110 and the second conductive type columns 120 extend along the third direction. In this embodiment, the second direction is the direction from the core area 10a to the terminal area 20a, the third direction is the thickness direction of the semiconductor material layer 100, and any two of the first direction, the second direction and the third direction are perpendicular to each other. It can be understood that, in actual preparation, the first conductive type ion implantation can be performed from the upper surface 101 side of the semiconductor material layer 100 to form the first conductive type column 110 in the semiconductor material layer 100 having the second conductive type. At this time, the second conductive type column 120 can be understood as the portion of the semiconductor material layer 100 between adjacent first conductive type columns 110 that is not further doped; or, the second conductive type ion implantation can be performed from the upper surface 101 side of the semiconductor material layer 100 to form the second conductive type column 120 in the semiconductor material layer 100 having the first conductive type. At this time, the first conductive type column 110 can be understood as the portion of the semiconductor material layer 100 between adjacent second conductive type columns 120 that is not further doped. In this embodiment, the semiconductor material layer 100 has the second conductive type.

[0072] In this embodiment, the first conductivity type is specifically P type, and the second conductivity type is specifically N type. The first conductivity type column 110 can be called a "P type column", the second conductivity type column 120 can be called an "N type column", and the first conductivity type well region 130 can be called a "P well".

[0073] Optionally, a second type well region 132 is provided between adjacent first type well regions 131. It can be understood that a plurality of units are usually provided in the device, and a second type well region 132 is provided between adjacent first type well regions 131, which can be understood as providing a virtual unit between adjacent real units, so that the depletion of the entire device is unidirectional depletion, which more effectively increases the depletion time, slows down the downward trend of Cgd, improves Cgd, and is conducive to uniform current and ensures device performance.

[0074] In this embodiment, the top end refers to an end facing the upper surface 101 of the semiconductor material layer 100, and the bottom end refers to an end facing the lower surface 102 of the semiconductor material layer 100. Therefore, the first conductive type well region 130 is located at the top of the first conductive type column 110, which means that the first conductive type well region 130 is located at the end of the first conductive type column 110 facing the upper surface 101 of the semiconductor material layer 100. In actual preparation, the first conductive type ion implantation can be performed from the upper surface 101 side of the semiconductor material layer 100 to form the first conductive type well region 130 at the top of the first conductive type column 110; the width of the first conductive type well region 130 is greater than the width of the first conductive type column 110; the doping concentration of the first conductive type well region 130 is greater than the doping concentration of the first conductive type column 110.

[0075] Please refer to Figure 4 , the first type well region 131 and the second type well region 132 both extend from the core region 10a to the terminal region 20a, the first type well region 131 further extends in the terminal region 20a in the direction of the second type well region 132, the second type well region 132 is separately arranged with the first type well region 131 in the core region 10a and in the terminal region 20a, from the layout point of view, the second type well region 132 and the first type well region 131 are not connected at any position, and the layout is completely independent. In some embodiments, the device may further include a second conductive type doping region 133, and the first type well region 131 and the second type well region 132 are isolated by the second conductive type doping region 133. Thus, it can be ensured that the first type well region 131 and the second type well region 132 are independent of each other. Specifically, the second conductive type doping region 133 is located at the top of the second conductive type column 120. The second conductive type doping region 133 and the second conductive type column 120 can be the part of the semiconductor material layer 100 that is not further doped.

[0076] Please refer to Figure 2 , the device may further include: a source region 140, located in the first type well region 131; the source region 140 is not provided in the second type well region 132. Therefore, when the device is working, an effective channel cannot be formed in the second type well region 132, and the virtual unit does not participate in the process of the device conducting current, which is conducive to extending the depletion time. The source region 140 has a second conductivity type. In actual preparation, the second conductivity type ion implantation can be performed from the upper surface 101 side of the semiconductor material layer 100 to form the source region 140 in the first type well region 131. At this time, there is no need to perform ion implantation in the second type well region 132.

[0077] Please refer to Figure 2 and Figure 3The device may further include: a first conductive layer 510, the first conductive layer 510 is located above the gate 200, directly contacts the first conductive plug 310, and is conductively connected to the first type well region 131 through the first conductive plug 310; a second conductive layer (not shown in the figure), located above the gate 200, directly contacts the second conductive plug 320, and is conductively connected to the gate 200 through the second conductive plug 320; the first conductive layer 510 and the second conductive layer are insulated and isolated; the second type well region 132 is insulated and isolated from both the first conductive layer 510 and the second conductive layer. Since the source region 140 is formed in the first-type well region 131, the first conductive plug 310 is conductively connected to the source region 140, and the first conductive layer 510 can be called a "source electrode" or an "emitter electrode"; the second conductive plug 320 passes through the dielectric layer above the gate 200 and is conductively connected to the gate 200, and the second conductive layer can be called a "gate electrode" or a "collector electrode". Therefore, the first conductive layer 510 and the second conductive layer are electrodes of different polarities of the device, and the two need to be insulated and isolated to avoid short circuit and affect the performance of the device.

[0078] As an optional specific implementation, please refer to Figure 7 and Figure 8 The device further includes: a dielectric layer 400, located between the gate 200 and the upper surface 101 of the semiconductor material layer 100; the gate 200 includes a first gate portion 210 located directly above the first type well region 131 and a second gate portion 220 located directly above the second type well region 132, and the average thickness of the portion of the dielectric layer 400 located between the second gate portion 220 and the second type well region 132 is greater than the average thickness of the portion located between the first gate portion 210 and the first type well region 131. It can be understood that, as Figure 8 As shown, in the device, the second conductive plug 320 is conductively connected to the gate 200. After the second conductive plug 320 is energized, the virtual unit may be energized under the action of the gate voltage, thereby forming a depletion region. Therefore, by thickening the average thickness of the dielectric layer 400 between the second gate portion 220 and the second type of well region 132, the isolation effect of the dielectric layer 400 can be enhanced, the influence of the gate 200 on the virtual unit below can be reduced, and the second type of well region 132 can be ensured to be in a floating state.

[0079] Optionally, refer to Fig. 9The dielectric layer 400 includes a gate dielectric layer 420 and an isolation dielectric layer 410. The gate dielectric layer 420 is located between the first type well region 131 and the first gate portion 210 and between the second type well region 132 and the second gate portion 220. The isolation dielectric layer 410 is located between the second type well region 132 and the gate dielectric layer 420. Therefore, by arranging the isolation dielectric layer 410 above the second type well region 132, the average thickness of the dielectric layer located between the second gate portion 220 and the second type well region 132 is greater than the average thickness of the dielectric layer located between the first gate portion 210 and the first type well region 131, thereby reducing the influence of the gate on the underlying virtual unit. It can be understood that since the gate dielectric layer 420 needs to be formed above both the first type well region 131 and the second type well region 132, during actual preparation, an isolation dielectric layer 410 can be first formed in the area that needs to be thickened, and then the gate dielectric layer 420 can be formed uniformly. Thus, in the area with thicker thickness, the isolation dielectric layer 410 is located below the gate dielectric layer 420 and the gate 200, and the gate dielectric layer 420 can be formed conformally on the isolation dielectric layer 410. The specific process conditions can be the same as those of conventional processes, thereby reducing the process difficulty.

[0080] The material of the isolation dielectric layer 410 may be any suitable dielectric material, such as silicon oxide, nitride and oxynitride. In this embodiment, the material of the isolation dielectric layer 410 is specifically oxide. The process of forming the isolation dielectric layer 410 may include a field oxygen process, a LOCOS (Local Oxidation of Silicon) process or a deposition process. It is understandable that Figure 7 Only part of the area in the device is schematically shown. During actual preparation, dielectric layers also need to be prepared in other areas of the device. Therefore, when preparing the dielectric layers in other areas, part of the dielectric layer located on the second type well region 132 can be retained to form an isolation dielectric layer 410 in the same process, saving process steps.

[0081] Please refer to Fig. 9 and Fig.10 The cross-sectional shape of the isolation dielectric layer 410 may include a triangle or a trapezoid. It is understandable that when the cross-sectional shape of the isolation dielectric layer 410 is a trapezoid, the thickness of the isolation dielectric layer 410 is more uniform at all locations, and the isolation effect is better. It is understandable that in actual preparation, different processes may be used to obtain isolation dielectric layers 410 with different cross-sectional shapes.

[0082] The material of the gate dielectric layer 420 may be any suitable dielectric material, such as silicon oxide, nitride and oxynitride, etc. In this embodiment, the material of the gate dielectric layer 420 may specifically be oxide. The process of forming the gate dielectric layer 420 may include a deposition process.

[0083] Optionally, refer to Figure 8 The gate further includes a first gate connection portion 230 located in the terminal region 20 a , and the first gate portion 210 and the second gate portion 220 are conductively connected in the terminal region 20 a through the first gate connection portion 230 .

[0084] Specifically, please refer to Figure 7 The gate also includes a second gate connection portion 240 located in the core area 10a, and the second gate connection portion 240 is located directly above the second conductive type column 120; the first gate portion 210 includes a first sub-portion 211 and a second sub-portion 212 separated by a first conductive plug 310 in the core area 10a, and the first sub-portion 211 and the second sub-portion 212 are conductively connected in the terminal area 20a through a first gate connection portion 230; for two first gate portions 210 adjacent to the same second gate portion 220 and respectively located on both sides of the second gate portion 220, the second sub-portion 212 of one first gate portion 210 is connected to the second gate portion 220 through a second gate connection portion 240, and the first sub-portion 211 of the other first gate portion 210 is connected to the second gate portion 220 through another second gate connection portion 240. Two source regions 140 are formed in the first type well region 131, and the two source regions 140 are arranged at intervals along the first direction. The first sub-portion 211 and the second sub-portion 212 are respectively located on the well region between the two source regions 140 and the second conductive type column 120. After the device is turned on, a channel will be formed in the first conductive type well region 130 below the first sub-portion 211 and the second sub-portion 212. Therefore, the first sub-portion 211 and the second sub-portion 212 are conductively connected in the terminal region 20a through the first gate connection portion 230. The second conductive plug 320 can be conductively connected to the first sub-portion 211 and the second sub-portion 212 through the first gate connection portion 230 to provide them with a gate voltage, so that the channel can be formed smoothly, thereby ensuring the functional realization of the real unit.

[0085] Furthermore, the second sub-portion 212 of one first gate portion 210 is connected to the second gate portion 220 via a second gate connecting portion 240, and the first sub-portion 211 of another first gate portion 210 is connected to the second gate portion 220 via another second gate connecting portion 240. Figure 8 From the layout, the first sub-section 211, the second sub-section 212, the second gate connection section 240 and the second gate section 220 form a whole structure. In the core area 10a, the first conductive plugs 310 are separated by gates. Therefore, in actual preparation, a gate material layer covering the core area 10a and the terminal area 20a can be directly formed. When the first conductive plug 310 is subsequently prepared, the corresponding part of the gate material layer is etched to form the gate 200, which is consistent with the conventional process of preparing the gate and is similar to the gate layout of the common super junction MOSFET. Figure 1 Under the effect of the isolation dielectric layer 410, the influence of the gate on the virtual unit below is reduced. On this basis, the above-mentioned setting of the gate can reduce the process difficulty, and there is no need to prepare additional structures such as masks, which saves process costs and ensures device performance.

[0086] As another optional specific implementation, please refer to Fig.11 The gate includes a first gate portion 210 located directly above the first type well region 131 and a second gate portion 220 located directly above the second type well region 132, and the first gate portion 210 is insulated and isolated from the second gate portion 220. Thus, the first gate portion 210 above the virtual unit is insulated and isolated from the second gate portion 220 above the real unit, so that when a voltage is applied to the second gate portion 220, the first gate portion 210 is not affected, thereby reducing the influence of the gate on the virtual unit.

[0087] Specifically, please refer to Fig.11 and Fig.12 , the gate also includes a first gate connection portion 230 located in the terminal area 20a; the first gate portion 210 includes a first sub-portion 211 and a second sub-portion 212 separated by a first conductive plug 310 in the core area 10a, and the first sub-portion 211 and the second sub-portion 212 are conductively connected in the terminal area 20a through the first gate connection portion 230; for two first gate portions 210 adjacent to the same second gate portion 220 and respectively located on both sides of the second gate portion 220, a first gap dielectric layer 430 exists between the second sub-portion 212 of one first gate portion 210 and the second gate portion 220, and another first gap dielectric layer 430 exists between the first sub-portion 211 of the other first gate portion 210 and the second gate portion 220, and each first gap dielectric layer 430 is respectively located directly above a different second conductive type column 120; the second sub-portion 212 of one first gate portion 210 is conductively connected to the first sub-portion 211 of the other first gate portion 210 in the terminal area 20a through the first gate connection portion 230. Thus, the first gate portion 210 and the second gate portion 220 are insulated and isolated by the first gap dielectric layer 430 .

[0088] Two source regions 140 are formed in the first type well region 131, and the first sub-section 211 and the second sub-section 212 are respectively located on the well region between the two source regions 140 and the second conductive type column 120. After the device is turned on, a channel will be formed in the first conductive type well region 130 below the first sub-section 211 and the second sub-section 212. Therefore, the first sub-section 211 and the second sub-section 212 are conductively connected in the terminal region 20a through the first gate connection portion 230, and the second conductive plug 320 can be conductively connected to the first sub-section 211 and the second sub-section 212 through the first gate connection portion 230 to provide a gate voltage therefor, so that the channel can be formed smoothly, ensuring the function of the real unit. In addition, the first gap dielectric layer 430 is set to be located directly above the second conductive type column 120 to prevent the first gap dielectric layer 430 from extending to the first type well region 131, affecting the formation of the channel, and further affecting the device performance.

[0089] The second sub-portion 212 of one first gate portion 210 is electrically connected to the first sub-portion 211 of another first gate portion 210 at the terminal region 20a through the first gate connection portion 230, which is conducive to the parallel connection of different real units. In this case, the first gate connection portion 230 will cross the virtual unit when connecting two real units. Please refer to Fig.12 The first gap dielectric layer 430 may also be disposed between the first gate connecting portion 230 and the second gate portion 220 to ensure insulation isolation between the first gate portion 210 and the second gate portion 220 .

[0090] Please refer to Figure 2 , Figures 13 to 16 In some optional specific examples, the device further includes: a first through-groove 600 passing through the gate 200, the first conductive plug 310 is located in the first through-groove 600, and the first through-groove 600 is also filled with a second gap dielectric layer 440; in a plane parallel to the upper surface 101, the first conductive type columns 110 and the second conductive type columns 120 are alternately arranged along the first direction, and the first through-groove 600 extends along the second direction, and the second direction is perpendicular to the first direction; along the second direction, a portion of the first type well region 131 is in contact with the first conductive plug 310, and a portion is in contact with the second gap dielectric layer 440. Figures 13 to 16 and Figure 3By comparison, it can be understood that, compared with the first type well region 131 being entirely in contact with the first conductive plug 310, a portion of the first type well region 131 is in contact with the first conductive plug 310 and a portion is in contact with the second gap dielectric layer 440, so that the area of ​​the first conductive plug 310 is reduced, thereby reducing the area of ​​the conductive region. At this time, the portion of the real unit in contact with the first conductive plug 310 is actually conductive, and the portion of the real unit in contact with the second gap dielectric layer 440 will be conductive under the influence of other portions, which can be understood as indirect conduction. Then, when the first conductive plug 310 is powered on, the current conduction speed of the indirect conductive portion of the real unit is slower, thereby further extending the depletion time, slowing down the downward trend of Cgd, increasing the Cgd of the device, and improving the device's anti-electromagnetic interference capability.

[0091] For further information, please refer to Fig.13 and Fig.14 , the first conductive plug 310 and the second gap dielectric layer 440 are distributed in the same position in two adjacent first through slots 600; or, please refer to Fig.15 and Fig.16 , the distribution positions of the first conductive plug 310 and the second gap dielectric layer 440 in the two adjacent first through slots 600 are opposite to each other. Thus, while reducing the area of ​​the conductive region, the conductive region distribution of the two adjacent real units is made to be the same or opposite, presenting an axisymmetric distribution or a center-symmetric distribution, which plays a role in uniform current flow to ensure the performance of the device.

[0092] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A superjunction semiconductor device, characterized in that: include: a semiconductor material layer including an upper surface and a lower surface opposite to each other; A super junction structure, located in the semiconductor material layer, the super junction structure comprising a plurality of first conductivity type columns and second conductivity type columns arranged alternately; A first conductive type well region, located in the semiconductor material layer and located at the top of the first conductive type column, the first conductive type well region includes a first type well region and a second type well region, and the first type well region and the second type well region respectively correspond to different first conductive type columns; a gate, located on the upper surface of the semiconductor material layer; A first conductive plug, passing through the gate and conductively connected to the first type well region; A second conductive plug, located on the gate and conductively connected to the gate; The second-type well region is covered by the gate, and the second-type well region is insulated and isolated from the first conductive plug and the second conductive plug; the first-type well region and the second-type well region both extend from the core region to the terminal region of the superjunction semiconductor device, and the second-type well region and the first-type well region are separately arranged at any position.

2. The superjunction semiconductor device according to claim 1, characterized in that: Also includes: a dielectric layer, located between the gate and the upper surface of the semiconductor material layer; The gate includes a first gate portion located directly above the first type of well region and a second gate portion located directly above the second type of well region, and the average thickness of the portion of the dielectric layer located between the second gate portion and the second type of well region is greater than the average thickness of the portion located between the first gate portion and the first type of well region.

3. The superjunction semiconductor device according to claim 2, characterized in that: The dielectric layer includes a gate dielectric layer and an isolation dielectric layer. The gate dielectric layer is located between the first type well region and the first gate portion and between the second type well region and the second gate portion. The isolation dielectric layer is located between the second type well region and the gate dielectric layer.

4. The superjunction semiconductor device according to claim 2 or 3, characterized in that: The gate further includes a first gate connection portion located in the terminal region, and the first gate portion and the second gate portion are conductively connected in the terminal region through the first gate connection portion.

5. The superjunction semiconductor device according to claim 4, characterized in that: The gate further includes a second gate connection portion located in the core region, the second gate connection portion being located directly above the second conductive type column; The first gate portion includes a first sub-portion and a second sub-portion separated by the first conductive plug in the core region, and the first sub-portion and the second sub-portion are conductively connected in the terminal region through the first gate connecting portion; For two first gate portions adjacent to the same second gate portion and respectively located on both sides of the second gate portion, the second sub-portion of one first gate portion is connected to the second gate portion via a second gate connecting portion, and the first sub-portion of the other first gate portion is connected to the second gate portion via another second gate connecting portion.

6. The superjunction semiconductor device according to claim 1, characterized in that: The gate includes a first gate portion located directly above the first type well region and a second gate portion located directly above the second type well region, and the first gate portion is insulated and isolated from the second gate portion.

7. The superjunction semiconductor device according to claim 6, characterized in that: The gate further includes a first gate connection portion located in the terminal region; The first gate portion includes a first sub-portion and a second sub-portion separated by the first conductive plug in the core region, and the first sub-portion and the second sub-portion are conductively connected in the terminal region through the first gate connecting portion; For two first gate portions adjacent to the same second gate portion and respectively located on both sides of the second gate portion, a first gap dielectric layer exists between the second sub-portion of one first gate portion and the second gate portion, another first gap dielectric layer exists between the first sub-portion of the other first gate portion and the second gate portion, and each of the first gap dielectric layers is respectively located directly above a different second conductive type column; The second sub-portion of one of the first gate portions is conductively connected to the first sub-portion of the other first gate portion in the terminal region through the first gate connecting portion.

8. The superjunction semiconductor device according to claim 1, characterized in that: Also includes: A source region, located in the first type of well region; The source region is not disposed in the second-type well region.

9. The superjunction semiconductor device according to claim 1, characterized in that: Also includes: A first through-groove passing through the gate, the first conductive plug being located in the first through-groove, and the first through-groove being further filled with a second gap dielectric layer; In a plane parallel to the upper surface, the first conductive type columns and the second conductive type columns are alternately arranged along a first direction, and the first through grooves extend along a second direction, and the second direction is perpendicular to the first direction; along the second direction, a portion of the first type of well region is in contact with the first conductive plug, and a portion is in contact with the second gap dielectric layer.

10. The superjunction semiconductor device according to claim 9, characterized in that: The first conductive plug and the second gap dielectric layer are distributed in the same position in two adjacent first through grooves; or, The distribution positions of the first conductive plug and the second gap dielectric layer in two adjacent first through grooves are opposite to each other.

Images